ADC1010S NXP | Alldatasheet
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Technical content
- General description The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1010S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1010S is ideal for use in communications, imaging and medical applications. 2. Features and benefits 3. Applications ADC1010S series Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 01 — 9 April 2010 Preliminary data sheet SNR, 62 dBFS; SFDR, 86 dBc Input bandwidth, 600 MHz Sample rate up to 125 Msps Power dissipation, 430 mW at 80 Msps 10-bit pipelined ADC core Serial Peripheral Interface (SPI) Clock input divider by 2 for less jitter contribution Duty cycle stabilizer Single 3 V supply Fast OuT of Range (OTR) detection Flexible input voltage range: 1 V p-p to 2V p - p INL ±0.07 LSB, DNL ±0.04 LSB CMOS or LVDS DDR digital outputs Offset binary, two’s complement, gray code Pin compatible with the ADC1410S series and the ADC1210S series Power-down and Sleep modes HVQFN40 package Wireless and wired broadband communications Portable instrumentation Spectral analysis Imaging systems Ultrasound equipment Software define radio
Table 1. Ordering information
6.1 Pinning
6.2 Pin description
Table 2. Pin description (CMOS digital outputs)
15 I output enable, active LOW
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
38 I SPI chip select
Table 3. Pin description (L VDS/DDR) digital outputs)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 5. Thermal characteristics
Table 6. Static characteristics [1]
CMOS and LVDS interface; unless otherwise specified. Table 6. Static characteristics [1] …continued
10.1 Dynamic characteristics
Table 7. Dynamic characteristics [1]
at VDDA =3V , VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Table 7. Dynamic characteristics [1] …continued
10.2 Clock and digital output timing
Tamb = −40 °Ct o+ 8 5°Ca tV DDA =3V , VDDO = 1.8 V; VINP − VINM = −1 dBFS; unless otherwise specified. [2] Measured between 20 % to 80 % of V DDO. [3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. Table 8. Clock and digital outp ut timing characteristics[1]
Preliminary data sheet Rev. 01 — 9 April 2010 11 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs Fig 4. CMOS mode timing Fig 5. LDVS DDR mode timing (N − 12) td(s) tclk N N + 1 N + 2 tclk tsu tPD th tPD CLKP CLKM DATA DAV 005aaa060 005aaa061 (N − 14) td(s) tclk N N + 1 N + 2 CLKP CLKM DAVP DAVM tsu th thtsu tPD tPD Dx_Dx + 1_P Dx_Dx + 1_M Dx Dx + 1 Dx + 1 Dx + 1 Dx + 1 Dx + 1Dx Dx DxDx tclk
10.3 SPI timings
11.1 Device control
The ADC1010S can be controlled via SPI or directly via the I/O pins (PIN control mode).
11.1.1 SPI and Pin control modes
control mode is illustrated in Figure 7. Table 9. SPI timings characteristics
11.1.2 Operating mode selection
11.1.3 Selecting the output data standard
HIGH, otherwise CMOS is selected.
11.1.4 Selecting the output data format
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1010S supports differential or single-ended input drive. voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. via a programmable internal reference (see Section 11.3 and Table 22 further details). Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8. Table 10. Operating mode selection via pin PWD and OE
Preliminary data sheet Rev. 01 — 9 April 2010 14 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 9) is needed to counteract the effects of a charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Fig 8. Input sampling circuit 005aaa043 INP Package ESD Parasitics Switch Ron = 15 Ω 4 pF 4 pF Sampling capacitor Sampling capacitor Switch Ron = 15 Ω INM Internal clock Internal clock Fig 9. Anti-kickback circuit 005aaa073 R R C INP INM
11.2.3 Transformer
configuration shown in Figure 10 would be suitable for a baseband application. Table 11. RC coupling versus input frequency - typical values
3 MHz 25 Ω 12 pF
70 MHz 12 Ω 8 pF
170 MHz 12 Ω 8 pF
11.3 System reference and power management
11.3.1 Internal/external references
reference is also possible by providing a voltage on pin VREF as described in Figure 15. externally as detailed in Table 12. [1] The voltage on pin VREF is doubled internally to generate the internal reference voltage. Table 12. Reference selection
0 AGND 330 pF capacitor to AGND 2 V
0.5 V and 1 V[1]
1 V to 2 V
required reference voltage source.
11.3.2 Reference gain control
Table 13. Reference SPI gain control
Preliminary data sheet Rev. 01 — 9 April 2010 18 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs
11.3.3 Common-mode output voltage (V O(cm))
A 0.1 μF filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point.
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.
11.4 Clock input
11.4.1 Drive modes
The ADC1010S can be driven differentially (SINE, LVPECL or LVDS) with little or no influence on the dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). Fig 17. Equivalent schematic of the common-mode reference circuit 1.5 V VCM 0.1 μF PACKAGE ESD PARASITICS 005aaa051 COMMON MODE REFERENCE ADC CORE a. Rising edge LVCMOS b. Falling edge LVCMOS Fig 18. LVCMOS single-ended clock input LVCMOS clock input CLKP CLKM 005aaa174 005aaa053 LVCMOS clock input CLKP CLKM
Preliminary data sheet Rev. 01 — 9 April 2010 19 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 20. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. a. Sine clock input b. Sine clock input (with transformer) c. LVDS clock input d. LVPECL clock input Fig 19. Differential clock input Sine clock input CLKP CLKM 005aaa173 Sine clock input CLKP CLKM 005aaa054 005aaa055 LVDS clock input CLKP CLKM LVPECL clock input 005aaa172 CLKP CLKM Fig 20. Equivalent input circuit CLKP CLKM 005aaa056 PACKAGE ESD PARASITICS 5 kΩ 5 kΩ Vcm(clk) SE_SEL SE_SEL
Preliminary data sheet Rev. 01 — 9 April 2010 20 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 21), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %.
11.4.4 Clock input divider
The ADC1010S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 21). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 23 Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 21. The buffer is powered by a separate power supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. Fig 21. CMOS digital output buffer VDDO ESD PACKAGEPARASITICS OGND Dx 005aaa057 50 ΩLOGIC DRIVER
Preliminary data sheet Rev. 01 — 9 April 2010 21 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 23). Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 22) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 23 and Table 32). The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATA[1:0]; see Table 31) in order to adjust the output logic voltage levels. Fig 22. LVDS DDR digital output buffer - externally terminated Fig 23. LVDS DDR digital output buffer - internally terminated VCCO 3.5 mA typ DnP/Dn + 1P DnM/Dn + 1M OGND 100 Ω 005aaa058 + − RECEIVER VCCO OGND 005aaa059 DxP/Dx + 1P DxM/Dx + 1M 100 Ω 3.5 mA typ + − + − RECEIVER
11.5.3 Data valid (DAV) output clock
Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
11.5.5 Digital offset
By default, the ADC1010S delivers output code that corresponds to the analog input. DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
Table 14. LVDS DDR output register 2 Table 15. Fast OTR register
11.5.7 Output codes versus input voltage
11.6 Serial peripheral interface
11.6.1 Register description
registers that control the operation of the chip. bytes is determined by the value of bits W1 and W2 (see Table 18). [1] Bit R/W indicates whether it is a read (1) or a write (0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18). Table 16. Output codes Table 17. Instruction bytes for the SPI
is increased to access subsequent addresses.
- A falling edge on CS in combination with a rising edge on SCLK determine the start of
- The first phase is the transfer of the 2-byte instruction.
- The second phase is the transfer of the da ta which can vary in length but will always
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). indicates the end on data transmission.
11.6.2 Default modes at start-up
selected. At power-up, the device enters Pin control mode. can be changed via bit LVDS/CMOS in Table 23. DATA_FORMAT[1:0] in Table 23. Table 18. Number of data bytes to be transferred after the instruction bytes
Preliminary data sheet Rev. 01 — 9 April 2010 25 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS CS SDIO (CMOS LVDS DDR) SCLK (Data format) Offset binary, LVDS DDR default mode at start-up 005aaa063 SDIO (CMOS LVDS DDR) SCLK (Data format) two's complement, CMOS default mode at start-up 005aaa064 CS
11.6.3 Register allocation map
Table 19. Register allocation map
0005 Reset and
0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000
0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000
0011 Output data
0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000
0013 Offset R/W - - DIG_OFFSET[5:0] 0000
0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000
0015 Test pattern 2 R/W TESTPAT_USER[9:2] 0000
0016 Test pattern 3 R/W TESTPAT_
0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000
0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000
0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN DAVI[1:0] DATAI_
0022 LVDS DDR O/P 2 R/W - - - - BIT_BYTE_WISE LVDS_INT_TER[2:0] 0000
Table 20. Reset and operating mode control register (address 0005h) bit description
7 SW_RST R/W reset digital section
Table 21. Clock control register (address 0006h) bit description
4 SE_SEL R/W single-ended clock input pin select
0 CLKM
3 DIFF_SE R/W differential/single ended clock input select
1 CLKDIV R/W clock input divide by 2
0 DCS_EN R/W duty cycle stabilizer
Table 22. Internal reference control register (address 0008h) bit description
3 INTREF_EN R/W programmable internal reference enable
Table 23. Output data standard control register (address 0011h) bit description
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
2 OUTBUS_SWAP R/W output bus swapping
Table 24. Output clock register (address 0012h) bit description
3 DAVINV R/W output clock data valid (DAV) polarity
Table 25. Offset register (add ress 0013h) bit description Table 26. Test pattern register 1 (address 0014h) bit description Table 27. Test pattern register 2 (address 0015h) bit description
Table 28. Test pattern register 3 (address 0016h) bit description Table 29. Fast OTR register (address 0017h) bit description
3 FASTOTR R/W fast Out-of-Range (OTR) detection
Table 30. CMOS output register (address 0020h) bit description
Table 31. LVDS DDR output register 1 (address 0021h) bit description
5 DAVI_x2_EN R/W double LVDS current for DAV LVDS buffer
2 DATAI_x2_EN R/W double LVDS current for DATA LVDS buffer
Table 32. LVDS DDR output register 2 (address 0022h) bit description
3 BIT_BYTE_WISE R/W DDR mode for LVDS output
Preliminary data sheet Rev. 01 — 9 April 2010 32 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs 12. Package outline Fig 27. Package outline SOT618-6 (HVQFN40) ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT618-6 - - - MO-220 sot618-6_po Unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.30 0.21 0.18 0.2 6.1 6.0 5.9 6.1 6.0 5.9 0.5 0.1 0.05 A (1) Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-6 A1 bc D (1) 0.1 y1Dh 4.55 4.40 4.25 E (1) Eh 4.55 4.40 4.25 ee 4.5 4.5 L 0.5 0.4 0.3 vw 0.05 y 0 2.5 5 mm scale terminal 1 index area terminal 1 index area BD A E b e AC Bv Cw11 20 e Dh 3140 Eh L C yCy1 X c detail X A1A 1/2 e 1/2 e 09-02-23 09-03-04
Table 33. Revision history
Preliminary data sheet Rev. 01 — 9 April 2010 34 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs 14. Legal information
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14.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Preliminary data sheet Rev. 01 — 9 April 2010 35 of 36 NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
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NXP Semiconductors ADC1010S series ADC1010S series; CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 April 2010 Document identifier: ADC1010S_SER_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 16. Contents 11.3 System reference and power management . . 16