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General description The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1010S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, because of a separate digital output supply. It supports the Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a programmable full-scale SPI to allow a flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1010S is ideal for use in communications, imaging and medical applications. 2. Features and benefits 3. Applications ADC1010S series Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 03 — 2 July 2012 Product data sheet  SNR, 62 dBFS; SFDR, 86 dBc  Input bandwidth, 600 MHz  Sample rate up to 125 Msps  Power dissipation, 430 mW at 80 Msps  10-bit pipelined ADC core  Serial Peripheral Interface (SPI)  Clock input divided by 2 for less jitter  Duty cycle stabilizer  Single 3 V supply  Fast OuT-of-Range (OTR) detection  Flexible input voltage range: 1 V (p-p) to

2 V (p-p)

 Offset binary, two’s complement, gray code  CMOS or LVDS DDR digital outputs  Power-down and Sleep modes  Pin compatible with the ADC1410S series and the ADC1210S series  HVQFN40 package  Wireless and wired broadband communications  Portable instrumentation  Spectral analysis  Imaging systems  Ultrasound equipment  Software defined radio

6.1 Pinning

6.2 Pin description

Table 2. Pin description (CMOS digital outputs)

15 I output enable, active LOW

38 I SPI chip select

Table 3. Pin description (LVDS DDR) digital outputs)

ADC1010S_SER 3 © IDT 2012. All rights reserved. [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2). [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. [1] Value for six layers board in still ai r with a minimum of 25 thermal vias. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 5. Thermal characteristics

10.1 Dynamic characteristics

Table 7. Dynamic characteristics [1]

10.2 Clock and digital output timing

Table 7. Dynamic characteristics [1] …continued Table 8. Clock input and digital output timing characteristics[1]

ADC1010S_SER 3 © IDT 2012. All rights reserved. at VDDA =3V , VDDO = 1.8 V; VINP  VINM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. [2] Measured between 20 % to 80 % of V DDO. [3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV. Table 8. Clock input and digital output timing characteristics[1] …continued

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 11 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs Fig 4. CMOS mode and clock timing Fig 5. LDVS DDR mode and clock timing (N − 12) td(s) tclk N N + 1 N + 2 tclk tsu tPD th tPD CLKP CLKM DATA DAV 005aaa060 005aaa061 (N − 14) td(s) tclk N N + 1 N + 2 CLKP CLKM DAVP DAVM tsu th thtsu tPD tPD Dx_Dx + 1_P Dx_Dx + 1_M Dx Dx + 1 Dx + 1 Dx + 1 Dx + 1 Dx + 1Dx Dx DxDx tclk

10.3 SPI timings

Table 9. SPI timings characterist ics[1]

10.4 Typical characteristics

Fig 7. Capacitance as a function of frequency Fig 8. Resistance as a function of frequency f (MHz) 50 550 450250 350150 001aam619 2.8 2.6 3.0 3.2 C (pF) 2.4 f (MHz) 50 550 450250 350150 001aam614 R (kΩ) T=2 5 C; VDD =3V ; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off T=2 5 C; V DD =3V ; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off Fig 9. SFDR as a function of duty cycle ( ) Fig 10. SNR as a function of duty cycle ( ) δ (%) 10 90 7030 50 001aam616 100 SFDR (dBc) (1) (2) δ (%) 10 90 7030 50 001aam615 SNR (dBFS) (1) (2)

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 14 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs (1) T amb = 40 C/typical supply voltages (2) T amb =+ 2 5C/typical supply voltages (3) T amb =+ 9 0C/typical supply voltages (1) T amb = 40 C/typical supply voltages (2) T amb =+ 2 5C/typical supply voltages (3) T amb =+ 9 0C/typical supply voltages Fig 11. SFDR as a function of duty cycle ( ) Fig 12. SNR as a function of duty cycle ( ) δ (%) 10 90 7030 50 001aam617 SFDR (dBc) (1) (2) (3) δ (%) 10 90 7030 50 001aam618 SNR (dBFS) (1) (2) (3) Fig 13. SFDR as a function of common-mode input voltage (VI(cm)) Fig 14. SNR as a function of common-mode input voltage (VI(cm)) VI(cm) (V) 001aam659 SFDR (dBc) VI(cm) (V) 001aam660 SNR (dBFS)

11.1 Device control

The ADC1010S can be controlled via SPI or directly via the I/O pins (Pin control mode).

11.1.1 SPI and Pin control modes

control mode is illustrated in Figure 15.

11.1.2 Operating mode selection

11.1.3 Selecting the output data standard

ODS is HIGH, otherwise CMOS is selected. Table 10. Operating mode selection via pin PWD and OE

11.1.4 Selecting the output data format

The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected.

11.2 Analog inputs

11.2.1 Input stage

The analog input of the ADC1010S supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 22). The equivalent circuit of the sample and hold input stage, including Electrostatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core.

11.2.2 Anti-kickback circuitry

Anti-kickback circuitry (R-C filter in Figure 17) is needed to counteract the effects of a charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. Fig 16. Input sampling circuit 005aaa043 INP Package ESD Parasitics Switch Ron = 15 Ω 4 pF 4 pF Sampling capacitor Sampling capacitor Switch Ron = 15 Ω INM Internal clock Internal clock

11.2.3 Transformer

configuration shown in Figure 18 would be suitable for a baseband application. both cases, the choice of transformer is a compromise between cost and performance. Table 11. RC coupling versus input frequency - typical values

3 MHz 25  12 pF

70 MHz 12  8 pF

170 MHz 12  8 pF

11.3 System reference and power management

11.3.1 Internal/external references

The ADC1010S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1; see Table 22). See Figure 21 to Figure 24. The equivalent reference circuit is shown in Figure 20. An external reference is also possible by providing a voltage on pin VREF as described in Figure 23. Fig 19. Dual transformer configuration suitable for a high intermediate frequency application 005aaa045 100 nF100 nF 100 nF 100 nF 12 Ω 12 Ω 8.2 pF INP INM VCM 50 Ω 50 Ω 50 Ω 50 Ω ADT1-1WTADT1-1WT analog input

ADC1010S_SER 3 © IDT 2012. All rights reserved. externally as detailed in Table 12. [1] The voltage on pin VREF is doubled internally to generate the internal reference voltage. required reference voltage source. Table 12. Reference selection

0 AGND 330 pF capacitor to AGND 2 V

0.5 V and 1 V[1]

1 V to 2 V

11.3.2 Programmable full-scale

Table 13. Reference SPI gain control

11.3.3 Common-mode output voltage (V O(cm))

A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point.

11.3.4 Biasing

The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.

11.4 Clock input

11.4.1 Drive modes

The ADC1010S can be driven differentially (LVPECL). It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor). Fig 25. Equivalent schematic of the common-mode reference circuit 1.5 V VCM 0.1 μF package ESD parasitics 005aaa051 COMMON-MODE REFERENCE ADC core a. Rising edge LVCMOS b. Falling edge LVCMOS Fig 26. LVCMOS single-ended clock input LVCMOS clock input CLKP CLKM 005aaa174 005aaa053 LVCMOS clock input CLKP CLKM

11.4.2 Equivalent input circuit

The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode voltage of the differential input stage is set via internal 5 k resistors. a. Sine clock input b. Sine clock input (with transformer) c. LVPECL clock input Fig 27. Differential clock input Sine clock input CLKP CLKM 005aaa173 Sine clock input CLKP CLKM 005aaa054 LVPECL clock input 005aaa172 CLKP CLKM Vcm(clk) = common-mode voltage of the differential input stage. Fig 28. Equivalent input circuit CLKP CLKM 005aaa056 Package ESD Parasitics 5 kΩ 5 kΩ Vcm(clk) SE_SEL SE_SEL

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 23 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor.

11.4.3 Duty cycle stabilizer

The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 21), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %.

11.4.4 Clock input divider

The ADC1010S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see Table 21). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed.

11.5 Digital outputs

11.5.1 Digital output buffers: CMOS mode

The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 29. The buffer is powered by a separate power supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. Fig 29. CMOS digital output buffer VDDO ESD PackageParasitics OGND Dx 005aaa057 50 ΩLOGIC DRIVER

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 24 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs The output resistance is 50  and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30):

11.5.2 Digital output buffers: LVDS DDR mode

The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic 1 (see Table 23). Each output should be terminated externally with a 100  resistor (typical) at the receiver side (Figure 30) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and Table 32). The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATA[1:0]; see Table 31) in order to adjust the output logic voltage levels. Fig 30. LVDS DDR digital output buffer - externally terminated Fig 31. LVDS DDR digital output buffer - internally terminated VDDO 3.5 mA typ DxP/Dx + 1P DxM/Dx + 1M OGND 100 Ω 005aaa058 + − RECEIVER VDDO OGND 005aaa059 DxP/Dx + 1P DxM/Dx + 1M 100 Ω 3.5 mA typ + − + − RECEIVER

11.5.3 DAta Valid (DAV) output clock

Figure 4 and Figure 5 respectively.

11.5.4 OuT-of-Range (OTR)

programmed via bits FASTOTR_DET[2:0].

11.5.5 Digital offset

By default, the ADC1010S delivers output code that corresponds to the analog input. DIG_OFFSET[5:0]; see Table 25).

11.5.6 Test patterns

regardless of the analog input. Table 14. LVDS DDR output register 2 Table 15. Fast OTR register

11.5.7 Output codes versus input voltage

11.6 Serial peripheral interface

11.6.1 Register description

registers that control the operation of the chip. is determined by the value of bits W1 and W2 (see Table 18). [1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18). Table 16. Output codes Table 17. Instruction bytes for the SPI

A falling edge on CS in combination with a rising edge on SCLK determine the start of
The first phase is the transfer of the 2-byte instruction.
The second phase is the transfer of the data which can vary in length but is always a

multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). indicates the end of data transmission.

11.6.2 Default modes at start-up

selected. At power-up, the device enters Pin control mode. can be changed via bit LVDS_CMOS in Table 23. DATA_FORMAT[1:0] in Table 23. Table 18. Number of data bytes to be transferred after the instruction bytes

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 28 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS CS SDIO (CMOS LVDS DDR) SCLK (Data format) Offset binary, LVDS DDR default mode at start-up 005aaa063 SDIO (CMOS LVDS DDR) SCLK (Data format) two's complement, CMOS default mode at start-up 005aaa064 CS

11.6.3 Register allocation map

Table 19. Register allocation map

0005 Reset and

0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000

0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000

0011 Output data

0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000

0013 Offset R/W - - DIG_OFFSET[5:0] 0000

0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000

0015 Test pattern 2 R/W TESTPAT_USER[9:2] 0000

0016 Test pattern 3 R/W TESTPAT_

0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000

0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000

0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN DAVI[1:0] DATAI_

0022 LVDS DDR O/P 2 R/W - - - - BIT_ BYTE_WISE LVDS_INT _TER[2:0] 0000

7 SW_RST R/W reset digital section

Table 21. Clock control register (address 0006h) bit description Default values are highlighted.

4 SE_SEL R/W single-ended clock input pin select

3 DIFF_SE R/W differential/single ended clock input select

1 CLKDIV R/W clock input divide by 2

0 DCS_EN R/W duty cycle stabilizer

3 INTREF_EN R/W programmable internal reference enable

000 FS = 2 V

110 FS = 1 V

Table 23. Output data standard control register (address 0011h) bit description Default values are highlighted.

4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS

1 LVDS DDR

3 OUTBUF R/W output buffers enable

2 OUTBUS_SWAP R/W output bus swapping

3 DAVINV R/W output clock data valid (DAV) polarity

Table 25. Offset register (add ress 0013h) bit description Default values are highlighted. Table 26. Test pattern register 1 (address 0014h) bit description Default values are highlighted.

ADC1010S_SER 3 © IDT 2012. All rights reserved. Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted. Table 29. Fast OTR register (address 0017h) bit description Default values are highlighted.

3 FASTOTR R/W fast OuT-of-Range (OTR) detection

Table 30. CMOS output register (address 0020h) bit description Default values are highlighted.

5 DAVI_x2_EN R/W double LVDS current for DAV LVDS buffer

2 DATAI_x2_EN R/W double LVDS current for DATA LVDS buffer

Table 32. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted.

3 BIT_BYTE_WISE R/W DDR mode for LVDS output

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 35 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs 12. Package outline Fig 35. Package outline SOT618-1 (HVQFN40) terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 6.1 5.9 Dh 4.25 3.95 6.1 5.9 4.25 3.95 4.5 4.50.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT618-1 HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A(1) max. A c detail X yy1 Ce L Eh Dh e b 11 20 40 31 2110 X D E C B A 01-08-08 02-10-22 terminal 1 index area 1/2 e 1/2 e AC C Bv M w M Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) E(1)

Data sheet status changed from Preliminary to Product.
Text and drawings updated throughout entire data sheet.
SOT618-6 changed to SOT618-1. See Table 1 “Ordering information” and Figure 35 “Package outline SOT618-1 (HVQFN40)”.
Section 10.4 “Typical characteristics” added to the data sheet. ADC1010S_SER_1 20100409 Preliminary data sheet - -

ADC1010S_SER 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 37 of 37 Integrated Device Technology ADC1010S series Single 10-bit ADC; CMOS or LVDS DDR digital outputs 15. Contents 11.3 System reference and power management . . 18

11.3.3 Common-mode output voltage (V

Product Information

ADC1010S specifications and overview.

Summary

Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

Description

Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

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