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General description The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features n 10-bit resolution n Sampling rate up to 70 MHz n −3 dB bandwidth of 245 MHz n 5 V power supplies and 3.3 V output power supply n Binary or two’s complement CMOS outputs n In-range CMOS compatible output n TTL and CMOS compatible static digital inputs n TTL and CMOS compatible digital outputs n Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible n Power dissipation 550 mW (typical) n Low analog input capacitance (typical 2 pF), no buffer ampliﬁer required n Integrated sample-and-hold ampliﬁer n Differential analog input n External amplitude range control n Voltage controlled regulator included n −40 °C to +85°C ambient temperature 3. Applications High-speed analog-to-digital conversion for: n Cellular infrastructure n Professional telecommunication n Digital radio n Radar n Medical imaging n Fixed network n Cable modem ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 02 — 12 August 2008 Product data sheet

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 3 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 6. Block diagram Fig 1. Block diagram 014aaa464 MSB data outputs VREF FSREF SH DEC CMADC 6 to 10, 13, 14, 16, 31, 32n.c. D0 LSB VCCO IR CMOS OUTPUTS LATCHESANALOG-TO-DIGITAL CONVERTER CLOCK DRIVER VCCD2 VCCD1 VCCA4 VCCA3 VCCA1 CLK CLKN CMOS OUTPUT OGND OVERFLOW/ UNDERFLOW LATCH VREF REFERENCE CMADC REFERENCE CEOTC ADC1006S055/070 DGND2 DGND1 AGND4 AGND3 AGND1 INN IN AMP s sample - and - hold

7.1 Pinning

7.2 Pin description

Table 3. Pin description

0.3 V CCA V

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. the supply voltage differencesΔVCC are respected. Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Table 5. Thermal characteristics Table 6. Characteristics and VCCO = 3.3 V, Tamb =2 5°C and CL = 10 pF; unless otherwise speciﬁed.

0.5 V and VCCO

and VCCO = 3.3 V, Tamb =2 5°C and CL = 10 pF; unless otherwise speciﬁed.

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. a) PECL mode 1: (DC level vary 1 : 1 with VCCD ) CLK and CLKN inputs are at differential PECL levels. signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. to be connected to the ground. [4] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. where α 1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; seeFigure6. [6] Signal-to-noise ratio (S/N) takes into account all harmonics above ﬁve and noise up to Nyquist frequency; seeFigure8. same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. [9] Output data acquisition: the output data is available after the maximum delay of td(o); seeFigure3. and VCCO = 3.3 V, Tamb =2 5°C and CL = 10 pF; unless otherwise speciﬁed.

Additional information relating toTable6

[1] Two’s complement reference is inverted MSB. Table 7. Output coding with differential inputs (typical values to AGND); Table 8. Mode selection Table 9. Sample-and-hold selection

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 13 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Fig 3. Timing diagram (1) frequency on pinCE = 100 kHz. Fig 4. Timing diagram and test conditions of 3-state output delay time sample N + 1sample N CLK 014aaa465 sample N + 2 sample N + 1sample N sample N + 2 tw(clk)L tw(clk)H DATA D0 TO D9 HIGH 50 % LOW HIGH 50 % LOW IN td(s) th(o) td(o) DATA N - 2 DATA N - 1 DATA N DATA N + 1 014aaa443 50 % 50 % HIGH LOW tdZHtdHZ 50 % HIGH LOW tdZLtdLZ 10 % 90 % output data VCCD output data 3.3 kW 15 pF VCCO ADC1006S 070 CE TEST tdLZ tdZL tdHZ VCCO VCCO OGND OGNDtdZH 0 V CE

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 14 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz (1) 55 MHz. (2) 70 MHz. (1) 55 MHz. (2) 70 MHz. Fig 5. Effective Number Of Bits (ENOB) as a function of input frequency (sample device) Fig 6. Total Harmonic Distortion (THD) as a function of input frequency (sample device) fi (MHz) 02 5 2010 155 014aaa444 9.50 9.40 9.60 9.70 ENOB (bit) 9.30 (1) (2) fi (MHz) 02 5 2010 155 014aaa445 -67 -69 -65 -63 THD (dB) -71 (1) (2) (1) 55 MHz. (2) 70 MHz. (1) 55 MHz. (2) 70 MHz. Fig 7. Spurious Free Dynamic Range (SFDR) as a function of input frequency (sample device) Fig 8. Signal-to-Noise Ratio (S/N) as a function of input frequency (sample device) fi (MHz) 02 5 2010 155 014aaa446 SFDR (dB) (1) (2) fi (MHz) 02 5 2010 155 014aaa447 59.4 59.6 59.2 59.8 60.0 S/N (dB) 59.0 (1) (2)

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 15 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Fig 9. Single-tone; fi= 20 MHz; fclk= 55 MHz 014aaa448 -80 -120 -40 power spectrum (dB) -160 fi (MHz) 0 3020105 2515 Fig 10. Two-tone; fi1 = 20 MHz; fi 2 = 20.1 MHz; fclk=5 5M H z 014aaa449 -80 -120 -40 power spectrum (dB) -160 fi (MHz) 0 3020105 2515

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 16 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Fig 11. Integral Non-Linearity (INL) output code 0 1024768512256 014aaa450 -0.60 0.60 0.20 -0.20 1.00 output range (INL) Fig 12. Differential Non-Linearity (DNL) output code 0 1024768512256 014aaa451 0.10 -0.10 0.20 0.30 DNL (LSB) -0.20

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 17 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz (1) fi= 4.43 MHz. (2) fi= 20 MHz. (3) SFDR = 80 dB. Fig 13. SFDR as a function of input amplitude; Vi(IN)(p-p)− Vi(INN)(p-p)= 1.9 V; fclk= 40 MHz Input amplitude (dBFS) 014aaa452 SFDR (dBFS) (1) (2) (3) (1) fi= 4.43 MHz. (2) fi= 20 MHz. (3) SFDR = 80 dB. Fig 14. SFDR as a function of input amplitude; Vi(IN)(p-p)− Vi(INN)(p-p)= 1.9 V; fclk= 55 MHz Input amplitude (dBFS) 014aaa453 SFDR (dBFS) (1) (2) (3)

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 18 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz (1) SFDR. (2) ENOB. (3) S/N. Fig 15. SFDR, ENOB and S/N as a function of VCCA − VVREF ; fclk= 55 MHz; fi=2 0M H z Fig 16. ADC full-scale; VI(IN)(p-p)− VI(INN)(p-p) as a function of VCCA − VVREF VCCA - VVREF (V) 014aaa455 (dB) 8.0 7.0 9.0 10.0 7.5 6.5 8.5 9.5 (bit) 6.0 (1) (2) (3) 014aaa456VCCA - VVREF (V) 1.8 1.4 2.2 2.6 1.0 VI(IN)(p-p) VI(INN)(p-p) (V)

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 19 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 12. Application information

12.1 Application diagrams

The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator 014aaa457

100 W100 W

IN1 : 1 INN 5 V 100 nF 5 V 5 V SH mode CLK n.c. n.c. D0 (LSB) ADC1006S055/070 n.c. n.c. n.c. n.c. n.c. chip select input output format select (MSB) VREF 343536 3738394041424344 2221201918171615141312 014aaa458

270 W270 W

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 20 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Fig 19. Application diagram for TTL single-ended clock 014aaa459 ADC1006S CLKN CLKTTL input

12.2 Demonstration board

C8 is close to TR1 pin. Fig 20. Demonstration board schematic IC2 ADC1006S055/070 014aaa460 OGND CLKN CLK V CCD1 DGND1 SH AGND4 VCCA4 IN INN AGND1 VCCA VCCD VCCA VCC VCCO VCC CMADC VCCA1 VCC VCCA VCC VCCA VCC VCCO VCCO VCCA3 AGDN3 DEC n.c. n.c. n.c. n.c. n.c. VREF 33 32 31 30 29 28 27 26 25 24 23 123456789 1 0 1 1 VCCO n.c n.c IR CE OTC DGND2 n.c. V CCD2 n.c. n.c. FSREF MC78MO5CDT IN OUT ICI GND 24 B8 23B11 50 W 100 W FL3 FL1 FL2 C13 100 nF 330 nF C15 10 nF 100 W 5 kW FL4 10 nF C17 10 nF C19 22 mF (20 V) 4.7 mF (16 V) 1 mF TP2 TM3 4.7 kW 1 mF 62 W 2.4 KW 1 kW 1.2 kW C11 100 nF C18 10 nF 330 nF C12 100 nF C16 10 nF C10 100 nF PMBT 2222A BZV55C3V6 C14 100 nF 330 nF 100 W BYD17G CLK2 CLK1 CLK1 IN 220 nF MCLT1_6T_KK81 TR1 CMADC

12 V 1 3

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 22 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Fig 21. Component placement (top side) Fig 22. Component placement (underside) 014aaa466 C4 C5 TP2 R2 R5 R7 R4 C11 C10 C14 112 23 C12 S3 S4 B5 B8 B11 FL4 FL2 TM3 TM2 TM1 IC1 IC2 TR1 014aaa467 FL1 FL3 C8C13 C17 C15 C19 C16 C18

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 23 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Fig 23. Printed-circuit board layout (top layer) Fig 24. Printed-circuit board layout (ground layer) 014aaa461 014aaa462

12.3 Alternative parts

12.4 Recommended companion chip

Table 10. Alternative parts

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 25 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 13. Support information

13.1 Deﬁnitions

13.1.1 Non-linearities

13.1.1.1 Integral Non-Linearity (INL)

It is deﬁned as the deviation of the transfer function from a best ﬁt straight line (linear regression computation). The INL of the code i is obtained from the equation: (1) where and S = slope of the ideal straight line = code width; i = code value.

13.1.1.2 Differential Non-Linearity (DNL)

It is the deviation in code width from the value of 1 LSB. (2) where

13.1.2 Dynamic parameters (single tone)

Figure26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft / fs = M / N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. INL i() V I i() V I ideal()– i0 2 n 1–()⋅= DNL i() V I i1+() V I i()– i0 2 n 2–()⋅= Fig 26. Spectrum of full-scale input sine wave with frequency ft a3 ak SFDR 014aaa440 fs/2measured output range (MHz) magnitude

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 26 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and ‘quantization noise’.

13.1.2.1 Signal-to-Noise And Distortion (SINAD)

The ratio of the output signal power to the noise and distortion power for a given sample rate and input frequency, excluding the DC component: (3)

13.1.2.2 Effective Number Of Bits (ENOB)

It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives:

13.1.2.3 Total Harmonic Distortion (THD)

The ratio of the power of the harmonics to the power of the fundamental. For k-1 harmonics the THD is: (4) where and The value of k is usually 6 (i.e. calculation of THD is done on the ﬁrst 5 harmonics).

13.1.2.4 Signal-to-Noise ratio (S/N)

The ratio of the output signal power to the noise power, excluding the harmonics and the DC component. (5)

13.1.2.5 Spurious Free Dynamic Range (SFDR)

The number SFDR speciﬁes available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic), excluding DC component. (6) SINAD dB[] 10 P signal P noise distortion+ ENOB SINAD dB [] 1.76()–() 6.02()⁄= THD dB[] 10= P harmonics P signal P harmonics α 2 2 α 3 α k ++= P signal α 1 S/N dB[] 10 P signal P noise SFDR dB[] 20 α 1

13.1.3 Intermodulation distortion

13.1.3.1 Spectral analysis (dual-tone)

From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd-order components) are deﬁned, as follows.

13.1.3.2 IMD2 (IMD3)

The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total IMD is given by: where, and is the power in the intermodulation component at frequency f

13.1.4 Noise Power Ratio (NPR)

When using a notch-ﬁltered broadband white-noise generator as the input to the ADC under test, the NPR is deﬁned as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set. Fig 27. Spectral analysis (dual-tone) IMD3 014aaa441 fs/2measured output range (MHz) magnitude IMD dB[] 10 P intermod P signal P intermod a im 2 ft1 ft2–() a im 2 ft1 ft2+() a im 2 ft1 2f t2–() a im 2 ft1 2f t2+() a im 2 2f t1 ft2–() a im 2 2f t1 ft2+()++ ++–= P signal a2 ft1() a2 ft2()+= a im 2 ft()

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 28 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 14. Package outline Fig 28. Package outline SOT307-2 (QFP44) UNIT A 1 A 2 A 3 bp cE (1) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 o o0.15 0.10.15 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 SOT307-2 97-08-01 03-02-25 D (1) (1)(1) 10.1 9.9 H D 12.9 12.3 EZ 1.2 0.8 D e E B c EH D ZD A Z E e v M A X 33 23 y θ A 1 A Lp detail X L (A )3 A 2 pin 1 index DH v M B bp bp w M w M 0 2.5 5 mm scale QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 A max. 2.1

Corrections made to titles inFigure13 and14.
Corrections made to note inFigure4. ADC1006S055_070_1 20080611 Product data sheet - -

ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 30 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data —The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 August 2008 Document identifier: ADC1006S055_070_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents

11 Additional information relating to

Table6 . . . 12

Product Information

ADC1006S070H specifications and overview.

Summary

Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 02-12 August 2008

Description

Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 02-12 August 2008

Source title ADC1006S070H Datasheet(PDF) - NXP Semiconductors

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