ADC1006S070 | DigiCamel IC Datasheet

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Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital Co nverters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features  10-bit resolution  Sa mpling rate up to 70 MHz  3 dB bandwidth of 245 MHz  5 V power supplies and 3.3 V output power supply  Bina ry or two’s complement CMOS outputs  In- range CMOS compatible output  TTL and CMOS compatible static digital inputs  TT L and CMOS compatible digital outputs  Dif ferential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible  Powe r dissipation 550 mW (typical)  L ow analog input capacitance (typical 2 pF), no buffer amplifier required  In tegrated sample-and-hold amplifier  Dif ferential analog input  Exte rnal amplitude range control  V oltage controlled regulator included  40 C t o +85 C a mbient temperature 3. Applications High-speed analog-to-digital conversion for:  Cellular infrastruc ture  Pr ofessional telecommunication  Digit al radio  Radar  Medical imaging  Fixed network  Ca ble modem

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 3 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 6. Block diagram 014aaa464 MSB data outputs VREF FSREF SH DEC CMADC 6 to 10, 13, 14, 16, 31, 32n.c. D0 LSB VCCO IR CMOS OUTPUTS LATCHESANALOG-TO-DIGITAL CONVERTER CLOCK DRIVER VCCD2 VCCD1 VCCA4 VCCA3 VCCA1 CLK CLKN CMOS OUTPUT OGND OVERFLOW/ UNDERFLOW LATCH VREF REFERENCE CMADC REFERENCE CEOTC ADC1006S055/070 DGND2 DGND1 AGND4 AGND3 AGND1 INN IN AMP s sample - and - hold Fig 1. Block diagram

7.1 Pinning

7.2 Pin description

Table 3. Pin description

0.3 VCCA V

ADC1006S055_070_3 © IDT 2012. All rights reserved. age differences VCC are respected. Table 5. Thermal characteristics Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Table 6. Characteristics d VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified.

0.5 V and VCCO

and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified.

ADC1006S055_070_3 © IDT 2012. All rights reserved. [1] D = guaranteed by design; C = guaranteed by c haracterization; I = 100 % industrially tested. a) PECL mode 1: (DC level vary 1 : 1 with VCCD) CLK and CLKN inputs are at differential PECL levels. signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. to be connected to the ground. [4] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input be ing a full-scale sine wave. where 1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. [6] Signal-to-noise ratio (S/N) takes into account all harmo n ics above five and noise up to Nyquist frequency; see Figure 8. SINAD = ENOB  6.02 + 1.76 dB; see Figure 5. IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. [9] Output data acquisition: the output data is available af ter the maximum delay of td(o); see Figure 3. and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified.

Additional information relating to Table 6

Table 7. Output coding with differential inputs (typical values to AGND); [1] Two’s complement reference is inverted MSB. Table 8. Mode selection Table 9. Sample-and-hold selection

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 13 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz sample N + 1sample N CLK 014aaa465 sample N + 2 sample N + 1sample N sample N + 2 tw(clk)L tw(clk)H DATA D0 TO D9 HIGH 50 % LO W HIGH 50 % LOW IN td(s) th(o) td(o) DATA N − 2 DATA N − 1 DATA N DATA N + 1 Fig 3. Timing diagram 014aaa443 50 % 50 % HIGH LOW tdZHtdHZ 50 % HIGH LOW tdZLtdLZ 10 % 90 % output data VCCD output data 3.3 kΩ 15 pF VCCO ADC1006S 070 CE TEST tdLZ tdZL tdHZ VCCO VCCO OGND OGNDtdZH 0 V CE (1) frequency on pin CE = 100 kHz. Fig 4. Timing diagram and test condit ions of 3-state output delay time

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 14 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz fi (MHz) 02 5 2010 155 014aaa444 9.50 9.40 9.60 9.70 ENOB (bit) 9.30 (1) (2) fi (MHz) 02 5 2010 155 014aaa445 −67 −69 −65 −63 THD (dB) −71 (1) (2) (1) 55 MHz. (2) 70 MHz. (1) 55 MHz. (2) 70 MHz. Fig 5. Effective Number Of Bits (ENOB) as a function of input frequency (sample device) Fig 6. Total Harmonic Distortion (THD) as a function of in put frequency (sample device) fi (MHz) 02 5 2010 155 014aaa446 SFDR (dB) (1) (2) fi (MHz) 02 5 2010 155 014aaa447 59.4 59.6 59.2 59.8 60.0 S/N (dB) 59.0 (1) (2) (1) 55 MHz. (2) 70 MHz. (1) 55 MHz. (2) 70 MHz. Fig 7. Spurious Free Dynamic Range (SFDR) as a function of input frequency (sample device) Fig 8. Signal-to-Noise Ratio (S/N) as a funct ion of input frequency (sample device)

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 15 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa448 −80 −120 −40 power spectrum (dB) −160 fi (MHz) 0 3020105 2515 Fig 9. Single-tone; f i = 20 MHz; fclk = 55 MHz 014aaa449 −80 −120 −40 power spectrum (dB) −160 fi (MHz) 0 3020105 2515 Fig 10. Two-tone; f i 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 16 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz output code 0 1024768512256 014aaa450 −0.60 0.60 0.20 −0.20 1.00 output range (INL) Fig 11. Integral Non-Linearity (INL) output code 0 1024768512256 014aaa451 0.10 −0.10 0.20 0.30 DNL (LSB) −0.20 Fig 12. Differential Non-Linearity (DNL)

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 17 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Input amplitude (dBFS) 014aaa452 SFDR (dBFS) (1) (2) (3) (1) f i = 4.43 MHz. (2) f i = 20 MHz. (3) SFDR = 80 dB. Fig 13. SFDR as a function of input amplitude; V i(IN)(p-p)  Vi(INN)(p-p) = 1.9 V; fclk = 40 MHz Input amplitude (dBFS) 014aaa453 SFDR (dBFS) (1) (2) (3) (1) f i = 4.43 MHz. (2) f i = 20 MHz. (3) SFDR = 80 dB. Fig 14. SFDR as a function of input amplitude; V i(IN)(p-p)  Vi(INN)(p-p) = 1.9 V; fclk = 55 MHz

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 18 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz VCCA − VVREF (V) 014aaa455 (dB) 8.0 7.0 9.0 10.0 7.5 6.5 8.5 9.5 (bit) 6.0 (1) (2) (3) 014aaa456VCCA − VVREF (V) 1.8 1.4 2.2 2.6 1.0 VI(IN)(p-p) VI(INN)(p-p) (V) (1) SFDR. (2) ENOB. (3) S/N. Fig 15. SFDR, ENOB and S/N as a function of VCCA  VVREF; fclk = 55 MHz; fi = 20 MHz Fig 16. ADC full-scale; V I(IN)(p-p)  VI(INN)(p-p) as a function of VCCA  VVREF

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 19 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 12. Application information

12.1 Application diagrams

100 Ω100 Ω 100 nF100 nF 5 V 100 nF 100 nF 100 nF 220 nF 10 nF 5 V IN1 : 1 INN 5 V 100 nF 5 V 5 V SH mode CLK n.c. n.c. D0 (LSB) ADC1006S055/070 n.c. n.c. n.c. n.c. n.c. chip select input output format select (MSB) VREF 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram 014aaa458 270 Ω270 Ω ADC1006S CLKN CLK TTL input MC100 ELT20 PECLD Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 20 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa459 ADC1006S CLKN CLKTTL input Fig 19. Application diagram for TTL single-ended clock

12.2 Demonstration board

V CCD1 DGND1 SH AGND4 VCCA4 IN INN AGND1 VCCA VCCD VCCA VCC VCCO VCC CMADC VCCA1 VCC VCCA VCC VCCA VCC VCCO VCCO VCCA3 AGDN3 DEC n.c. n.c. n.c. n.c. n.c. VREF 33 32 31 30 29 28 27 26 25 24 23 123456789 1 0 1 1 VCCO n.c n.c IR CE OTC DGND2 n.c. V CCD2 n.c. n.c. FSREF MC78MO5CDT IN OUT ICI GND 24 B8 B11 50 Ω 100 Ω FL3 FL1 FL2 C13 100 nF 330 nF C15 10 nF 100 Ω 5 kΩ FL4 10 nF C17 10 nF C19 22 μF (20 V) 4.7 μF (16 V) 1 μF TP2 TM3 4.7 kΩ 1 μF 62 Ω 2.4 KΩ 1 kΩ 1.2 kΩ C11 100 nF C18 10 nF 330 nF C12 100 nF C16 10 nF C10 100 nF PMBT 2222A BZV55C3V6 C14 100 nF 330 nF 100 Ω BYD17G CLK2 CLK1 CLK1 IN 220 nF MCLT1_6T_KK81 TR1 CMADC

12 V 1 3

750 Ω LGT679 330 nF P2 R7 C8 is close to TR1 pin. Fig 20. Demonstration board schematic

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 22 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa466 C4 C5 TP2 R2 R5 R7 R4 C11 C10 C14 112 23 C12 S3 S4 B5 B8 B11 FL4 FL2 TM3 TM2 TM1 IC1 IC2 TR1 Fig 21. Component placement (top side) 014aaa467 FL1 FL3 C8C13 C17 C15 C19 C16 C18 Fig 22. Component placement (underside)

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 23 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa461 Fig 23. Printed-circuit board layout (top layer) 014aaa462 Fig 24. Printed-circuit board layout (ground layer)

12.3 Alternative parts

Table 10. Alternative parts

12.4 Recommended companion chip

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 25 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 13. Support information

13.1 Definitions

13.1.1 Non-linearities

13.1.1.1 Integral Non-Linearity (INL)

It is defined as the deviation of the transfer fu nction from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: INL i where i0 2 n 1–= and S = slope of the ideal straight line = code width; i = code value.

13.1.1.2 Differential Non-Linearity (DNL)

It is the deviation in code width from the value of 1 LSB. DNL i where i0 2 n 2–=

13.1.2 Dynamic parameters (single tone)

Figure 26 shows the spectrum of a full-scale in put sine wave with frequency ft, conforming to coherent sampling (ft / fs = M / N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. a3 ak SFDR 014aaa440 fs/2measured output range (MHz) magnitude Fig 26. Spectrum of full-scale input sine wave with frequency f t

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 26 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and ‘quantization noise’.

13.1.2.1 Signal-to-Noise And Dis tortion (SINAD)

The ratio of the output signal power to the noise a nd distortion power for a given sample rate and input frequency, excluding the DC component: SINAD dB 10 Psignal Pnoise distortion+

13.1.2.2 Effective Number Of Bits (ENOB)

It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to ob tain the same SINAD measured on the real ADC. A good approximation gives:

13.1.2.3 Total Harmonic Distortion (THD)

The ratio of the power of the harmonics to the power of the fundamental. For k-1 h armonics the THD is: THD dB 10 = Pharmonics Psignal where Pharmonics  2 2  3  k ++= and Psignal  1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).

13.1.2.4 Signal-to-Noise ratio (S/N)

The ratio of the output signal power to the noise power, excluding the harmonics and the DC com ponent. S/N dB 10 Psignal Pnoise

13.1.2.5 Spurious Free Dynamic Range (SFDR)

The number SFDR specifies available signal range as the spectral distance between the a mplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic), excluding DC component. SFDR dB 20 1

13.1.3 Intermodulation distortion

13.1.3.1 Spectral analysis (dual-tone)

fs/2measured output range (MHz) magnitude Fig 27. Spectral analysis (dual-tone) From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd-order components) are defined, as follows.

13.1.3.2 IMD2 (IMD3)

The ratio of the RMS value of either tone to the RMS value of the worst second (third) o rder intermodulation product. The total IMD is given by: IMD dB 10 Pintermod Psignal where, Pintermod a im 2 ft1 ft2– a im ft1 ft2+ a im ft1 2ft2– a im ft1 2ft2+ a im 2 2ft1 ft2– a im 2ft1 ft2+++ ++–= Psignal a2 ft1 a2 ft2+ = and a im 2 ft is the power in the intermodulation component at frequency ft.

13.1.4 Noise Power Ratio (NPR)

When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the NPR is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set.

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 28 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 14. Package outline UNIT A 1 A2 A3 bp cE (1) eH E LL p Zy w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 o o0.15 0.10.15 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 SOT307-2 97-08-01 03-02-25 D(1) (1) (1) 10.1 9.9 HD 12.9 12.3 EZ 1.2 0.8 D e E B c EH D ZD A ZE e v M A X 33 23 y θ A Lp detail X L (A )3 pin 1 index DH v M B bp bp w M w M 0 2.5 5 mm scale QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 A max. 2.1 Fig 28. Package outline SOT307-2 (QFP44)

Corrections made to note in Figure 4. ADC1006S055_070_1 20080611 Product data sheet - - 16. Contact information For more information or sales office addresses, please visit: http://www.idt.com

ADC1006S055_070_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 30 of 30 Integrated Device Technology ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 17. Contents 11 Additional inform ation relating to Table 6 . . . 12

Product Information

ADC1006S070 specifications and overview.

Summary

Single 10 bits ADC, up to 55 MHz or 70 MHz

Description

Single 10 bits ADC, up to 55 MHz or 70 MHz

Source title ADC1006S070 Datasheet(PDF) - Integrated Device Technology

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