ADC10064CIWM

ADC10061 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

n Built-in sample-and-hold n Single +5V supply n 1, 2, or 4-input multiplexer options n No external clock required n Speed adjust pin for faster conversions (ADC10062 and ADC10064). See ADC10662/4 for high speed guaranteed performance. Key Specifications n Conversion time to 10 bits 600 ns typical, n 900 ns max over temperature n Sampling Rate 800 kHz n Low power dissipation 235 mW (max) n Total unadjusted error ±1.0 LSB (max) n No missing codes over temperature

Applications

n Digital signal processor front ends n Instrumentation n Disk drives n Mobile telecommunications Simplified Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS011020-1 *ADC10061 Only ADC10062 and ADC10064 Only *ADC10064 Only June 1999 ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold © 1999 National Semiconductor Corporation DS011020 www.national.com

Ordering Information

Industrial (−40˚C≤ TA ≤ +85˚C) Package ADC10061CIWM M20B Small Outline ADC10062CIWM M24B Small Outline ADC10064CIWM M28B Small Outline Connection Diagrams DS011020-11 Top View DS011020-12 Top View DS011020-13 Top View www.national.com 2

DV CC ,A VCC These are the digital and analog positive sup- ply voltage inputs. They should always be con- nected to the same voltage source, but are brought out separately to allow for separate bypass capacitors. Each supply pin should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to ground. INT This is the active low interrupt output. INT goes low at the end of each conversion, and returns to a high state following the rising edge of RD. S/H This is the Sample/Hold control input. When this pin is forced low (and CS is low), it causes the analog input signal to be sampled and ini- tiates a new conversion. RD This is the active low Read control input. When this RD and CS are low, any data present in the output registers will be placed on the data bus. CS This is the active low Chip Select control input. When low, this pin enables the RD and S/H pins. S0, S1 On the multiple-input devices (ADC10062 and ADC10064), these pins select the analog input that will be connected to the A/D during the conversion. The input is selected based on the state of S0 and S1 when S/H makes its High-to-Low transition (See the Timing Dia- grams). The ADC10064 includes both S0 and S1. The ADC10062 includes just S0, and the ADC10061 includes neither. V REF− , VREF+ These are the reference voltage inputs. They may be placed at any voltage between GND and V CC , but VREF+ must be greater than VREF− . An input voltage equal to VREF− pro- duces an output code of 0, and an input volt- age equal to (V REF+ − 1 LSB) produces an out- put code of 1023. VIN,V IN0, VIN1,V IN2, VIN3 These are the analog input pins. The ADC10061 has one input (V IN), the ADC10062 has two inputs (VIN0 and V IN1), and the ADC10064 has four inputs (VIN0,V IN1,V IN2 and V IN3). The impedance of the source should be less than 500Ω for best accuracy and conversion speed. For accurate conver- sions, no input pin (even one that is not se- lected) should be driven more than 50 mV above V CC or 50 mV below ground. GND, AGND, DGND These are the power supply ground pins. The ADC10061 has a single ground pin (GND), and the ADC10062 and ADC10064 have separate analog and digital ground pins (AGND and DGND) for separate bypassing of the analog and digital supplies. The ground pins should be connected to a stable, noise-free system ground. For the devices with two ground pins, both pins should be re- turned to the same potential. DB0–DB9 These are the TRI-STATE ® output pins. SPEED ADJ (ADC10062 and ADC10064 only). This pin is normally left unconnected, but by connecting a resistor between this pin and ground, the con- version time can be reduced. See the Typical Performance Curves and the table of Electri- cal Characteristics. www.national.com3

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V + = AV CC = DV CC ) −0.3V to +6V Voltage at Any Input or Output −0.3V to V + + 0.3V Input Current at Any Pin (Note 3) 5 mA Package Input Current (Note 3) 20 mA Power Dissipation (Note 4) 875 mW ESD Susceptability (Note 5) 2000V Soldering Information (Note 6) Vapor Phase (60 Sec) Infrared (15 Sec) 215˚C 220˚C Storage Temperature Range −65˚C to +150˚C Junction Temperature 150˚C Operating Ratings(Notes 1, 2) Temperature Range T MIN ≤ TA ≤ TMAX ADC10061CIWM, ADC10062CIWM, ADC10064CIWM −40˚C ≤ T A ≤ +85˚C Supply Voltage Range 4.5V to 5.5V Converter Characteristics The following specifications apply for V+ = +5V, VREF(+) = +5V, VREF(−) = GND, and Speed Adjust pin unconnected unless otherwise specified.Boldface limits apply for TA = TJ = TMin to TMax ;all other limits TA = TJ = +25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limit) Resolution 10 Bits Integral Linearity Error R SA = 18 kΩ ±0.5 ±1.0/±1.5 LSB (max) Offset Error ±1 LSB (max) Full-Scale Error ±1 LSB (max) Total Unadjusted Error All Suffixes, R SA = 18 kΩ ±0.5 ±1.5/±2.0 LSB (max) Missing Codes 0 (max) Power Supply Sensitivity V + = 5V ±5% ,V REF = 4.5V V+ = 5V ±10% ,V REF = 4.5V ±1/16 ±3⁄8 LSB LSB (max) THD Total Harmonic Distortion f IN = 10 kHz, 4.85 VP-P fIN = 160 kHz, 4.85 VP-P 0.06 0.08 SNR Signal-to-Noise Ratio f IN = 10 kHz, 4.85 VP-P fIN = 160 kHz, 4.85 VP-P dB dB Effective Number of Bits f IN = 10 kHz, 4.85 VP-P fIN = 160 kHz, 4.85 VP-P 9.6 9.4 Bits Bits R REF Reference Resistance 650 400 Ω (min) R REF Reference Resistance 650 900 Ω (max) VREF(+) VREF(+) Input Voltage V+ + 0.05 V (max) VREF(−) VREF(−) Input Voltage GND − 0.05 V (min) VREF(+) VREF(+) Input Voltage VREF(−) V (min) VREF(−) VREF(−) Input Voltage VREF(+) V (max) VIN Input Voltage V+ + 0.05 V (max) VIN Input Voltage GND − 0.05 V (min) OFF Channel Input Leakage Current ON Channel Input Leakage Current CS = V+,V IN = V+ CS = V+,V IN = V+ 0.01 µA (max) µA (max) The following specifications apply for V+ = +5V, VREF(+) = 5V VREF(−) = GND, and Speed Adjust pin unconnected unless other- wise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = +25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limit) VIN(1) Logical “1” Input Voltage V + = 5.5V 2.0 V (min) VIN(0) Logical “0” Input Voltage V + = 4.5V 0.8 V (max) IIN(1) Logical “1” Input Current V IN(1)= 5V 0.005 3.0 µA (max) IIN(0) Logical “0” Input Current V IN(0)0V −0.005 −3.0 µA (max) VOUT(1) Logical “1” Output Voltage V + = 4.5V, IOUT = −360 µA V+ = 4.5V, IOUT = −10 µA 2.4 4.25 V (min) V (min) www.national.com 4

The following specifications apply for V+ = +5V, VREF(+) = 5V VREF(−) = GND, and Speed Adjust pin unconnected unless other- wise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = +25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limit) VOUT(0) Logical “0” Output Voltage V + = 4.5V, IOUT = 1.6 mA 0.4 V (max) IOUT TRI-STATE ® Output Current V OUT = 5V VOUT = 0V 0.1 −0.1 −50 µA (max) µA (max) DICC DV CC Supply Current CS = S/H = RD = 0, RSA = ∞ CS = S/H = RD = 0, RSA = 18 kΩ 1.0 1.0 2 mA (max) mA (max) AICC AV CC Supply Current CS = S/H = RD = 0, RSA = ∞ CS = S/H = RD = 0, RSA = 18 kΩ 30 45 mA (max) mA (max) The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(−) = GND, and Speed Adjust pin uncon- nected unless otherwise specified.Boldface limits apply for TA = TJ = TMIN to TMAX ;all other limits TA = TJ = +25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limit) tCONV Mode 1 Conversion Time from Rising Edge of S/H to Falling Edge of INT R SA = ∞ R SA = 18k 600 375 750/900 ns(max) ns tCRD Mode 2 Conversion Time R SA = ∞ Mode 2, RSA = 18k 850 530 1400 ns(max) ns tACC1 Access Time (Delay from Falling Edge of RD to Output Valid) Mode 1; CL = 100 pF 30 60 ns (max) tACC2 Access Time (Delay from Falling Edge of RD to Output Valid) Mode 2; CL = 100 pF 900 tCRD +5 0 ns (max) tSH Minimum Sample Time ( Figure 1); (Note 8) 250 ns (max) t1H ,t0H TRI-STATE Control (Delay from Rising Edge of RD to High-Z State) R L = 1k, CL = 10 pF 30 60 ns (max) tINTH Delay from Rising Edge of RD to Rising Edge of INT C L = 100 pF 25 50 ns (max) tP Delay from End of Conversion to Next Conversion 50 ns (max) tMS Multiplexer Control Setup Time 10 75 ns (max) tMH Multiplexer Hold Time 10 40 ns (max) C VIN Analog Input Capacitance 35 pF (max) C OUT Logic Output Capacitance 5 pF (max) C IN Logic Input Capacitance 5 pF (max) Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func- tional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditons. Note 2:All voltages are measured with respect to GND, unless otherwise specified. Note 3:When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. Note 4:The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX −T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases, the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found from the tables below: Device θJA (˚C/W) ADC10061CIWM 54 ADC10062CIWM 48 ADC10064CIWM 44 Note 5:Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 6:See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon- ductor Linear Data Book for other methods of soldering surface mount devices. Note 7:Typicals are at +25˚C and represent must likely parametric norm. www.national.com5

Note 8:Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 9:Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs tSH . Typical Performance Characteristics Zero (Offset) Error vs Reference Voltage DS011020-16 Linearity Error vs Reference Voltage DS011020-17 Analog Supply Current vs Temperature DS011020-18 Digital Supply Current vs Temperature DS011020-19 Conversion Time vs Temperature DS011020-20 Conversion Time vs Temperature DS011020-21 Conversion Time vs Speed-Up Resistor (ADC10062 and ADC10064 Only) DS011020-22 Conversion Time vs Speed-Up Resistor (ADC10062 and ADC10064 Only) DS011020-23 Spectral Response with100 kHz Sine Wave Input DS011020-24 www.national.com 6

Typical Performance Characteristics(Continued) TRI-STATE Test Circuits and Waveforms Spectral Response with 100 kHz Sine Wave Input DS011020-25 Signal-to-Noise + THD Ratio vs Signal Frequency DS011020-26 Linearity Change vs Speed-Up Resistor (ADC10062 and ADC10064 Only) DS011020-27 Linearity Change vs Speed-Up Resistor (ADC10062 and ADC10064 Only) DS011020-28 Linearity Error Change vs Sample Time DS011020-29 DS011020-5 DS011020-6 DS011020-7 DS011020-8 www.national.com7

comparators at the right of the diagram. quired using conventional half-flash methods. sions without excessive power drain.

1.0 MODES OF OPERATION

showing how the input channnels are assigned. FIGURE 3. Block Diagram of the Multistep Converter Architecture

parators in the “coarse” flash converter to become active. is reset high on the rising edge of RD. TABLE 1. Input Multiplexer Programming

00 V IN0

01 V IN1

10 V IN2

11 V IN3

2.0 REFERENCE CONSIDERATIONS

ence voltages less than 2V are not recommended. passed with a 10 µF tantalum and a 0.1 µF ceramic.

3.0 THE ANALOG INPUT

proximately equal to 600Ω in series with 35 pF. normal and do not degrade the converter’s performance. pling time is increased, the source impedance can be larger.

4.0 INHERENT SAMPLE-AND-HOLD

nents from DC to over 160 kHz.

5.0 POWER SUPPLY CONSIDERATIONS

more bypassing may be necessary. applied to any of the other pins.

6.0 LAYOUT AND GROUNDING

the digital and analog parts of the system.

7.0 DYNAMIC PERFORMANCE

FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREF− Considerations”). AGND and DGND should be at the same potential. VIN0 is shown with an input protection network. Pin 17 is normally left open, but optional “speedup” resistor RSA can be used to reduce the conversion time.

Applications Information(Continued) digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic charac- teristics such as signal-to-noise ratio (SNR) and total har- monic distortion (THD), are quantitative measures of this ca- pability. An A/D converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal wave- form is applied to the A/D converter’s input, and the trans- form is then performed on the digitized waveform. The re- sulting spectral plot might look like the ones shown in the typical performance curves. The large peak is the fundamen- tal frequency, and the noise and distortion components (if any are present) are visible above and below the fundamen- tal frequency. Harmonic distortion components appear at whole multiples of the input frequency. Their amplitudes are combined as the square root of the sum of the squares and compared to the fundamental amplitude to yield the THD specification. Typical values for THD are given in the table of Electrical Characteristics. Signal-to-noise ratio is the ratio of the amplitude at the fun- damental frequency to the rms value at all other frequencies, excluding any harmonic distortion components. Typical val- ues are given in the Electrical Characteristics table. An alter- native definition of signal-to-noise ratio includes the distor- tion components along with the random noise to yield a signal-to-noise-plus-distortion ratio, or S/(N + D). The THD and noise performance of the A/D converter will change with the frequency of the input signal, with more dis- tortion and noise occurring at higher signal frequencies. One way of describing the A/D’s performance as a function of sig- nal frequency is to make a plot of “effective bits” versus fre- quency. An ideal A/D converter with no linearity errors or self-generated noise will have a signal-to-noise ratio equal to (6.02n + 1.76) dB, where n is the resolution in bits of the A/D converter. A real A/D converter will have some amount of noise and distortion, and the effective bits can be found by: where S/(N + D) is the ratio of signal to noise and distortion, which can vary with frequency. As an example, an ADC10061 witha5V P-P, 100 kHz sine wave input signal will typically have a signal-to-noise-plus-distortion ratio of 59.2 dB, which is equivalent to 9.54 effective bits. As the input frequency in- creases, noise and distortion gradually increase, yielding a plot of effective bits or S/(N + D) as shown in the typical per- formance curves.

8.0 SPEED ADJUST

In applications that require faster conversion times, the Speed Adjust pin (pin 14 on the ADC10062, pin 17 on the ADC10064) can significantly reduce the conversion time. The speed adjust pin is connected to an on-chip current source that determines the converter’s internal timing. By connecting a resistor between the speed adjust pin and ground as shown in Figure 4, the internal programming cur- rent is increased, which reduces the conversion time. As an example, an 18k resistor reduces the conversion time of a typical part from 600 ns to 350 ns with no significant effect on linearity. Using smaller resistors to further decrease the con- version time is possible as well, although the linearity will be- gin to degrade somewhat (see curves). Note that the resistor value needed to obtain a given conversion time will vary from part to part, so this technique will generally require some “tweaking” to obtain satisfactory results. www.national.com 12

Physical Dimensionsinches (millimeters) unless otherwise noted Order Number ADC10061CIWM Order Number ADC10062CIWM www.national.com13

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Order Number ADC10064CIWM ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.