ADC10061_14 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 23
Technical content
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 ADC10061/ADC10062/ADC1006410-Bit600nsA/DConverterwithInputMultiplexerand Sample/Hold Check forSamples: ADC10061 ,ADC10062 ,ADC10064 1FEATURES DESCRIPTION NOTE: The ADC10061 and ADC10062 areobsolete. 2• Built-inSample-and-Hold They aredescribedhereforreferenceonly.• Single+5V Supply Using an innovative,patentedmultistep*conversion• No ExternalClock Required technique,these CMOS analog-to-digitalconverters• Speed AdjustPin forFasterConversions offersub-microsecondconversiontimesyetdissipate(ADC10062 and ADC10064). See ADC10662/4 a maximum of only 235 mW. These converters forHigh Speed Ensured Performance. perform 10-bitconversionsin two lower-resolution “flashes”,yieldinga fastA/D withoutthecost,power APPLICATIONS consumption,and other problems associatedwith trueflashapproaches.• DigitalSignalProcessor FrontEnds The analoginputvoltageissampled and heldby an• Instrumentation internalsamplingcircuit.Inputsignalsatfrequencies• Disk Drives from DC toover200 kHz can,therefore,be digitized
- MobileTelecommunications accuratelywithoutthe need foran externalsample- and-holdcircuit. KEY SPECIFICATIONS The ADC10062 and ADC10064 includea “speed-up”
- Conversion Time 600 ns Typical,900 ns Max pin.Connectingan externalresistorbetween thispin and groundreducesthetypicalconversiontimetoas• Sampling Rate 800 kHz littleas 350 ns withonlya smallincreaseinlinearity• Low Power Dissipation235 mW (Max) error.
- TotalUnadjusted Error±1.0LSB (Max) For ease of interfaceto microprocessors,the• No MissingCodes Over Temperature ADC10061, ADC10062, and ADC10064 have been designedtoappear as a memory locationor I/Oport withouttheneed forexternalinterfacelogic. *U.S.PatentNumber 4918449 SimplifiedBlock Diagram *ADC10061 Only,ADC10062 and ADC10064 Only,*ADC10064 Only Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com Connection Diagram Thisdeviceisobsolete;shown forreferenceonly. Figure1. Top View Thisdeviceisobsolete;shown forreferenceonly. Figure2. Top View Figure3. Top View
2 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 NOTE: The ADC10061 and ADC10062 areobsolete;shown forreferenceonly. PIN DESCRIPTIONS Pin Function Description DV CC ,AV CC Digitaland analogpositivesupplyvoltageinputs.Connectbothtothesame voltagesource,butbypassseparatelywith a 0.1µF ceramiccapacitorinparallelwitha 10 µF tantalumcapacitortogroundateach pin. INT Activelowinterruptoutput.INT goes lowattheend ofeach conversion,and returnshighfollowingtherisingedge of RD. S/H Sample/Holdcontrolinput.When thispinisforcedlow(andCS islow),theanaloginputsignalissampled and a new conversionisinitiated. RD Activelowreadcontrolinput.When thisRD and CS arelow,any datapresentintheoutputregisterswillbe placed ontothedatabus. CS ActivelowChipSelectcontrolinput.When low,thispinenablestheRD and S/H pins. S0,S1 On themultiple-inputdevices(ADC10062 and ADC10064), thesepinsselecttheanaloginputthatwillbe connectedto theA/D duringtheconversion.The inputisselectedbased on thestateofS0 and S1 when S/H makes itsHigh-to-Low transition(See TimingDiagrams).The ADC10064 includesbothS0 and S1.The ADC10062 includesjustS0,and the ADC10061 has neither. VREF −,VREF+ Referencevoltageinputs.They may be placedatany voltagebetween GND and VCC ,butVREF+ must be greaterthan VREF −.An inputvoltageequaltoVREF − producesan outputcode of0,and an inputvoltageequalto(VREF+ − 1 LSB) producesan outputcode of1023. VIN,VIN0,VIN1, Analoginputpins.The ADC10061 has one input(VIN),theADC10062 has two inputs(VIN0 and VIN1),and the VIN2,VIN3 ADC10064 has fourinputs(VIN0,VIN1,VIN2 and VIN3).The impedance oftheinputsourceshouldbe lessthan500Ω for bestaccuracyand conversionspeed.Foraccurateconversions,no inputpin(evenone thatisnotselected)shouldbe drivenmore than50 mV above VCC or50 mV belowground. GND, AGND, Power supplygroundpins.The ADC10061 has a singlegroundpin(GND),and theADC10062 and ADC10064 have DGND separateanalogand digitalgroundpins(AGND and DGND) forseparatebypassingoftheanalogand digitalsupplies. The groundpinsshouldbe connectedtoa stable,noise-freesystemground.Forthedeviceswithtwo groundpins, bothpinsshouldbe returnedtothesame potential. DB0 –DB9 TRI-STATE dataoutputpins. SPEED ADJ (ADC10062 and ADC10064 only).Thispinisnormallyleftunconnected,butby connectinga resistorbetween thispin and ground,theconversiontimecan be reduced.See TypicalPerformanceCharacteristicsand thetableofElectrical Characteristics. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com AbsoluteMaximum Ratings(1)(2)(3) SupplyVoltage(V+ = AV CC = DV CC ) −0.3Vto+6V VoltageatAny InputorOutput −0.3VtoV+ + 0.3V InputCurrentatAny Pin(4) 5 mA Package InputCurrent(4) 20 mA Power Consumption(5) 875 mW ESD Susceptibility(6) 2000V Vapor Phase (60Sec) 215°C SolderingInformation Infrared(15Sec) 220°C StorageTemperatureRange −65°C to+150°C JunctionTemperature 150°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional.These ratingsdo notensurespecificperformancelimits,however.Forensuredspecificationsand test conditions,see theElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performance characteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) When theinputvoltage(VIN)atany pinexceedsthepower supplyrails(VIN < GND orVIN > V+)theabsolutevalueofcurrentatthatpin shouldbe limitedto5 mA orless.The 20 mA package inputcurrentlimitsthenumber ofpinsthatcan safelyexceed thepower supplies withan inputcurrentof5 mA tofour. (5) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJMAX ,θJA and theambienttemperature, TA.The maximum allowablepower dissipationatany temperatureisPD = (TJMAX − TA)/θJA orthenumber givenintheAbsolute Maximum Ratings,whicheverislower.Inmost cases,themaximum deratedpower dissipationwillbe reachedonlyduringfault conditions.Forthesedevices,TJMAX fora board-mounteddeviceareas indicatedinPackage ThermalResistance. (6) Human body model,100 pF dischargedthrougha 1.5kΩ resistor. OperatingRatings(1)(2) TMIN ≤ TA ≤ TMAX =TemperatureRange −40°C ≤ TA ≤ +85°C SupplyVoltageRange +4.5V to+5.5V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional.These ratingsdo notensurespecificperformancelimits,however.Forensuredspecificationsand test conditions,see theElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performance characteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified. Package Thermal Resistance Device θJA (°C/W) ADC10061CIWM 85 ADC10062CIWM 82 ADC10064CIWM 78 ConverterCharacteristics The followingspecificationsapplyforV+ = +5V, VREF(+) = +5V, VREF(−) = GND, and Speed Adjustpinunconnectedunless otherwisespecified.BoldfacelimitsapplyforTA = TJ = TMin toTMax ;allotherlimitsTA = TJ = +25°C. UnitsSymbol Parameter Conditions Typical(1) Limit(2) (Limit) Resolution 10 Bits IntegralLinearityError R SA = 18 kΩ ±0.5 ±1.0/±1.5 LSB (max) OffsetError ±1.5 LSB (max) Full-ScaleError ±1 LSB (max) TotalUnadjustedError AllSuffixes,R SA = 18 kΩ ±0.5 ±1.5/±2.2 LSB (max) MissingCodes] 0 (max) (1) Typicalnumbers areat+25°C and representmust likelyparametricnorm. (2) LimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel).
4 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 ConverterCharacteristics(continued) The followingspecificationsapplyforV+ = +5V, VREF(+) = +5V, VREF(−) = GND, and Speed Adjustpinunconnectedunless otherwisespecified.BoldfacelimitsapplyforTA = TJ = TMin toTMax ;allotherlimitsTA = TJ = +25°C. UnitsSymbol Parameter Conditions Typical(1) Limit(2) (Limit) V+ = 5V ±5%, VREF = 4.5V ±1/16 LSBPower SupplySensitivity V+ = 5V ±10%, VREF = 4.5V ±⅜ LSB (max) fIN = 10 kHz,4.85VP-P 0.06 %THD TotalHarmonicDistortion fIN = 160 kHz,4.85VP-P 0.08 % fIN = 10 kHz,4.85VP-P 61 dBSNR Signal-to-NoiseRatio fIN = 160 kHz,4.85VP-P 60 dB fIN = 10 kHz,4.85VP-P 9.6 BitsEffectiveNumber ofBits fIN = 160 kHz,4.85VP-P 9.4 Bits R REF ReferenceResistance 650 400 Ω (min) R REF ReferenceResistance 650 900 Ω (max) VREF(+) VREF(+) InputVoltage V+ + 0.05 V (max) VREF(−) VREF(−) InputVoltage GND − 0.05 V (min) VREF(+) VREF(+) InputVoltage VREF(−) V (min) VREF(−) VREF(−) InputVoltage VREF(+) V (max) VIN InputVoltage V+ + 0.05 V (max) VIN InputVoltage GND − 0.05 V (min) OFF ChannelInputLeakage Current CS = V+,VIN = V+ 0.01 3 µA (max) ON ChannelInputLeakage Current CS = V+,VIN = V+ ±1 −3 µA (max) DC ElectricalCharacteristics The followingspecificationsapplyforV+ = +5V, VREF(+) = 5V VREF(−) = GND, and Speed Adjustpinunconnectedunless otherwisespecified.BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsTA = TJ = +25°C. UnitsSymbol Parameter Conditions Typical(1) Limit(2) (Limit) VIN(1) Logical“1”InputVoltage V+ = 5.5V 2.0 V (min) VIN(0) Logical“0”InputVoltage V+ = 4.5V 0.8 V (max) IIN(1) Logical“1”InputCurrent VIN(1)= 5V 0.005 3.0 µA (max) IIN(0) Logical“0”InputCurrent VIN(0)0V −0.005 −3.0 µA (max) V+ = 4.5V,IOUT = −360 µA 2.4 V (min)VOUT(1) Logical“1”OutputVoltage V+ = 4.5V,IOUT = −10 µA 4.25 V (min) VOUT(0) Logical“0”OutputVoltage V+ = 4.5V,IOUT = 1.6mA 0.4 V (max) VOUT = 5V 0.1 50 µA (max)IOUT TRI-STATE OutputCurrent VOUT = 0V −0.1 −50 µA (max) CS = S/H = RD = 0,R SA = ∞ 1.0 2 mA (max)DICC DV CC SupplyCurrent CS = S/H = RD = 0,R SA = 18 kΩ 1.0 2 mA (max) CS = S/H = RD = 0,R SA = ∞ 30 45 mA (max)AICC AV CC SupplyCurrent CS = S/H = RD = 0,R SA = 18 kΩ 30 45 mA (max) (1) Typicalnumbers areat+25°C and representmust likelyparametricnorm. (2) LimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel). AC ElectricalCharacteristics The followingspecificationsapplyforV+ = +5V, tr = tf = 20 ns,VREF(+) = 5V,VREF(−) = GND, and Speed Adjustpinunconnected unlessotherwisespecified.BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsTA = TJ = +25°C. UnitsSymbol Parameter Conditions Typical(1) Limit(2) (Limit) Mode 1 ConversionTime fromRising R SA = ∞ 600 750/900 ns (max)tCONV Edge ofS/H toFallingEdge ofINT R SA = 18k 375 ns (1) Typicalnumbers areat+25°C and representmust likelyparametricnorm. (2) LimitsarespecifiedtoTI's AOQL (AverageOutgoingQualityLevel). Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com AC ElectricalCharacteristics(continued) The followingspecificationsapplyforV+ = +5V, tr = tf = 20 ns,VREF(+) = 5V,VREF(−) = GND, and Speed Adjustpinunconnected unlessotherwisespecified.BoldfacelimitsapplyforTA = TJ = TMIN toTMAX ;allotherlimitsTA = TJ = +25°C. UnitsSymbol Parameter Conditions Typical(1) Limit(2) (Limit) R SA = ∞ 850 1400 ns (max)tCRD Mode 2 ConversionTime Mode 2,R SA = 18k 530 ns Access Time (DelayfromFallingEdge oftACC1 Mode 1;C L = 100 pF 30 60 ns (max)RD toOutputValid) Access Time (DelayfromFallingEdge oftACC2 Mode 2;C L = 100 pF 900 tCRD + 50 ns (max)RD toOutputValid) tSH Minimum Sample Time(3) Figure4(2) 250 ns (max) TRI-STATE Control(DelayfromRisingt1H ,t0H R L = 1k,C L = 10 pF 30 60 ns (max)Edge ofRD toHigh-ZState) DelayfromRisingEdge ofRD toRisingtINTH C L = 100 pF 25 50 ns (max)Edge ofINT DelayfromEnd ofConversiontoNexttP 50 ns (max)Conversion tMS MultiplexerControlSetupTime 10 75 ns (max) tMH MultiplexerHoldTime 10 40 ns (max) C VIN AnalogInputCapacitance 35 pF (max) C OUT LogicOutputCapacitance 5 pF (max) C IN LogicInputCapacitance 5 pF (max) (3) Accuracymay degradeiftSH isshorterthanthevaluespecified.See curvesofAccuracyvs.tSH . TRI-STATE TestCircuitsand Waveforms
6 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 Timing Diagrams The conversiontime(tCONV )issetby theinternaltimer. Figure4. Mode 1 The conversiontime(tCRD )includesthe samplingtimeand isdeterminedby theinternaltimer. Figure5. Mode 2 (RD Mode) Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics Zero (Offset)Error LinearityError vs.ReferenceVoltage vs.ReferenceVoltage Figure6. Figure7. Analog Supply Current DigitalSupply Current vs.Temperature vs.Temperature Figure8. Figure9. Conversion Time Conversion Time vs.Temperature vs.Temperature Figure10. Figure11.
8 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) Conversion Time Conversion Time vs.Speed-Up Resistor vs.Speed-Up Resistor (ADC10062 and ADC10064 Only) (ADC10062 and ADC10064 Only) Figure12. Figure13. SpectralResponse with100kHz Sine SpectralResponse with Wave Input 100 kHz Sine Wave Input Figure14. Figure15. LinearityChange Signal-to-Noise+ THD Ratio vs.Speed-Up Resistor vs.SignalFrequency (ADC10062 and ADC10064 Only) Figure16. Figure17. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) LinearityChange vs.Speed-Up Resistor LinearityErrorChange (ADC10062 and ADC10064 Only) vs.Sample Time Figure18. Figure19. FunctionalDescription The ADC10061 and theADC10062 areobsolete.They arediscussed here forreferenceonly. The ADC10061, ADC10062 and ADC10064 digitizean analoginputsignalto10 bitsaccuracyby performingtwo lower-resolution“flash” conversions.The firstflashconversionprovidesthe sixmost significantbits(MSBs) of data,and thesecond flashconversionprovidesthefourleastsignificantbitsLSBs). Figure20 isa simplifiedblockdiagramoftheconverter.Near thecenterofthediagramisa stringofresistors.At the bottom of the stringof resistorsare 16 resistors,each of which has a value1/1024 the resistanceof the whole resistorstring.These lower16 resistors(theLSB Ladder) thereforehave a voltagedrop of16/1024,or 1/64ofthetotalreferencevoltage(VREF+ − VREF −)acrossthem.The remainderoftheresistorstringismade up of eightgroups of eightresistorsconnectedinseries.These comprisethe MSB Ladder. Each sectionof the MSB Ladder has ⅛ ofthetotalreferencevoltageacrossit,and each oftheLSB resistorshas 1/64ofthetotal referencevoltageacrossit.Tap pointsacrosstheseresistorscan be connected,ingroups of sixteen,to the sixteencomparatorsattherightofthediagram. On the leftside of the diagram is a stringof seven resistorsconnected between VREF+ and VREF −. Six comparatorscompare theinputvoltagewiththetapvoltageson thisresistorstringtoprovidea low-resolution “estimate” of the inputvoltage.This estimateisthen used to controlthe multiplexerthatconnectsthe MSB Ladder tothesixteencomparatorson theright.Note thatthecomparatorson theleftneedn'tbe veryaccurate; theysimplyprovidean estimateoftheinputvoltage.Only thesixteencomparatorson therightand thesixon the leftare necessaryto performthe initialsix-bitflashconversion,insteadof the 64 comparatorsthatwould be requiredusingconventionalhalf-flashmethods. To performa conversion,theestimatorcompares theinputvoltagewiththetapvoltageson theseven resistors on theleft.The estimatordecoderthendetermineswhichMSB Laddertappointswillbe connectedtothesixteen comparatorson the right.For example,assume thatthe estimatordeterminesthatVIN isbetween 11/16 and 13/16ofVREF .The estimatordecoderwillinstructthecomparatorMUX toconnectthe16 comparatorstothetaps on the MSB ladderbetween 10/16 and 14/16 of VREF . The 16 comparatorswillthen performthe firstflash conversion.Note thatsincethe comparatorsare connectedto laddervoltagesthatextendbeyond the range indicatedby theestimatorcircuit,errorsintheestimatoras largeas 1/16ofthereferencevoltage(64LSBs) will be corrected.Thisfirstflashconversionproducesthesixmost significantbitsofdata— fourbitsintheflashitself, and 2 bitsintheestimator. The remainingfourLSBs are now determinedusingthesame sixteencomparatorsthatwere used forthefirst flashconversion.The MSB Ladder tapvoltagejustbelow theinputvoltage(asdeterminedby thefirstflash)is subtractedfrom the inputvoltageand compared withthe tap pointson the sixteenLSB Ladder resistors.The resultofthissecond,four-bitflashconversionisthendecoded,and thefull10-bitresultislatched.
10 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 Note thatthesixteencomparatorsused inthefirstflashconversionare reusedforthesecond flash.Thus,the multistepconversiontechniqueused intheADC10061, ADC10062, and ADC10064 needs onlya smallfraction ofthenumber ofcomparatorsthatwouldbe requiredfora traditionalflashconverter,and farfewerthanwouldbe used ina conventionalhalf-flashapproach.ThisallowstheADC10061, ADC10062, and ADC10064 toperform high-speedconversionswithoutexcessivepower drain. Figure20. Block Diagram oftheMultistepConverterArchitecture SIMILAR PRODUCT DIFFERENCES The ADC1006x, ADC1046x and ADC1066x (where "x"indicatesthe number of multiplexerinputs)are similar deviceswithdifferentspecificationlimits.The differencesinthesedevicefamiliesaresummarized below. Device Family ILE,TUE, PSS THD, SNR, ENOB Max. Conversion Time ADC1006x Ensured - 900ns ADC1046x - Ensured 900ns ADC1066x - Ensured 466ns Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION MODES OF OPERATION The ADC10061, ADC10062, and ADC10064 have two basicdigitalinterfacemodes. Figure4 and Figure5 are timingdiagramsforthetwo modes. The ADC10062 and ADC10064 have inputmultiplexersthatarecontrolledby thelogiclevelson pinsS0 and S1 when S/H goes low.Table1 isa truthtableshowinghow theinputchannels areassigned. Mode 1 Inthismode, theS/H pincontrolsthestartofconversion.S/H ispulledlow fora minimum of250 ns.Thiscauses thecomparatorsinthe“coarse”flashconvertertobecome active.When S/H goes high,theresultofthecoarse conversionislatchedand the“fine” conversionbegins.After600 ns (typical),INT goes low,indicatingthatthe conversionresultsare latchedand can be read by pullingRD low.Note thatCS must be low toenableS/H or RD. CS isinternally“ANDed ”withS/H and RD; theinputvoltageissampled when CS and S/H arelow,and data isreadwhen CS and RD arelow.INT isresethighon therisingedge ofRD. Table1.InputMultiplexerProgramming ADC10064 (a) S1 S0 Channel 0 0 VIN0 0 1 VIN1 1 0 VIN2 1 1 VIN3 ADC10062 (b) S0 Channel
0 VIN0
1 VIN1
InMode 2,alsocalled“RD mode ”,theS/H and RD pinsaretiedtogether.A conversionisinitiatedby pullingboth pinslow.The A/D convertersamples theinputvoltageand causes thecoarsecomparatorstobecome active.An internaltimerthenterminatesthecoarseconversionand beginsthefineconversion.850 ns (typical)afterS/H and RD are pulllow,INT goes low,indicatingthattheconversioniscompleted.Approximately20 ns laterthe dataappearingon theTRI-STATE outputpinswillbe valid.Note thatdatawillappearon thesepinsthroughout theconversion,butuntilINT goes lowthedataattheoutputpinswillbe theresultofthepreviousconversion. REFERENCE CONSIDERATIONS The ADC10061, ADC10062, and ADC10064 each have two referenceinputs.These inputs,VREF+ and VREF −,are fullydifferentialand definethezerotofull-scalerangeoftheinputsignal.The referenceinputscan be connected tospan theentiresupplyvoltagerange (VREF − = 0V, VREF+ = VCC ) forratiometricapplications,or theycan be connectedto differentvoltages(as long as they are between ground and VCC ) when otherinputspans are required. ReducingtheoverallVREF span tolessthan5V increasesthesensitivityoftheconverter(e.g.,ifVREF = 2V, then 1 LSB = 1.953mV). Note,however,thatlinearityand offseterrorsbecome largerwhen lowerreferencevoltages areused.See TypicalPerformanceCharacteristicsformore information.For thisreason,referencevoltagesless than2V arenotrecommended. Inmost applications,VREF − willsimplybe connectedtoground,butitisoftenusefultohave an inputspan thatis offsetfromground.Thissituationiseasilyaccommodated by thereferenceconfigurationused intheADC10061, ADC10062, and ADC10064. VREF − can be connectedto a voltageotherthan ground as longas the voltage sourceconnectedtothispiniscapableofsinkingtheconverter'sreferencecurrent(12.5mA Max @ VREF = 5V). IfVREF − isconnectedtoa voltageotherthanground,bypassitwithmultiplecapacitors.
12 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 Sincetheresistancebetween thetwo referenceinputscan be as low as 400Ω,thevoltagesourcedrivingthe referenceinputsshouldhave low outputimpedance.Any noiseon eitherreferenceinputisa potentialcause of conversionerrors,so each ofthesepinsmust be suppliedwitha clean,lownoisevoltagesource.Each reference pinshouldbe bypassedwitha 10 µF tantalumand a 0.1µF ceramic. THE ANALOG INPUT The ADC10061, ADC10062, and ADC10064 sample the analog inputvoltageonce every conversioncycle. When thishappens,theinputisbrieflyconnectedtoan impedance approximatelyequalto600Ω inserieswith35 pF.Short-durationcurrentspikescan be observedattheanaloginputduringnormaloperation.These spikesare normaland do notdegradetheconverter'sperformance. Large sourceimpedances can slow thechargingofthesamplingcapacitorsand degrade conversionaccuracy. Therefore,onlysignalsourceswithoutputimpedances lessthan500Ω shouldbe used ifratedaccuracyistobe achieved at the minimum sample time (250 ns maximum). Ifthe sampling time is increased,the source impedance can be larger.Ifa signalsourcehas a highoutputimpedance,itsoutputshouldbe bufferedwithan operationalamplifier.The operationalamplifier'soutputshouldbe well-behavedwhen drivinga switched35 pF/600Ω load.Any ringingor voltageshiftsat the op-amp'soutputduringthe samplingperiodcan resultin conversionerrors. Correctconversionresultswillbe obtainedforinputvoltagesgreaterthan GND − 50 mV and lessthan V+ + 50 mV. Do notallowthesignalsourcetodrivetheanaloginputpinbeyond theAbsoluteMaximum Rating.Ifan analoginputpinisforcedbeyond thesevoltages,thecurrentflowingthroughthepinshouldbe limitedto5 mA or lesstoavoidpermanentdamage totheIC.The sum ofalltheoverdrivecurrentsintoallpinsmust be lessthan theAbsoluteMaximum RatingforPackage InputCurrent.When theinputsignalisexpectedtoextendbeyond thislimit,an inputprotectionscheme should be used. A simpleinputprotectionnetwork using diodes and resistorsisshown inFigure21.Note themultiplebypass capacitorson thereferenceand power supplypins.If VREF − isnot grounded,itshouldalsobe bypassed to analogground usingmultiplecapacitors(see POWER SUPPLY CONSIDERATIONS ).AGND and DGND shouldbe atthesame potential.VIN0 isshown withan input protectionnetwork.Pin 17 isnormallyleftopen,butoptional“speedup” resistorR SA can be used toreducethe conversiontime. Figure21. TypicalConnection INHERENT SAMPLE-AND-HOLD Because theADC10061, ADC10062, and ADC10064 sample theinputsignalonce duringeach conversion,they are capableof measuringrelativelyfastinputsignalswithoutthe helpof an externalsample-hold.In a non- samplingsuccessive-approximationA/D converter,regardlessofspeed,theinputsignalmust be stabletobetter than ±1/2 LSB duringeach conversioncycleor significanterrorswillresult.Consequently,even formany relativelyslowinputsignals,thesignalsmust be externallysampled and heldconstantduringeach conversionif a SAR withno internalsample-and-holdisused. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com Because theyincorporatea directsample/holdcontrolinput,the ADC10061, ADC10062, and ADC10064 are suitableforuse inDSP-based systems.The S/H inputallowssynchronizationoftheA/D convertertotheDSP system'ssamplingrateand tootherADC10061s, ADC10062s, and ADC10064s. POWER SUPPLY CONSIDERATIONS The ADC10061, ADC10062, and ADC10064 aredesignedtooperatefroma +5V (nominal)power supply.There are two supplypins,AV CC and DV CC .These pinsallowseparateexternalbypass capacitorsfortheanalogand digitalportionsofthecircuit.To ensureaccurateconversions,thetwo supplypinsshouldbe connectedtothe same voltagesource,and each shouldbe bypassed witha 0.1 µF ceramiccapacitorinparallelwitha 10 µF tantalumcapacitor.Depending upon thecircuitboard layoutand othersystem considerations,more bypassing may be necessary. The ADC10061 has a singleground pin,and the ADC10062 and ADC10064 each have separateanalogand digitalground pinsforseparatebypassingoftheanalogand digitalsupplies.The deviceswithseparateanalog and digitalgroundpinsshouldhave theirgroundpinsconnectedtothesame potential,and allgroundsshouldbe “clean”and freeofnoise. Insystemswithmultiplepower supplies,carefulattentiontopower supplysequencingmay be necessarytoavoid over-drivinginputs.The A/D converter'spower supplypinsshouldbe at the propervoltagebeforedigitalor analogsignalsareappliedtoany oftheotherpins. LAYOUT AND GROUNDING Inordertoensurefast,accurateconversionsfromtheADC10061, ADC10062, and ADC10064, itisnecessaryto use appropriatecircuitboard layouttechniques.The analogground returnpath shouldbe low-impedanceand freeofnoisefromotherpartsofthesystem.Noisefromdigitalcircuitrycan be especiallytroublesome. Allbypass capacitorsshould be locatedas closeto the converteras possibleand should connect to the converterand togroundwithshorttraces.The analoginputshouldbe isolatedfromnoisysignaltracestoavoid havingspurioussignalscoupletotheinput.Any externalcomponent (e.g.,a filtercapacitor)connectedacross theconverter'sinputshouldbe connectedtoa verycleangroundreturnpoint.Groundingthecomponent atthe wrong pointwillresultinreducedconversionaccuracy. DYNAMIC PERFORMANCE Many applicationsrequiretheA/D convertertodigitizeAC signals,butconventionalDC integraland differential nonlinearityspecificationsdon'taccuratelypredictthe A/D converter'sperformancewithAC inputsignals.The importantspecificationsforAC applicationsreflecttheconverter'sabilitytodigitizeAC signalswithoutsignificant spectralerrorsand withoutaddingnoisetothedigitizedsignal.Dynamic characteristicssuch as signal-to-noise ratio(SNR) and totalharmonicdistortion(THD),arequantitativemeasures ofthiscapability. An A/D converter'sAC performancecan be measured usingFastFourierTransform(FFT)methods.A sinusoidal waveform isappliedtotheA/D converter'sinput,and thetransformisthenperformedon thedigitizedwaveform. The resultingspectralplotmightlookliketheones shown inTypicalPerformanceCharacteristics.The largepeak isthefundamentalfrequency,and thenoiseand distortioncomponents (ifany arepresent)arevisibleabove and below the fundamentalfrequency.Harmonic distortioncomponents appear at whole multiplesof the input frequency.Theiramplitudesare combined as thesquarerootofthesum ofthesquaresand compared tothe fundamentalamplitudetoyieldtheTHD specification.TypicalvaluesforTHD aregiveninthetableofElectrical Characteristics. Signal-to-noiseratioisthe ratioof the amplitudeat the fundamentalfrequencyto the rms valueat allother frequencies,excludingany harmonic distortioncomponents. Typicalvalues are given in the Electrical Characteristicstable.An alternativedefinitionof signal-to-noiseratioincludesthe distortioncomponents along withtherandom noisetoyielda signal-to-noise-plus-distortionratio,orS/(N+ D). The THD and noiseperformanceof the A/D converterwillchange withthe frequencyof the inputsignal,with more distortionand noiseoccurringathighersignalfrequencies.One way ofdescribingtheA/D'sperformance as a functionofsignalfrequencyistomake a plotof“effectivebits” versusfrequency.An idealA/D converter withno linearityerrorsorself-generatednoisewillhave a signal-to-noiseratioequalto(6.02n+ 1.76)dB, where n isthe resolutionin bitsof the A/D converter.A realA/D converterwillhave some amount of noiseand distortion,and theeffectivebitscan be foundby:
14 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 www.ti.com SNAS069E –JUNE 1999–REVISED MARCH 2013 where
- S/(N+ D) istheratioofsignaltonoiseand distortion,whichcan varywithfrequency (1) As an example,an ADC10061 witha 5 VP-P,100 kHz sinewave inputsignalwilltypicallyhave a signal-to-noise- plus-distortionratioof59.2dB, whichisequivalentto9.54effectivebits.As theinputfrequencyincreases,noise and distortiongraduallyincrease,yieldinga plotofeffectivebitsor S/(N + D) as shown inTypicalPerformance Characteristics. SPEED ADJUST Inapplicationsthatrequirefasterconversiontimes,theSpeed Adjustpin(pin14 on theADC10062, pin17 on the ADC10064) can significantlyreducetheconversiontime.The speed adjustpinisconnectedtoan on-chipcurrent sourcethatdeterminestheconverter'sinternaltiming.By connectinga resistorbetween thespeed adjustpinand groundas shown inFigure21,theinternalprogrammingcurrentisincreased,whichreducestheconversiontime. As an example,an 18k resistorreducesthe conversiontimeof a typicalpartfrom 600 ns to 350 ns withno significanteffecton linearity.Usingsmallerresistorstofurtherdecreasetheconversiontimeispossibleas well, althoughthelinearitywillbegintodegrade somewhat (seeTypicalPerformanceCharacteristics).Note thatthe resistorvalueneeded toobtaina givenconversiontimewillvaryfromparttopart,so thistechniquewillgenerally requiresome “tweaking”toobtainsatisfactoryresults. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC10061 ADC10062 ADC10064
ADC10061,ADC10062,ADC10064 SNAS069E –JUNE 1999–REVISED MARCH 2013 www.ti.com
REVISION HISTORY
Changes from RevisionD (March 2013)toRevisionE Page
16 SubmitDocumentationFeedback Copyright© 1999–2013,Texas InstrumentsIncorporated
ProductFolderLinks:ADC10061 ADC10062 ADC10064
www.ti.com 1-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC10064CIWM NRND SOIC DW 28 26 TBD Call TI Call TI -40 to 85 ADC10064 CIWM ADC10064CIWM/NOPB ACTIVE SOIC DW 28 26 Green (RoHS & no Sb/Br) SN | CU SN Level-2-260C-1 YEAR -40 to 85 ADC10064 CIWM ADC10064CIWMX/NOPB ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) SN | CU SN Level-3-260C-168 HR -40 to 85 ADC10064 CIWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 1-Nov-2013 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10064CIWMX/NOPB SOIC DW 28 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 2
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated
Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: ADC10064CIWM ADC10064CIWM/NOPB ADC10064CIWMX ADC10064CIWMX/NOPB