ADC1005S060TS

ADC1005S060 IDT | Alldatasheet

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Single 10 bits ADC, up to 60 MHz Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC1005S060 is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 60 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device requires an external source to drive its reference ladder. 2. Features  10-bit resolution (binary or gray code)  Sa mpling rate up to 60 MHz  DC sampling allowed  One clock cycle conversion only  High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 5 MHz full-scale input at fclk = 60 MHz)  No missing cod es guaranteed  In-R ange (IR) CMOS output  TTL and CMOS levels compatible digital inputs  2 .7 V to 3.6 V CMOS digital outputs  Low-lev el AC clock input signal allowed  Exte rnal reference voltage regulator  Powe r dissipation only 312 mW (typical)  L ow analog input capacitance, no buffer amplifier required  No samp le-and-hold circuit required 3. Applications  Video data digitizing  Radar  Bar code scanners  Digit al instrumentation  T ransient signal analysis   m odulators  Medical imaging

ADC1005S060_3 © IDT 2012. All rights reserved. Table 1. Quick reference data VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Table 2. Ordering information

ADC1005S060_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 3 of 18 Integrated Device Technology ADC1005S060 Single 10 bits ADC, up to 60 MHz 6. Block diagram DGND n.c. Rlad RB RM RT VI VCCD VCCA IN-RANGE LATCH CMOS OUTPUTSLATCHES CLOCK DRIVER 014aaa519 CLK 10 15 OE GRAY TC ADC1005S060

13 VCCO

5, 27, 28 Fig 1. Block diagram

ADC1005S060_3 © IDT 2012. All rights reserved.

7.1 Pinning

7.2 Pin description

Table 3. Pin description

ADC1005S060_3 © IDT 2012. All rights reserved. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). the supply voltage differences VCC are respected. Table 5. Thermal characteristics Table 3. Pin description …continued

ADC1005S060_3 © IDT 2012. All rights reserved. Table 6. Characteristics

ADC1005S060_3 © IDT 2012. All rights reserved.

0.5 V < VO < VCCO 20 - +20 A

Table 6. Characteristics …continued

ADC1005S060_3 © IDT 2012. All rights reserved. [1] The rise and fall times of the clock signal must not be less than 0.5 ns. resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. parallel and fed with the same reference source, the matching between each of them is optimized. than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. wave signal) in order to sample the signal and obtain correct output data. signal-to-noise ratio: S/N = ENOB  6.02 + 1.76 dB. same amplitude and the total amplitude of both signals provides full-scale to the converter. load. These parameters are guaranteed by characterization and not by production test.

ADC1005S060_3 © IDT 2012. All rights reserved.

1. Additional information relating to Table 6

Table 7. Output coding and input voltage (typical values; referenced to AGND, V RB = 1.3 V, Table 8. Output coding and input voltage

ADC1005S060_3 © IDT 2012. All rights reserved. Table 9. TC mode selection Table 10. Gray mode selection

ADC1005S060_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 12 of 18 Integrated Device Technology ADC1005S060 Single 10 bits ADC, up to 60 MHz ADC1005S060 OE 10 pF 3.3 kΩ S1TEST VCCDtdLZ VCCDtdZL DGNDtdZH tdHZ DGND 014aaa523 VCCD 50 % 50 % 50 % 10 % 90 % LOW LOW HIGH HIGH OE tdZH tdZL tdHZ VCCD output data LOW output data HIGH tdLZ frequency on pin OE = 100 kHz. Fig 5. Timing diagram and test condit ions of 3-state output delay time 014aaa524 code 1023 code 0 50 % 50 %CLK VI ts(LH) ts(HL) 50 % 50 % 2 ns 2 ns 0.5 ns 0.5 ns Fig 6. Analog input settling time diagram

ADC1005S060_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 13 of 18 Integrated Device Technology ADC1005S060 Single 10 bits ADC, up to 60 MHz 014aaa525 VCCO D9 to D0 IR OGND VCCA VI AGND 014aaa526 Fig 7. D9 to D0 and IR outputs Fig 8. VI analog input 014aaa527 VCCO OGND OE TC GRAY VCCA RT RM RB AGND 014aaa528 RL RL RL RL Fig 9. OE GRAY and TC inputs Fig 10. RB, RM and RT inputs VCCD CLK 1.5 V DGND 014aaa529 Fig 11. CLK input

ADC1005S060_3 © IDT 2012. All rights reserved.

12.1 Application diagrams

The analog and digital supplies should be separated and decoupled. ADC1004S030/040/050 family with an application environment. (2) Decoupling capacitor for supplies must be placed close to the device. (3) This resistor is mandatory (33  is it s minimum value) and must be near the clock source.

12.2 Alternative parts

Table 11. Alternative parts

ADC1005S060_3 © IDT 2012. All rights reserved.

ADC1005S060_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 16 of 18 Integrated Device Technology ADC1005S060 Single 10 bits ADC, up to 60 MHz 13. Package outline UNIT A1 A2 A3 bp cD (1) E(1) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.257.9 7.6 0.9 0.7 1.1 0.7 o o0.13 0.10.2 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 SOT341-1 MO-150 99-12-27 03-02-19 X w M θ A bp D HE Lp Q detail X E Z e c L v M A (A )3 A 11 4 28 15 0.25 y pin 1 index 0 2.5 5 mm scale SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 A max. Fig 13. Package outline SOT341-1 (SSOP28)

ADC1005S060_3 © IDT 2012. All rights reserved. Table 12. Revision history Modifications: Corrections made to INL and DNL conditions in Table• 1. Corrections made to several entries and notes in Table• 6. Correction made to table description in Table• 7. Correction made to column D9 to D0 in Table• 10. Correction made to Figure• 8. Correction made to Figure• 10.

ADC1005S060_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 18 of 18 Integrated Device Technology ADC1005S060 Single 10 bits ADC, up to 60 MHz 16. Contents 11 Additional informa tion relating to Table 6 . . 10