ADC1005

ADC1005 NSC | Alldatasheet

Document overview

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Technical content

Features

n Easy interface to all microprocessors n Differential analog voltage inputs n Operates ratiometrically or with 5 VDC voltage reference or analog span adjusted voltage reference n 0V to 5V analog input voltage range with single 5V supply n On-chip clock generator n TLL/MOS input/output compatible n 0.3" standard width 20-pin DIP Key Specifications n Resolution 10 bits n Linearity Error ±1⁄2 LSB and ±1 LSB n Conversion Time 50 µs Connection Diagram

Ordering Information

Part Number Package Temperature Linearity Outline Range Error ADC1005BCJ-1 J20A 0˚C to +70˚C ±1⁄2 LSB ADC1005BCJ J20A −40˚C to +85˚C ADC1005CCJ-1 J20A 0˚C to +70˚C ±1 LSB ADC1005CCJ J20A −40˚C to +85˚C TRI-STATE® is a registered trademark of National Semiconductor Corporation. ADC 1005 (for an 8–bit data bus) Dual-In-Line Package DS005261-1 Top View June 1999 ADC1005 10-Bit µP Compatible A/D Converter © 1999 National Semiconductor Corporation DS005261 www.national.com

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) 6.5V Logic Control Inputs −0.3V to +15V Voltage at Other Inputs and Outputs −0.3V to V CC +0.3V Input Current Per Pin ±5m A Input Current Per Package ±20 mA Storage Temperature Range −65˚C to +150˚C Package Dissipation at T A =25˚C 875 mW Lead Temperature (Soldering, 10 seconds) Dual-In-Line Package (Ceramic) 300˚C Surface Mount Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C ESD Susceptibility (Note 8) 800V Operating Ratings(Notes 1, 2) Supply Voltage (VCC ) 4.5V to 6.0V Temperature Range T MN ≤TA≤TMAX ADC1005BCJ, ADC1005CCJ −40˚C ≤TA≤+85˚C ADC1005BCJ-1, ADC1005CCJ-1

Electrical Characteristics

The following specifications apply for VCC = 5V, VREF = 5V, fCLK = 1.8 MHz unless otherwise specified.Boldface limits apply from TMIN to TMAX ;All other limits TA = Tj = 25˚C. Parameter Conditions ADC1005BCJ ADC1005BCJ-1, Limit UnitsADC1005CCJ ADC1005CCJ-1 Typ Tested Design Typ Tested Design (Note 5) Limit Limit (Note 5) Limit Limit (Note 6) (Note 7) (Note 6) (Note 7) Converter Characteristics Linearity Error (Note 3) ADC1005BCJ ±0.5 LSB ADC1005BCJ-1 ±0.5 ±0.5 LSB ADC1005CCJ ±1 LSB ADC1005CCJ-1, CCV ±1 ±1 LSB Zero Error ADC1005BCJ ±0.5 LSB ADC1005BCJ-1 ±0.5 ±0.5 LSB ADC1005CCJ ±1 LSB ADC1005CCJ-1, CCV ±1 ±1 LSB Fullscale Error ADC1005BCJ ±0.5 LSB ADC1005BCJ-1 ±0.5 ±0.5 LSB ADC1005CCJ ±1 LSB ADC1005CCJ-1, CCV ±1 ±1 LSB Resistance Common-Mode MIN V CC +0.05 VCC +0.05 VCC +0.05 V Input (Note 4) MAX V IN(+) or VIN(−) GND−0.05 GND−0.05 GND−0.05 V DC Common-Mode Over Error Input Range Power Supply Sensitivity VCC =5V DC ±5% ±1⁄8 ±1⁄4 ±1⁄8 ±1⁄4 ±1⁄4 LSB VREF = 4.75V www.national.com 2

Electrical Characteristics(Continued) The following specifications apply for VCC = 5V, VREF = 5V, fCLK = 1.8 MHz unless otherwise specified.Boldface limits apply from TMIN to TMAX ;All other limits TA = Tj = 25˚C. Parameter Conditions ADC1005BCJ ADC1005BCJ-1, Limit UnitsADC1005CCJ ADC1005CCJ-1 Typ Tested Design Typ Tested Design (Note 5) Limit Limit (Note 5) Limit Limit (Note 6) (Note 7) (Note 6) (Note 7) DC Characteristics V IN(1)Logical “1” Input V CC =5.25V 2.0 2.0 2.0 V Voltage MIN (except CLK IN ) VIN(0), Logical “0” Input VCC =4.75V 0.8 0.8 0.8 V Voltage MAX (Except CLK IN ) IIN, Logical “1” Input V IN=5.0V 0.005 1 0.005 1 1 µA Current MAX I IN, Logical “0” Input V IN=0V −0.005 −1 −0.005 −1 −1 µA Current MAX V T+(MIN), Minimum CLKIN Voltage V T(MAX), Maximum CLKIN Voltage V T−(MIN), Minimum CLKIN Voltage V T−(MAX), Maximum CLKIN Voltage V Hysteresis (VT+-VT−) Hysteresis (VT+-VT−) VOUT(1), Logical “1” V CC =4.75V Output Voltage MIN I OUT =−360 µA 2.4 2.8 2.4 V IOUT =−10 µA 4.5 4.6 4.5 V VOUT(0), Logical “0” V CC =4.75V 0.4 0.34 0.4 V Output Voltage MAX I OUT =1.6 mA IOUT , TRI-STATE Output V OUT = 0V −0.01 −3 −0.01 −0.3 −3 µA Current MAX V OUT = 5V 0.01 3 0.01 0.3 3 µA ISOURCE , Output Source V OUT =0V −14 −6.5 −14 −7.5 −6.5 mA Current MIN I SINK, Output Sink V OUT =5V 16 8.0 16 9.0 8.0 mA Current MIN I CC , Supply Current MAX fCLK =1.8 MHz 1.5 3 1.5 2.5 3 mA CS =“1” www.national.com3

The following specifications apply for VCC = 5V, VREF = 5V,VREF = 5V, tr=tf= 20 ns unless otherwise specified.Boldface lim- its apply from TMIN to TMAX ;All other limits TA = Tj = 25˚C. Typ Tested Design Limit Parameter Conditions (Note 5) Limit Limit Units (Note 6) (Note 7) fCLK , Clock Frequency MIN 0.2 0.2 MHz MAX 2.6 2.6 MHz Clock Duty Cycle MIN 40 40 % MAX 60 60 % tC , Conversion Time MIN 80 80 1/f CLK MAX 90 90 1/f CLK MIN f CLK =1.8 MHz 45 45 µs MAX f CLK =1.8 MHz 50 50 µs tW(WR)L , Minimum WR Pulse Width CS =0 100 150 150 ns tACC , Access Time (Delay from falling edge of RD to Output Data Valid) CS =0 170 300 300 ns C L=100 pF, RL = 2k t1H ,t0H , TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) R L=10k, CL=10 pF 125 200 ns R L=2k, CL=100 pF 145 230 230 ns tWI,tRI, Delay from Falling Edge of WR or RD to Reset of INTR 300 450 450 ns tIRS, INTR to 1st Read Set-up Time 400 550 550 ns C IN, Capacitance of Logic Inputs 5 7.5 pF C OUT , Capacitance of Logic Outputs 5 7.5 pF Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2:All voltages are measured with respect to ground. Note 3:Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through the end points of the transfer characteristic. Note 4:For VIN(−)≥VIN(+)the digital output code will be 00 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC t o5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5:Typicals are at 25˚C and represent most likely parametric norm. Note 6:Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 7:Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 8:Human body model, 100 pF discharged through a 1.5 kΩ resistor. www.national.com 4

Typical Performance Characteristics DS005261-3 Logic Input Threshold Voltage vs Supply Voltage DS005261-21 Delay from Falling Edge of RD to Output data Valid vs Load Capacitance DS005261-22 CLK IN Schmitt Trip Levels vs Supply Voltage DS005261-23 Output Current vs Temperature DS005261-24 Typical Linearity Error vs Clock Frequency DS005261-25 www.national.com5

Byte Sequencing for ADC1005 Byte 8-Bit Data Bus Connection Order DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB 1st Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB 2 n d B i t 1 B i t 0 000000 Start Conversion DS005261-5 Output Enable and Reset INTR DS005261-6 Note:All timing is measured from the 50% voltage points. www.national.com 6

1.0 GENERAL OPERATION

A block diagram of the A/D converter is shown inFigure 1. All of the inputs and outputs are shown and the major logic con- trol paths are drawn in heavier weight lines.

1.1 Converter Operation

The ADC1005 uses an advanced potentiometric resistive ladder network. The analog inputs, as well as the taps of this ladder network are switched into a weighted capacitor array. The output of this capacitor array is the input to a sampled data comparator. This comparator allows the successive ap- proximation logic to match the analog input voltage [V IN(+) – VIN(−)] to taps on the R network. The most significant bit is tested first and after 10 comparisons (80 clock cycles) a digi- tal 10-bit binary code (all “1”s= full-scale) is transferred to an output latch.

1.2 Starting a Conversion

The conversion is initialized by taking CS and WR simulta- neously low. This sets the start flip-flop (F/F) and the result- ing “1” level resets the 10-bit shift register, resets the inter- rupt (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the input end of the 10-bit shift register. Internal clock sig- nals then transfer this “1” to the Q ouput of F/F1. The AND gate, G1, combines this “1” output with a clock signal to pro- vide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 10-bit shift register then can have the “1” clocked in, allowing the conversion process to continue. If the set signal were still present, this reset pulse would have no effect and the 10-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR sig- nals. The converter will start after at least one of these sig- nals returns high and the internal clocks again provide a re- set signal for the start F/F. To summarize, on the high-to-low transition of the WR input the internal SAR latches and the shift register stages are re- set. As long as the CS input and WR input remain low, the A/D will remain in a reset state.Conversion will start after at least one of these inputs makes a low-to-high transition.

1.3 Output Control

After the “1” is clocked through the 10-bit shift register (which completes the SAR search) it causes the new digital word to transfer to the TRI-STATE output latches. When the XFER DS005261-11 Note 9:CS shown twice for clarity. Note 10:SAR =Successive Approximation Register. FIGURE 1. www.national.com7

signal the end of the conversion (by a high-to-low transition). TRI-STATE output latches will be enabled.

1.4 Free-Running and Self-Clocking Modes

power-up cycle to ensure start up.

2.0 REFERENCE VOLTAGE

used for the successive approximation conversion. code for a given input condition. low current devices to use with these converters.

3.0 THE ANALOG INPUTS

3.1 Analog Differential Voltage Inputs and

FIGURE 2. Self-Clocking the A/D FIGURE 3. Ratiometric FIGURE 4. Absolute with a Reduced Span

Functional Description(Continued) change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal, this error is: where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value and fCLK is the clock fre- quency at the CLK IN pin. For a 60 Hz common-mode signal to generate a1⁄4 LSB error (1.2 mV) with the converter running at 1.8 MHz, its peak value would have to be 1.46V. A common-mode signal this large is much greater than that generally found in data aqui- sition systems.

3.2 Input Current

Due to the sampling nature of the analog inputs, short dura- tion spikes of current enter the “+” input and exit the “−” input at the clock rising edges during the conversion. These cur- rents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period.

3.3 Input Bypass Capacitors

Bypass capacitors at the inputs will average the current spikes noted in 3.2 and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the V IN(+) input voltage at full scale. For continuous conversions with a 1.8 MHz clock frequency with the VIN(+) input at 5V, this DC current is at a maximum of approxi- mately 5 µA. Therefore, bypass capacitors should not be used at the analog inputs or the VREF pinfor high resistance sources (>1k Ω ). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental effects of the volt- age drop across this input resistance, which is due to the av- erage value of the input current, can be eliminated with a full-scale adjustment while the given source resistor and in- put bypass capacitor are both in place. This is possible be- cause the average value of the input current is a linear func- tion of the differential input voltage.

3.4 Input Source Resistance

Large values of source resistance where an input bypass ca- pacitor is not used, will not cause errorsif the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (≤1 kΩ ) for a passive RC section or add an op amp RC active low pass filter. For low source resistance applications (≤0.1 kΩ ) a 4700 pF bypass capacitor at the inputs will prevent pickup due to series lead induction of a long wire. A 100Ω se- ries resistor can be used to isolate this capacitor – both the R and the C are placed outside the feedback loop – from the output of an op amp, if used.

3.5 Noise

The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize input noise coupling. Both noise and undesired digital clock coupling to these inputs can cause system errors. The source resistance for these in- puts should, in general, be kept below 1 kΩ . Larger values of source resistance can cause undesired system noise pickup. Input bypass capacitors, placed from the analog in- puts to ground, can reduce system noise pickup but can cre- ate analog scale errors. See section 3.2, 3.3, and 3.4 if input filtering is to be used.

4.0 OFFSET AND REFERENCE ADJUSTMENT

4.1 Zero Offset

The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V(−) input and applying a small magnitude positive voltage to the V(+) input. Zero error is the difference between the actual DC input voltage that is necessary to just cause an output digital code transition from 00 0000 0000 to 00 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 2.45 mV for VREF = 5.0 VDC ). The zero of the A/D normally does not require adjustment. However, for cases where VIN(MIN)is not ground and in re- duced span applications (VREF < 5V), an offset adjustment may be desired. The converter can be made to output an all zero digital code for an arbitrary input by biasing the A/D’s V IN(−) input at that voltage. This utilizes the differential input operation of the A/D.

4.2 Full Scale

The full-scale adjustment can be made by applying a differ- ential input voltage that is 11⁄2 LSB down from the desired analog full-scale voltage range and then adjusting the mag- nitude of the V REF input for a digital output code that is just changing from 111111 1110 to 11 1111 1111.

4.3 Adjusting for an Arbitrary Analog

If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal that does not go to ground), this new zero reference should be properly adjusted first. A V IN(+) voltage that equals this desired zero reference plus1⁄2 LSB (where the LSB is calcu- lated for the desired analog span, 1 LSB= analog span/ 1024) is applied to selected “+” input and the zero reference voltage at the corresponding “−” input should then be ad- justed to just obtain the 000 HEX 001HEX code transition. The full-scale adjustment should be made [with the proper VIN(−) voltage applied] by forcing a voltage to the VIN(+) in- put given by: where VMAX = the high end of the analog input range and VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced). The VREF (or VCC ) voltage is then adjusted to provide a code change from 3FFHEX to 3FEHEX . This completes the adjust- ment procedure. For an example see the Zero-Shift and Span-Adjust circuit below.

5.0 POWER SUPPLIES

Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A low in- ductance tantalum filter capacitor should be used close to the converter V CC pin and values of 1 µF or greater are rec- ommended. If an unregulated voltage is available in the sys- www.national.com9

should be returned to the analog ground point. FIGURE 5. Zero-Shift and Span-Adjust (2V≤ VIN ≤ 5V)

Typical Applications(Continued) TRI-STATE Test Circuits and Waveforms Operating with Ratiometric Transducers DS005261-14 VIN(−)= 0.15 VCC 15% of VCC ≤ VXDR ≤ 85% of VCC Handling ±5V Analog Inputs DS005261-15 t1H DS005261-7 tIH,C L=10 pF DS005261-9 tr=20 ns t0H DS005261-8 tIH,C L=10 pF DS005261-10 tr=20 ns www.national.com11

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