ADC1004S030 IDT | Alldatasheet
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Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Rev. 04 — 2 July 2012 Product data sheet 1. General description The ADC1004S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Tran sistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device requires an external source to drive its reference ladder. If the application r equires that the reference is driven via internal sources, Integrated Device Technology recommends you use one of the ADC1003S030/040/050 family. 2. Features 10-bit resolution Sa mpling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) No missing cod es guaranteed In-R ange (IR) CMOS output TTL and CMOS levels compatible digital inputs 3 V to 5 V CMOS digital outputs Low-lev el AC clock input signal allowed Exte rnal reference voltage regulator Powe r dissipation only 175 mW (typical) L ow analog input capacitance, no buffer amplifier required No samp le-and-hold circuit required 3. Applications Video data digitizing Radar T ransient signal analysis m odulators Medical imaging Bar code scanner Global Pos itioning System (GPS) receiver
Table 1. Quick reference data Tamb = 25 C; unless otherwise specified. Table 2. Ordering information
ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 3 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 6. Block diagram DGND2 Rlad RB RM RT VI VCCD2 VCCA 20 D4 17 D1 16 D0 IN-RANGE LATCH CMOS OUTPUTSLATCHES CLOCK DRIVER 014aaa336 CLK OE TC ADC1004S030/040/050
13 VCCO
analog ground digital ground digital ground DGND1 OGND output ground analog voltage input data outputs LSB MSB
28 VCCD1
Fig 1. Block diagram
7.1 Pinning
7.2 Pin description
Table 3. Pin description
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). the supply voltage differences VCC are respected. Table 5. Thermal characteristics Table 3. Pin description …continued
Table 6. Characteristics VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified.
0.5 V < VO < VCCO
Table 6. Characteristics …continued VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified.
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified.
ROB and ROT as shown in Figure 3. connected in parallel and fed with the same reference source, the matching between each of them is optimized. than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. wave signal) in order to sample the signal and obtain correct output data. VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified.
signal-to-noise ratio: SINAD = ENOB 6.02 + 1.76 dB. the same amplitude and the total amplitude of both signals provides full-scale to the converter. Technology recommends the lowest possible output load.
- Additional information relating to Table 6
Table 7. Output coding and input voltage (typical values; referenced to AGND, V RB = 1.3 V,
Table 8. Mode selection
ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 12 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz LOW HIGH HIGH LOW ADC1004S050 VCCD VCCD OE OE output data output data 10% 50% 50% 90% 50% tdLZ tdZL tdHZ tdZH 15 pF 3.3 kΩ S1TEST VCCDtdLZ VCCDtdZL DGNDtdZH tdHZ DGND 014aaa335 frequency on pin OE = 100 kHz Fig 5. Timing diagram and test conditions of 3-state output delay time 014aaa327 code 1023 code 0 50% 50%CLK VI ts(LH) ts(HL) 50% 50% 2 ns 2 ns 0.5 ns 0.5 ns Fig 6. Analog input settling time diagram
ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 13 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 014aaa328 −60 −100 −20 +20 amplitude (dB) −140 f (MHz) 0 20.015.05.00 10.0 Effective bits: 9.42; THD = 71.8 dB. Fig 7. Typical fast Fourier transform (f clk = 40 MHz; fi = 4.43 MHz) f (MHz) 014aaa329 −60 −100 −20 +20 amplitude (dB) −140 Effective bits: 8.91; THD = 62.96 dB. Fig 8. Typical fast Fourier transform (f clk = 50 MHz; fi = 10 MHz)
ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 14 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 014aaa330 VCCO D9 to D0 IR OGND VCCA VI AGND 014aaa332 Fig 9. CMOS data and in-range outputs Fig 10. Analog inputs 014aaa323 VCCO OGND OE TC VCCA RT RM RB AGND 014aaa331 RL RL RL RL Fig 11. OE and TC input Fig 12. RB, RM and RT VCCD CLK 1.5 V DGND 014aaa324 Fig 13. CLK input
(1) RB, RM and RT are decoupled to AGND. (2) Pin 15 may be connected to DGND in or der to prevent noise influence. (3) Decoupling capacitor for supplies; must be placed close to the de vice.
12.1 Alternative parts
Table 9. Alternative parts
30 MHz
40 MHz
50 MHz
ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 16 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 13. Package outline UNIT A1 A2 A3 bp cD (1) E(1) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.257.9 7.6 0.9 0.7 1.1 0.7 o o0.13 0.10.2 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 SOT341-1 MO-150 99-12-27 03-02-19 X w M θ A bp D HE Lp Q detail X E Z e c L v M A (A )3 A 11 4 28 15 0.25 y pin 1 index 0 2.5 5 mm scale SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 A max. Fig 15. Package outline SOT341-1 (SSOP28)
Table 10. Revision history Modifications: Corrections made to the table description in Table• 1. Corrections made to several entries in Table• 6. Corrections made to Figure• 12.
ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 18 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 16. Contents 11 Additional informa tion relating to Table 6 . . 10