ADC1004S030 NXP | Alldatasheet
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Technical content
- General description The ADC1004S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters (ADC) for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device requires an external source to drive its reference ladder. If the application requires that the reference is driven via internal sources, NXP Semiconductors recommends you use one of the ADC1003S030/040/050 family. 2. Features n 10-bit resolution n Sampling rate up to 50 MHz n DC sampling allowed n One clock cycle conversion only n High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk= 40 MHz) n No missing codes guaranteed n In-Range (IR) CMOS output n TTL and CMOS levels compatible digital inputs n 3 V to 5 V CMOS digital outputs n Low-level AC clock input signal allowed n External reference voltage regulator n Power dissipation only 175 mW (typical) n Low analog input capacitance, no buffer amplifier required n No sample-and-hold circuit required 3. Applications n Video data digitizing n Radar n Transient signal analysis n ΣΔ modulators n Medical imaging n Barcode scanner n Global Positioning System (GPS) receiver ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Rev. 03 — 7 August 2008 Product data sheet
Table 1. Quick reference data Tamb = 25°C; unless otherwise specified. Table 2. Ordering information
ADC1004S030_040_050_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 August 2008 3 of 19 NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 6. Block diagram Fig 1. Block diagram DGND2 R lad RB RM RT VI VCCD2 VCCA 20 D4 17 D1 16 D0 IN-RANGE LATCH CMOS OUTPUTSLATCHES CLOCK DRIVER 014aaa336 CLK OE TC ADC1004S030/040/050
13 VCCO
analog ground digital ground digital ground DGND1 OGND output ground analog voltage input data outputs LSB MSB
28 VCCD1
7.1 Pinning
7.2 Pin description
Table 3. Pin description
the supply voltage differencesΔVCC are respected. Table 3. Pin description …continued Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 5. Thermal characteristics
Table 6. Characteristics VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25°C; unless otherwise specified.
0.5 V < VO <V CCO
Table 6. Characteristics …continued VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25°C; unless otherwise specified.
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25°C; unless otherwise specified.
to code 1023 at Tamb = 25°C. OB and ROT as shown inFigure3. connected in parallel and fed with the same reference source, the matching between each of them is optimized. than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. wave signal) in order to sample the signal and obtain correct output data. VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25°C; unless otherwise specified.
signal-to-noise ratio: SINAD = ENOB× 6.02 + 1.76 dB. the same amplitude and the total amplitude of both signals provides full-scale to the converter. recommends the lowest possible output load.
- Additional information relating toTable6
Table 7. Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V,
Table 8. Mode selection
ADC1004S030_040_050_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 August 2008 12 of 19 NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz frequency on pinOE = 100 kHz Fig 5. Timing diagram and test conditions of 3-state output delay time Fig 6. Analog input settling time diagram LOW HIGH HIGH LOW ADC1004S050 VCCD VCCD OE OE output data output data 10% 50% 50% 90% 50% tdLZ tdZL tdHZ tdZH 15 pF 3.3 kW S1TEST VCCDtdLZ VCCDtdZL DGNDtdZH tdHZ DGND 014aaa335 014aaa327 code 1023 code 0 50% 50%CLK VI ts(LH) ts(HL) 50% 50% 2 ns 2 ns 0.5 ns 0 .5 ns
ADC1004S030_040_050_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 August 2008 13 of 19 NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Effective bits: 9.42; THD =−71.8 dB. Fig 7. Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz) 014aaa328 -60 -100 -20 +20 amplitude (dB) -140 f (MHz) 0 20.015.05.00 10.0 Effective bits: 8.91; THD =−62.96 dB. Fig 8. Typical fast Fourier transform (fclk = 50 MHz; fi = 10 MHz) f (MHz) 014aaa329 -60 -100 -20 +20 amplitude (dB) -140
ADC1004S030_040_050_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 August 2008 14 of 19 NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Fig 9. CMOS data and in-range outputs Fig 10. Analog inputs Fig 11.OE and TC input Fig 12. RB, RM and RT 014aaa330 VCCO D9 to D0 IR OGND VCCA VI AGND 014aaa332 014aaa323 VCCO OGND OE TC VCCA RT RM RB AGND 014aaa331 R L R L R L R L Fig 13. CLK input VCCD CLK 1.5 V DGND 014aaa324
12.1 Alternative parts
(1) RB, RM and RT are decoupled to AGND. (2) Pin 15 may be connected to DGND in order to prevent noise influence. (3) Decoupling capacitor for supplies; must be placed close to the device. Table 9. Alternative parts
30 MHz
40 MHz
50 MHz
ADC1004S030_040_050_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 August 2008 16 of 19 NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 13. Package outline Fig 15. Package outline SOT341-1 (SSOP28) UNIT A 1 A 2 A 3 bp cD (1) E (1) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.257.9 7.6 0.9 0.7 1.1 0.7 o o0.13 0.10.2 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 SOT341-1 MO-150 99-12-27 03-02-19 X w M q A A 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A 11 4 28 15 0.25 y pin 1 index 0 2.5 5 mm scale SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 A max.
Table 10. Revision history
- Corrections made to the table description inTable1.
- Corrections made to several entries inTable6.
- Corrections made toFigure12. ADC1004S030_040_050_2 20080616 Product data sheet - ADC1004S030_040_050_1 ADC1004S030_040_050_1 20080611 Product data sheet - -
ADC1004S030_040_050_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 7 August 2008 18 of 19 NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz 15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values —Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data —The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 August 2008 Document identifier: ADC1004S030_040_050_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents
11 Additional information relating to
Table6 . . . 10