ADC10040

ADC10040 NSC | Alldatasheet

Document overview

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Technical content

Features

n Single +3.0V operation n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 V P-P full-scale input swing n 400 MHz −3 dB input bandwidth n Low power consumption n Standby mode n On-chip reference and sample-and-hold amplifier n Offset binary or two’s complement data format n Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families n 28-pin TSSOP package Key Specifications n Resolution 10 Bits n Conversion Rate 40 MSPS n Full Power Bandwidth 400 MHz n DNL ±0.3 LSB (typ) n SNR (fIN = 11 MHz) 59.6 dB (typ) n SFDR (fIN = 11 MHz) −80 dB (typ) n Data Latency 6 Clock Cycles n Supply Voltage +3.0V n Power Consumption, 40 MHz 55.5 mW

Applications

n Cellular Based Stations/Communications Receivers n Sonar/Radar n xDSL n Wireless Local Loops n Data Acquisition Systems n DSP Front Ends Connection Diagram 20077801 November 2004 ADC10040 10-Bit 40 MSPS 3V, 55 mW A/D Converter © 2004 National Semiconductor Corporation DS200778 www.national.com

Ordering Information

Industrial (−40˚C ≤ TA ≤ +85˚C) NS Package ADC10040CIMT 28 Pin TSSOP ADC10040CIMTX 28 Pin TSSOP Tape & Reel Block Diagram 20077802 ADC10040 www.national.com 2

Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O

12 V IN−

Inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 V P-P. This pin may be tied to VCOM (pin 4) for single-ended operation.

13 V IN+

Non-inverting analog input signal. With a 1.2V reference the full-scale input signal level is 1.0 V P-P. 6V REF Reference input. This pin should be bypassed to V SSA with a 0.1 µF monolithic capacitor. V REF is 1.20V nominal. This pin may be driven by a 1.20V external reference if desired. Do not load this pin. REFT VREFT and VREFB are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to V SSA. These pins should not be loaded. V COM should also be bypassed with a 0.1 µF capacitor to V SSA.V COM may be used to set the input common voltage V CM. 4V COM 8V REFB DIGITAL I/O

1 CLK

Digital clock input. The range of frequencies for this input is 20 MHz to 40 MHz. The input is sampled on the rising edge of this input.

15 DF DF = “1” Two’s Complement

DF = “0” Offset Binary

28 STBY

This is the standby pin. When high, this pin sets the converter into standby mode. When this pin is low, the converter is in active mode.

5 IRS (Input Range

Select) I R S=“ V DDA” 2.0 VP-P input range I R S=“ VSSA” 1.5 VP-P input range IRS = “Floating” 1.0 VP-P input range If using both V IN+ and VIN- pins, (or differential mode), then the peak-to-peak voltage refers to the differential voltage IN+-V IN-). ADC10040 www.national.com3

Pin Descriptions and Equivalent Circuits (Continued) Pin No. Symbol Equivalent Circuit Description 16–20, 23–27 D0–D9 Digital output data. D0 is the LSB and D9 is the MSB of the binary output word. ANALOG POWER 2, 9, 10 V DDA Positive analog supply pins. These pins should be connected to a quiet 3,0V source and bypassed to analog ground with a 0.1 µF monolithic capacitor located within 1 cm of these pins. A 4.7 µF capacitor should also be used in parallel. 3, 11, 14 V SSA Ground return for the analog supply. DIGITAL POWER

22 V DDIO

Positive digital supply pins for the ADC10040’s output drivers. This pin should be bypassed to digital ground with a 0.1 µF monolithic capacitor located within 1 cm of this pin. A 4.7 µF capacitor should also be used in parallel. The voltage on this pin should never exceed the voltage on V DDA by more than 300 mV.

21 V SSIO

The ground return for the digital supply for the output drivers. This pin should be connected to the digital ground, but not near the analog ground. ADC10040 www.national.com 4

Absolute Maximum Ratings (Notes 1, If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V DDA,V DDIO 3.9V Voltage on Any Pin to GND −0.3V to V DDA or VDDIO +0.3V Input Current on Any Pin ±25 mA Package Input Current (Note 3) ±50 mA Package Dissipation at T = 25˚C See (Note 4) ESD Susceptibility Human Body Model (Note 5) 2500V Machine Model (Note 5) 250V Soldering Temperature Infrared, 10 sec. (Note 6) 235˚C Storage Temperature −65˚C to +150˚C Operating Ratings Operating Temperature Range −40˚C ≤ TA ≤ +85˚C VDDA (Supply Voltage) +2.7V to +3.6V VDDIO (Output Driver Supply Voltage) +2.5V to V DDA VREF 1.20V |VSSA–VSSIO| ≤ 100 mV NOTE: Absolute maximum ratings are limiting values, to be applied individu- ally, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily im- plied. Exposure to maximum ratings for extended periods may affect device reliability. Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for V SSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.20V, (External Supply) f CLK = 40 MHz, 50% Duty Cycle, C L = 10 pF/pin. Boldface limits apply for TA =T MIN to TMAX: all other limits T A = 25˚C. Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No Missing Codes Guaranteed 10 Bits INL Integral Non-Linearity (Note 11) FIN = 250 kHz, −0 dB Full Scale −1.0 ±0.3 +1.0 LSB DNL Differential Non-Linearity FIN = 250 kHz, −0 dB Full Scale −0.9 ±0.3 +0.9 LSB GE Gain Error Positive Error −1.5 +0.4 +1.9 %F S Negative Error −1.5 −0.01 +1.9 %F S OE Offset Error (V IN+=V IN−) −1.4 0.12 +1.6 %F S Under Range Output Code 0 Over Range Output Code 1023 FPBW Full Power Bandwidth 400 MHz REFERENCE AND INPUT CHARACTERISTICS V CM Common Mode Input Voltage 0.5 1.5 V VCOM Output Voltage for use as an input common mode voltage (Note 16) 1.45 V V REF Reference Voltage 1.2 V VREFTC Reference Voltage Temperature Coefficient ±80 ppm/˚C POWER SUPPLY CHARACTERISTICS IVDDA Analog Supply Current STBY = 1 4.5 6.0 mA STBY = 0 18 25 mA IVDDIO Digital Supply Current S T B Y=1 ,fIN =0H z 0 m A S T B Y=0 ,fIN =0H z 0 . 6 0.8 mA PWR Power Consumption STBY = 1 13.5 18 mW STBY = 0 55.5 77 mW ADC10040 www.national.com5

DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.20V, (Externally Supplied) fCLK = 40 MHz, 50% Duty Cycle, C L = 10 pF/pin. Boldface limits apply for T A =T MIN to TMAX: all other limits T A = 25˚C Symbol Parameter Conditions Min Typ Max Units CLK, DF, STBY, SENSE Logical “1” Input Voltage 2 V Logical “0” Input Voltage 0.8 V Logical “1” Input Current +10 µA Logical “0” Input Current −10 µA D0–D9 OUTPUT CHARACTERISTICS Logical “1” Output Voltage I OUT = −0.5 mA VDDIO−0.2 V Logical “0” Output Voltage I OUT = 1.6 mA 0.4 V DYNAMIC CONVERTER CHARACTERISTICS ENOB Effective Number of Bits fIN = 11 MHz 9.4, 9.3 9.6 Bits fIN = 19 MHz 9.4, 9.3 9.6 Bits SNR Signal-to-Noise Ratio fIN = 11 MHz 58.7, 58.1 59.6 dB fIN = 19 MHz 58.6, 58 59.5 dB SINAD Signal-to-Noise Ratio + Distortion fIN = 11 MHz 58.6, 58 59.5 dB fIN = 19 MHz 58.5, 57.8 59.4 dB 2nd HD 2nd Harmonic fIN = 11 MHz −75.9, −74.7 −89 dBc fIN = 19 MHz −74.4, −73 −86 dBc 3rd HD 3rd Harmonic fIN = 11 MHz −69.5, −67.5 −78 dBc fIN = 19 MHz −68.8, −66.7 −77 dBc THD Total Harmonic Distortion (First 6 Harmonics) fIN = 11 MHz −69.5, −67.5 −78 dB f.IN = 19 MHz −68.8, −66.7 −77 dB SFDR Spurious Free Dynamic Range (Excluding 2nd and 3rd Harmonic) fIN = 11 MHz −75.8, −74.5 −80 dBc fIN = 19 MHz −75.7, −74.3 −80 dBc ADC10040 www.national.com 6

Unless otherwise specified, the following specifications apply for V SSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2V P-P (full scale), STBY = 0V, V REF = 1.20V, (Externally Supplied), f CLK = 40 MHz, 50% Duty Cycle, C L = 10 pF/pin. Boldface limits apply for T A =T MIN to TMAX: all other limits T A = 25˚C Symbol Parameter Conditions Min (Note 11) Typ (Note 11) Max (Note 11) Units CLK, DF, STBY, SENSE fCLK1 Maximum Clock Frequency 40 MHz (min) fCLK2 Minimum Clock Frequency 20 MHz tCH Clock High Time 12.5 ns tCL Clock Low Time 12.5 ns tCONV Conversion Latency 6 Cycles tOD Data Output Delay after a Rising Clock Edge T = 25˚C 2 3.3 5 ns 16 ns tAD Aperture Delay 1 ns tAJ Aperture Jitter 2 ps (RMS) Over Range Recovery Time Differential VIN step from ±3V to 0V to get accurate conversion

1 Clock Cycle

tSTBY Standby Mode Exit Cycle 20 Cycles Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Note 2: All voltages are measured with respect to GND = V SSA =V SSIO = 0V, unless otherwise specified. Note 3: When the voltage at any pin exceeds the power supplies (V IN < VSSA or VIN > VDDA,V DDIO or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (T Jmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by T Jmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDM A X=( TJmax − TA)/θJA. In the 28-pin TSSOP, θJA is 96˚C/W, so PDMAX = 1,302 mW at 25˚C and 677 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this device under normal operation will typically be about 55.5 mW. The values for maximum power dissipation listed above will be reached only when theADC10040 is operated in a severe fault condition. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through 0 Ω. Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top of the package body above 183˚C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above 183˚C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above V DDA or VDDIO and below VSSA or VSSIO. 20077807 Note 7: To guarantee accuracy, it is required that |V DDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 8: With the test condition for 2 V P-P differential input, the 10-bit LSB is 1.95 mV. Note 9: Typical figures are at TA =T J = 25˚C and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and nega tive full-scale. Note 11: Timing specifications are tested at TTL logic levels, V IL = 0.4V for a falling edge, and V IH = 2.4V for a rising edge. Note 12: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V. Note 13: VDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply output driver supply voltage, C n is the total load capacitance on the output pin, and f n is the average frequency at which the pin is toggling. Note 14: Power consumption includes output driver power. (f IN = 0 MHz). Note 15: The input bandwidth is limited using a 10 pF capacitor between V IN− and VIN+. Note 16: VCOM is a typical value, measured at room temperture. It is not guaranteed by test. ADC10040 www.national.com7

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (V CM) is the d.c. potential present at both signal inputs to the ADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The speci- fication here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full-Scale Error − Negative Full- Scale Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale ( 1⁄2 LSB below the first code transition) through positive full scale ( 1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC10040 is guaranteed not to have any missing codes. NEGATIVE FULL SCALE ERRORis the difference between the input voltage (V IN+ −V IN−) just causing a transition from negative full scale to the first code and its ideal value of 0.5 LSB. OFFSET ERROR is the input voltage that will cause a tran- sition from a code of 011111 1111 to acode of 10 0000 0000. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY)is the number of clock cycles between initiation of conversion and when that data is pre- sented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1 1⁄2 LSB below positive full scale. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or dc. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral compo- nents below half the clock frequency, including harmonics but excluding dc. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ- ence, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, ex- pressed in dBc, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated as: where f 1 is the RMS power of the fundamental (output) frequency and f2 through f6 are the RMS power in the first 6 harmonic frequencies. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the dif- ference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd har- monic level at the output. ADC10040 www.national.com 8

Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.2V, (External Supply) f CLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. DNL DNL vs. f CLK 20077812 20077815 DNL vs. Clock Duty Cycle (DC input) DNL vs. Temperature 20077813 20077816 INL INL vs. f CLK 20077814 20077817 ADC10040 www.national.com 10

Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.2V, (External Supply) f CLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. (Continued) INL vs. Clock Duty Cycle SNR vs. V DDIO 20077818 20077819 SNR vs. VDDA SNR vs. fCLK 20077820 20077821 INL vs. Temperature SNR vs. Clock Duty Cycle 20077822 20077823 ADC10040 www.national.com11

Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.2V, (External Supply) f CLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. (Continued) SNR vs. Temperature THD vs. V DDA 20077824 20077825 THD vs. VDDIO THD vs. fCLK 20077826 20077827 SNR vs. IRS THD vs. IRS 20077828 20077829 ADC10040 www.national.com 12

Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.2V, (External Supply) f CLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. (Continued) SINAD vs. VDDA SINAD vs. VDDIO 20077830 20077831 THD vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle 20077832 20077833 THD vs. Temperature SINAD vs. Temperature 20077834 20077835 ADC10040 www.national.com13

Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.2V, (External Supply) f CLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. (Continued) SINAD vs. fCLK SFDR vs. VDDIO 20077836 20077837 SINAD vs. IRS SFDR vs. f CLK 20077838 20077839 SFDR vs. VDDA SFDR vs. IRS 20077840 20077841 ADC10040 www.national.com 14

Typical Performance Characteristics Unless otherwise specified, the following specifications apply: VSSA =V SSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =2V P-P, STBY = 0V, V REF = 1.2V, (External Supply) f CLK = 40 MHz, fIN = 19 MHz, 50% Duty Cycle. (Continued) SFDR vs. Clock Duty Cycle Spectral Response @ 11 MHz Input 20077842 20077843 SFDR vs. Temperature Spectral Response @ 19 MHz Input 20077844 20077845 ADC10040 www.national.com15

correction circuitry to help ensure maximum performance.

1.0 ANALOG INPUTS

The ADC10040 has two analog signal inputs, VIN+ and VIN−.

1.1 REFERENCE PINS

to ground with a 0.1 µF capacitor. DO NOT LOAD these pins. pins hould be bypassed with at least a 0.1uF capacitor.

1.3 SIGNAL INPUTS

A single ended input signal is shown in Figure 4. tors form a low-pass filter with a -3 dB frequency of 177 Mhz.

1.4 CLK PIN

The CLK signal controls the timing of the sampling process. duty cycle range of 40% to 60%.

1.5 STBY PIN

being used. The power consumption in this state is 13.5 mW. data in the pipeline is corrupted while in the power down.

1.6 DF PIN

1.7 IRS PIN

below describes the function of the IRS pin. FIGURE 3. Input Voltage Waveforms for a 2V P-P FIGURE 4. Input Voltage Waveform for a 2V P-P Single

TABLE 1. IRS Pin Functions

1.8 OUTPUT PINS

1.9 APPLICATION SCHEMATICS

input. Figure 6shows a single ended application circuit. FIGURE 5. A Simple Application Using a Differential Driving Source

FIGURE 6. A Simple Application Using a Single Ended Driving Source

Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead TSSOP Package National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com ADC10040 10-Bit 40 MSPS 3V, 55 mW A/D Converter