ADC10030

ADC10030 NSC | Alldatasheet

Document overview

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Technical content

Features

n Internal Sample-and-Hold n Single +5V Operation n Low Power Standby Mode n Guaranteed No Missing Codes n TRI-STATE® Outputs n TTL/CMOS or 3V Logic Input/Output Compatible Key Specifications n Resolution 10 Bits n Conversion Rate 30 Msps n ENOB @ 15 MHz Input 9.1 Bits (typ) n DNL 0.40 LSB (typ) n Conversion Latency 2 Clock Cycles n PSRR 56 dB n Power Consumption 125 mW (typ) n Low Power Standby Mode <3.5 mW (typ)

Applications

TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS101064-1 January 2000 ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold © 2000 National Semiconductor Corporation DS101064 www.national.com

Ordering Information

Commercial Temperature Range (−40˚C≤ TA ≤ +85˚C) NS Package ADC10030CIVT TQFP Block Diagram DS101064-2 ADC10030 www.national.com 2

Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description

30 V IN

Analog Input signal to be converted. Conversion range is VREF + St oVREF − S.

31 V REF + F

Analog input that goes to the high side of the reference ladder of the ADC. This voltage should force V REF + S to be in the range of 2.6V to 3.8V.

32 V REF + S Analog output used to sense the voltage at the top

of the ADC reference ladder. 2V REF − F Analog input that goes to the low side of the reference ladder of the ADC. This voltage should force V REF− S to be in the range of 1.7V to 2.8V. 1V REF− S Analog output used to sense the voltage at the bottom of the ADC reference ladder.

9 CLK

Converter digital clock input. VIN is sampled on the falling edge of CLK input. 8P D Power Down input. When this pin is high, the converter is in the Power Down mode and the data output pins are in a high impedance state. 26 OE Output Enable pin. When this pin and the PD pin are low, the output data pins are active. When this pin or the PD pin is high, the data output pins are in a high impedance state. thru and thru D0–D9 Digital Output pins providing the 10-bit conversion results. D0 is the LSB, D9 is the MSB. Data is acquired on the falling edge of the CLK input and valid data is present 2.0 clock cycles plus t OD later. 3, 7, 28 VA Positive analog supply pins. These pins should be connected to a clean, quiet voltage source of +5V. V A and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 5, 10 V D Positive digital supply pins. These pins should be connected to a clean, quiet voltage source of +5V. V A and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. ADC10030 www.national.com3

Pin Descriptions and Equivalent Circuits(Continued) Pin No. Symbol Equivalent Circuit Description 12, 21 V D I/O Positive supply pins for the digital output drivers. These pins should be connected to a clean, quiet voltage source of +3V to +5V and be separately bypassed with 10 µF to 50 µF capacitors. 4, 27,

29 AGND

The ground return for the analog supply. AGND and DGND should be connected together close to the ADC10030 package. 6, 11 DGND The ground return for the digital supply. AGND and DGND should be connected together close to the ADC10030 package. 13, 20 DGND I/O The ground return of the digital output drivers. ADC10030 www.national.com 4

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (V= V A = VD ) 6.5V Voltage on Any Pin −0.3V to (V A or VD +0.3V) Input Current at Any Pin (Note 3) ±25 mA Package Input Current (Note 3) ±50 mA Package Dissipation at TA = 25˚C See (Note 4) ESD Susceptibility (Note 5) Human Body Model 1500V Machine Model 200V Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C Storage Temperature −65˚C to +150˚C Operating Ratings(Notes 1, 2) Operating Temperature Range −40˚C ≤ TA ≤ +85˚C VA, VD Supply Voltage +4.75V to +5.5V VD I/O Supply Voltage +2.7V to 5.5V VIN Voltage Range 1.7V to (V A−1.2V) VREF + Voltage Range 2.6V to (V A−1.2V) VREF − Voltage Range 1.7V to 2.8V PD, CLK, OE Voltage Range −0.3V to +5.5V Converter Electrical Characteristics C L = 20 pF, fCLK = 27 MHz, RS = 50Ω .Boldface limits apply for TA = TMIN to TMAX :all other limits TA = 25˚C (Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units Static Converter Characteristics INL Integral Non-Linearity ±0.45 ±1.0 LSB(max) DNL Differential-Non-Linearity ±0.40 ±0.95 LSB(max) Resolution with No Missing Codes 10 Bits Zero Scale Offset Error −4 mV Full-Scale Offset Error +3 mV Dynamic Converter Characteristics ENOB Effective Number of Bits fIN = 1.0 MHz 9.6 8.6 Bits fIN = 4.43 MHz 9.4 Bits fIN = 13.5 MHz 9.4 Bits fIN = 4.43 MHz, fCLK = 30 MHz 9.3 Bits fIN = 15.0 MHz, fCLK = 30 MHz 9.1 Bits S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 1.0 MHz 60 53.5 dB fIN = 4.43 MHz 59 dB fIN = 13.5 MHz 58 dB fIN = 4.43 MHz, fCLK = 30 MHz 58 dB fIN = 15.0 MHz, fCLK = 30 MHz 57 dB SNR Signal-to-Noise Ratio fIN = 1.0 MHz 60 dB fIN = 4.43 MHz 59 dB fIN = 13.5 MHz 59 dB fIN = 4.43 MHz, fCLK = 30 MHz 59 dB fIN = 15.0 MHz, fCLK = 30 MHz 58 dB THD Total Harmonic Distortion fIN = 1.0 MHz −72 −61 dB fIN = 4.43 MHz −69 dB fIN = 13.5 MHz −66 dB fIN = 4.43 MHz, fCLK = 30 MHz −64 dB fIN = 15.0 MHz, fCLK = 30 MHz −61 dB SFDR Spurious Free Dynamic Range fIN = 1.0 MHz 73 dB fIN = 4.43 MHz 71 dB fIN = 13.5 MHz 68 dB fIN = 4.43 MHz, fCLK = 30 MHz 66 dB fIN = 15.0 MHz, fCLK = 30 MHz 62 dB Overrange Output Code V IN > VREF + 1023 ADC10030 www.national.com5

Converter Electrical Characteristics(Continued) C L = 20 pF, fCLK = 27 MHz, RS = 50Ω .Boldface limits apply for TA = TMIN to TMAX :all other limits TA = 25˚C (Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units Dynamic Converter Characteristics Underrange Output Code V IN < VREF − BW Full Power Bandwidth 150 MHz PSRR Power Supply Rejection Ratio Change in Full Scale with 4.5V to 5.5V Supply Change 56 dB Reference, DC, and Logic Electrical Characteristics The following specifications apply for VA = +5.0VDC ,V D = +5.0VDC ,V D I/O= +5.0VDC ,V REF + = +3.5VDC ,V REF − = +1.75VDC ,C L = 20 pF, fCLK = 27 MHz, RS = 50Ω .Boldface limits apply for TA = TMIN to TMAX :all other limits TA = 25˚C (Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units Reference and Analog Input Characteristics VIN Analog Input Range 1.75 3.5 1.6 3.8 V(min) V(max) C IN Analog VIN Input Capacitance 5p F IIN Input Leakage Current 10 µA R REF Reference Ladder Resistance 1000 850 1150 Ω (min) Ω (max) VREF + Positive Reference Voltage 3.5 3.8 V(max) VREF − Negative Reference Voltage 1.75 1.6 V(min) (VREF +) − (VREF −) Total Reference Voltage 1.75 1.0 2.2 V(min) V(max) CLK, OE, PD, Digital Input Characteristics VIH Logical “1” Input Voltage VD = 5.5V 2.0 V(min) VIL Logical “0” Input Voltage VD = 4.5V 1.0 V(max) IIH Logical “1” Input Current VIH = VD 10 µA IIL Logical “0” Input Current VIL = DGND −10 µA DB0–DB9 Digital Output Characteristics VOH Logical “1” Output VoltageVD I/O= +4.5V, IOUT = −0.5 mA VD I/O= +2.7V, IOUT = −0.5 mA 4.0 2.4 V(min) V(min) VOL Logical “0” Output VoltageVD I/O= +4.5V, IOUT = −1.6 mA VD I/O= +2.7V, IOUT = −1.6 mA 0.4 0.4 V(max) V(max) IOZ TRI-STATE Output Current VOUT = DGND VOUT = VD −10 µA µA IOS Output Short Circuit Current VD I/O= 3V ±12 mA VD I/O= 5V ±25 mA Power Supply Characteristics IA Analog Supply Current PD = LOW, Ladder Current not included PD = HIGH, Ladder Current not included 17.6 0.5 mA(max) mA I D + ID I/O Digital Supply Current PD = LOW, Ladder Current not included PD = HIGH, Ladder Current not included 6.6 0.2 mA(max) mA ADC10030 www.national.com 6

Reference, DC, and Logic Electrical Characteristics(Continued) The following specifications apply for VA = +5.0VDC ,V D = +5.0VDC ,V D I/O= +5.0VDC ,V REF + = +3.5VDC ,V REF − = +1.75VDC ,C L = 20 pF, fCLK = 27 MHz, RS = 50Ω .Boldface limits apply for TA = TMIN to TMAX :all other limits TA = 25˚C (Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units Power Supply Characteristics PD Power Consumption PD = LOW 121 130 mW(max) PD = HIGH 3.5 PD = LOW, f CLK = 30 MHz 125 mW The following specifications apply for VA = +5.0VDC ,V D = +5.0VDC ,V D I/O= 5.0VDC ,V REF + = +3.5VDC ,V REF − = +1.75VDC ,C L = 20 pF, fCLK = 27 MHz, RS = 50Ω .Boldface limits apply for TA = TMIN to TMAX :all other limits TA = 25˚C (Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) fCLK1 Maximum Clock Frequency 27 30 MHz fCLK2 Minimum Clock Frequency 1 MHz tCH Clock High Time 16.5 ns(min) tCL Clock Low Time 16.5 ns(min) Duty Cycle 50 45 % (min) % (max) Pipeliine Delay (Latency) 2.0 Clock Cycles trc,tfc Clock Input Rise and Fall Time 4 ns(max) tr,tf Output Rise and Fall Times 10 ns tOD Fall of CLK to Data Valid 20 25 ns(max) tOH Output Data Hold Time 12 ns tDIS Rising Edge of OE to TRI-STATE From Output High, 2k Ω to Ground 25 ns From Output Low, 2 kΩ to VD I/O 18 ns tEN Falling Edge of OE to Valid Data 1k Ω to VCC 25 ns tVALID Data Valid Time 27 ns tAJ Aperture Jitter <30 ps Full Scale Step Response t r = 10 ns 1 conversion Overrange Recovery Time VIN Step from (VREF + +100 mV) to (VREF −) 1 conversion tWU PD Low to1⁄2 LSB Accurate Conversion (Wake-Up Time) 700 ns Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func- tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.The guaranteed speci- fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2:All voltages are measured with respect to GND= AGND = DGND = 0V, unless otherwise specified. Note 3:When the input voltage at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD ), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4:The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PD M A X=( TJmax − TA)/θJA. In the 32-pin TQFP, θJA is 69˚C/W, so PD MAX = 1,811 mW at 25˚C and 942 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this device under normal operation will typically be about 137 mW (125 mW quiescent power+2m W reference ladder power +10 mW due to 1 TTL load on each digital output). The values for maximum power dissipation listed above will be reached only when the ADC10030 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5:Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZEROΩ . Note 6:See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 300 mV beyond the supply rails will not damage this device. However, errors in the A/D conversion can occur if the input goes above VA or below AGND by more than 300 mV. ADC10030 www.national.com7

Note 8:Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Note 9:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10:When the input signal is between VREF + and (VA + 300 mV), the output code will be 3FFh, or all 1s. When the input signal is between −300 mV and VREF −, the output code will be 000h, or all 0s. Typical Performance CharacteristicsVA = VD = VD I/O= 5V, TA = 25˚C, fIN = 4.4 MHz, fCLK = 27 MHz, unless otherwise specified. DS101064-11 DS101064-12 DS101064-24 Typical INL DS101064-41 INL vs fCLK DS101064-42 INL vs VA DS101064-43 INL vs Clock Duty Cycle DS101064-44 Typical DNL DS101064-45 DNL vs fCLK DS101064-46 ADC10030 www.national.com 8

Typical Performance CharacteristicsVA = VD = VD I/O= 5V, TA = 25˚C, fIN = 4.4 MHz, fCLK = 27 MHz, unless otherwise specified.. (Continued) Specification Definitions APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. APERTURE DELAY See Sampling Delay. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise plus Distortion Ratio (S/N+D or SINAD). ENOB is defined as (SI- NAD −1.76) / 6.02. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its 1 MHz value for a full scale input. The test is per- formed with f IN equal to 100 kHz plus integral multiples of fCLK . The input frequency at which the output is −3 dB rela- tive to the 1 MHz input signal is the full power bandwidth. FULL SCALE (FS) INPUT RANGE of the ADC is the input range of voltages over which the ADC will digitize that input. For V REF + = 3.5V and VREF − = 1.5V, FS = (VREF +) − (VREF −) = 2.0V. FULL SCALE OFFSET ERROR is a measure of how far the last code transition is from the ideal 11⁄2 LSB below VREF + and is defined as V1023 +1.5 LSB − VREF +, where V1023 is the voltage at which the transition from code 1022 to 1023 occurs. INTEGRAL NON-LINEARITY (INL) is a measure of the de- viation of each individual code from a line drawn from nega- tive full scale ( 1⁄2 LSB below the first code transition) through DNL vs VA DS101064-47 DNL vs Clock Duty Cycle DS101064-48 SINAD & ENOB vs Temperature and fIN DS101064-49 SINAD & ENOB vs V A DS101064-50 IA +ID vs Temparature DS101064-52 Spectral Response at 27 MSPS DS101064-53 Spectral Response at 30 MSPS DS101064-54 Dynamics at 27 MSPS DS101064-55 Dynamics at 30 MSPS DS101064-56 ADC10030 www.national.com9

positive full scale (11⁄2 LSB above the last code transition). measured from the center of that code value. clock before the data update is present at the output pins. data is valid after the fall of the input clock. change in Full Scale Error, expressed in dB. amount of time after the fall of the clock input. not including harmonics or dc. ponents, to the RMS value of the input signal. FIGURE 1. ADC10030 Timing Diagram

REF + S will cause the output word to consist of all ones. 1.0V more positive than VREF −S . when the OE pin or the PD pin is high.

1.0 THE ANALOG INPUT

rails, even momentarily, as during power-up. input circuitry to maintain highest noise performance.

2.0 REFERENCE INPUTS

Note:Throughout this data sheet reference is made to VREF + and to VREF −. REF + S and VREF − S, respectively. VREF − to be somewhat variable. high reference variability and thermal drift. the reference ladder itself. FIGURE 2. AC Test Circuit FIGURE 3. tEN ,tDIS Test Circuit

FIGURE 4. Simple, Low Component Count Reference Biasing

LMC6081 and LMC6082, should be used for this application. is at its minimum value of 850Ω . minimum of 1.0V and a maximum of 2.2V. FIGURE 5. Improved Low Component Count Reference Biasing

3.0 POWER SUPPLY CONSIDERATIONS

same supply used for the ADC10030 analog supply. ply rejection. A clean analog power source should be used.

4.0 THE ADC10030 CLOCK

5.0 LAYOUT AND GROUNDING

and free of noise from other parts of the system. clean point in the analog ground return. FIGURE 6. Setting Precision Reference Voltages

6.0 DYNAMIC PERFORMANCE

7.0 COMMON APPLICATION PITFALLS

from supplies outside the range of the ADC10030 supply. Attempting to drive a high capacitance digital data bus. REF + F pin and sink sufficient current from the VREF − F pin. verter output will exhibit excessive noise. gates with RC timing is generally inadequate. source used by VA, but should be decoupled from VA. FIGURE 8. Isolating the ADC Clock

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 32-Lead TQFP Package ADC10030 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.