ADC1002S020HL | DigiCamel IC Datasheet

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Single 10 bits ADC, up to 20 MHz Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC1002S020 is a 10-bit high-speed Analog-to-Digital Converter (ADC) for professional video and other applications. It converts with 3.0 V to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows a reduction of the device power consumption to 4 mW. 2. Features  10-bit resolution  3 .0 V to 5.25 V operation  Sa mpling rate up to 20 MHz  DC sampling allowed  High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz; full-scale input at fclk = 20 MHz)  In-R ange (IR) CMOS output  CMOS/T ransistor-Transistor Logic (TTL) compatible digital inputs and outputs  Exte rnal reference voltage regulator  Power dissip ation only 53 mW (typical value)  L ow analog input capacitance, no buffer amplifier required  S tandby mode  No samp le-and-hold circuit required 3. Applications  Video data digitizing  Came ra  Camcorder  Rad io communication  Bar code scanner

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 3 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz 6. Block diagram VSSD2 Rlad RB RM RT VI VDDD2 VDDA 27 D4 23 D1 22 D0 IN - RANGE LATCH CMOS OUTPUTSLATCHES CLOCK DRIVER 014aaa482 CLK OE STDBY ADC1002S020

20 VDDO

analog ground digital ground 2 digital ground 1 VSSD1 VSSO output ground analog voltage input data outputs LSB MSB VDDD1 IR output ANALOG - TO - DIGITAL CONVERTER CMOS OUTPUT Fig 1. Block diagram

7.1 Pinning

7.2 Pin description

Table 3. Pin description

ADC1002S020_3 © IDT 2012. All rights reserved. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). the supply voltage VDD remains as indicated. Table 5. Thermal characteristics Table 3. Pin description …continued

ADC1002S020_3 © IDT 2012. All rights reserved. resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. parallel and fed with the same reference source, the matching between each of them is optimized. wave signal) in order to sample the signal and obtain correct output data. SIgnal-to-Noise And Distortion (SINAD) ratio: SINAD = ENOB  6.02 + 1.76 dB. [6] Output data acquisition: the output data is available af ter the maximum delay time of td(o).

Additional information relating to Table 6

Table 7. Mode selection Table 8. Standby selection Table 9. Output coding and input voltage (typical values; referenced to V SSA)

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 10 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz sample N + 1sample N CLK 014aaa481 sample N + 2 sample N + 1sample N sample N + 2 50% VI DATA D0 to D9 VDDO 0 V 50%DATA N + 1 DATA N DATA N − 1 DATA N − 2 td(o) tw(clk)H tw(clk)L td(s) th(o) Fig 4. Timing diagram

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 11 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz LOW HIGH HIGH LOW ADC1002S020 VDDD VDDO OE OE output data output data 10 % 50 % 50 % 90 % 50 % tdLZ tdZL tdHZ tdZH 20 pF 3.3 kΩ S1TEST VDDOtdLZ VDDOtdZL VSSOtdZH tdHZ VSSO 014aaa484 frequency on pin OE= 100 kHz. Fig 5. Timing diagram and test condit ions of 3-state output delay time 014aaa491 −0.2 0.2 0.6 A (LSB) −0.6 f (MHZ) 0 1200800400200 1000600 1023 Fig 6. Typical Integral Non-Linearity (INL) performance

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 12 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz 014aaa492 −0.05 0.05 −0.15 0.15 0.25 A (LSB) −0.25 f (MHZ) 0 1200800400200 1000600 1023 Fig 7. Typical Differential Non-Linearity (DNL) performance 014aaa479 code 1023 code 0 50 % 50 %CLK VI ts(LH) ts(HL) 50 % 50 % 5 ns 5 ns 2 ns 2 ns Fig 8. Analog input settling time diagram

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 13 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz 014aaa493 −80 −40 A (dB) −120 f (MHz) 0 107.512.5 5.01 Effective bits: 9.59; THD = 76.60 dB. Fig 9. Typical fast Fourier transform (f clk = 20 MHz; fi = 1 MHz)

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 14 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz 014aaa485 VDDO D9 to D0 IR VSSO VDDA VI VSSA 014aaa486 Fig 10. D9 to D0 and IR outputs Fig 11. VI analog input 014aaa487 VDDO VSSO OE STDBY VDDA RT RM RB VSSA 014aaa488 Rlad Rlad Rlad Rlad Fig 12. OE and STDBY inputs Fig 13. RB, RM and RT inputs VDDD CLK 1/2 VDDD VSSD 014aaa489 Fig 14. CLK input

12.1 Application diagram

n.c.(2) VSSA VSSAVSSAVSSA RB(1) RT(1) OEVI(4)n.c.(2) n.c.(2)RM(1) (3) n.c.(2) n.c.(2) n.c.(2) 10 11 12 13 14 15 16 32 31 100 nF 100 nF 100 nF 30 29 28 27 26 25 D5 D4 D3 D2D8 D7 D6 The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) RB, RM and RT are decoupled to V SSA (2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence (3) When RM is not used, pin 11 can be left open ci rcuit , avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. (4) When the analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14). Fig 15. Application diagram

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 16 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz 13. Package outline 0.2 UNIT A max. A1 A2 A3 bp cE (1) eH E LL p Zy w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 0.5 7.15 6.85 1 0.95 0.55 o o0.12 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT401-1 136E01 MS-026 00-01-19 03-02-20 D(1) (1) (1) 5.1 4.9 H D 7.15 6.85 EZ 0.95 0.55 D bp e E B DH bp EH v M B D ZD A ZE e v M A X 24 17 θ A Lp detail X L (A )3 y w M w M 0 2.5 5 mm scale LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm SOT401-1 c pin 1 index Fig 16. Package outline SOT401-1 (LQFP32)

ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 18 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz 16. Contents 11 Additional informa tion relating to Table 6 . . . 9

Product Information

ADC1002S020HL specifications and overview.

Summary

Single 10 bits ADC, up to 20 MHz

Description

Single 10 bits ADC, up to 20 MHz

Source title ADC1002S020HL Datasheet(PDF) - Integrated Device Technology

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