ADC1001

ADC1001 NSC | Alldatasheet

Document overview

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Technical content

Features

n ADC1001 is pin compatible with ADC0801 series 8-bit A/D converters n Compatible with NSC800 and 8080 µP derivatives — no interfacing logic needed n Easily interfaced to 6800 µP derivatives n Differential analog voltage inputs n Logic inputs and outputs meet both MOS and TTL voltage level specifications n Works with 2.5V (LM336) voltage reference n On-chip clock generator n 0V to 5V analog input voltage range with single 5V supply n Operates ratiometrically or with 5 VDC , 2.5 VDC ,o r analog span adjusted voltage reference n 0.3" standard width 20-pin DIP package Connection Diagram

Ordering Information

0˚C to +70˚C −40˚C to +85˚C Order Number ADC1001CCJ-1 ADC1001CCJ Package Outline J20A J20A TRI-STATE® is a registered trademark of National Semiconductor Corp. ADC1001 Dual-In-Line Package DS005675-11 Top View June 1999 ADC1001 10-Bit µP Compatible A/D Converter © 1999 National Semiconductor Corporation DS005675 www.national.com

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) (Note 3) 6.5V Logic Control Inputs −0.3V to +18V Voltage at Other Inputs and Outputs −0.3V to (V CC +0.3V) Storage Temperature Range −65˚C to +150˚C Package Dissipation at T A =25˚C 875 mW Lead Temp. (Soldering, 10 seconds) 300˚C ESD Susceptibility (Note 10) 800V Operating Conditions(Notes 1, 2) Temperature Range T MIN ≤TA≤TMAX ADC1001CCJ −40˚C ≤TA≤+85˚C ADC1001CCJ-1 0˚C ≤TA≤+70˚C Range of VCC 4.5 VDC to 6.3 VDC Converter Characteristics Converter Specifications:VCC =5V DC ,V REF /2=2.500 VDC ,TMIN ≤TA≤TMAX and fCLK =410 kHz unless otherwise specified. Parameter Conditions MIn Typ Max Units Linearity Error ±1 LSB Zero Error ±2 LSB Full-Scale Error ±2 LSB Total Ladder Resistance (Note 9) Input Resistance at Pin 9 2.2 4.8 K Ω Analog Input Voltage Range (Note 4) V(+) or V(−) GND−0.05 V CC +0.05 V DC DC Common-Mode Error Over Analog Input Voltage Range ±1⁄8 LSB Power Supply Sensitivity V CC =5V DC ±5% Over ±1⁄8 LSB Allowed VIN(+) and VIN(−) Voltage Range (Note 4) Timing Specifications:VCC =5V DC and TA =25˚C unless otherwise specified. Symbol Parameter Conditions MIn Typ Max Units Tc Conversion Time (Note 5) 80 90 1/f CLK fCLK =410 kHz 195 220 µs fCLK Clock Frequency (Note 8) 100 1260 kHz Clock Duty Cycle 40 60 % CR Conversion Rate In Free-Running INTR tied to WR with 4600 conv/s Mode CS =0V DC ,fCLK =410 kHz tW(WR)L Width of WR Input (Start Pulse CS =0V DC (Note 6) 150 ns Width) tACC Access Time (Delay from C L=100 pF 170 300 ns Falling Edge of RD to Output Data Valid) t1H ,t0H TRI-STATE ® Control (Delay C L=10 pF, RL=10k 125 200 ns from Rising Edge of RD to (See TRI-STATE Test Hi-Z State) Circuits) tWI,tRI Delay from Falling Edge 300 450 ns of WR or RD to Reset of INTR t1rs INTR to 1st Read Set-Up Time 550 400 ns C IN Input Capacitance of Logic 5 7.5 pF Control Inputs C OUT TRI-STATE Output 5 7.5 pF Capacitance (Data Buffers) www.national.com 2

The following specifications apply for VCC =5V DC and TMIN ≤TA≤ TMAX , unless otherwise specified. Symbol Parameter Conditions MIn Typ Max Units CONTROL INPUTS [Note: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical “1” Input Voltage V CC =5.25 VDC 2.0 15 V DC (Except CLK IN) VIN (0) Logical “0” Input Voltage V CC =4.75 VDC 0.8 V DC (Except CLK IN) IIN (1) Logical “1” Input Current V IN=5V DC 0.005 1 µA DC (All Inputs) IIN (0) Logical “0” input Current V IN=0V DC −1 −0.005 µA DC (All Inputs) CLOCK IN V T+ CLK IN Positive Going 2.7 3.1 3.5 V DC Threshold Voltage VT− CLK IN Negative Going 1.5 1.8 2.1 V DC Threshold Voltage VH CLK IN Hysteresis 0.6 1.3 2.0 V DC (VT+)−(VT−) OUTPUTS AND INTR VOUT (0) Logical “0” Output Voltage I OUT =1.6 mA, VCC =4.75 VDC 0.4 V DC VOUT (1) Logical “1” Output Voltage I O =−360 µA, VCC =4.75 VDC 2.4 V DC IO =−10 µA, VCC =4.75 VDC 4.5 V DC IOUT TRI-STATE Disabled Output V OUT =0.4 VDC 0.1 −100 µA DC Leakage (All Data Buffers) V OUT =5V DC 0.1 3 µA DC ISOURCE VOUT Short to GND, TA =25˚C 4.5 6 mA DC ISINK VOUT Short to VCC ,TA =25˚C 9.0 16 mA DC POWER SUPPLY ICC Supply Current (Includes f CLK =410 kHz, Ladder Current) V REF /2=NC, TA =25˚C and CS =1 2.5 5.0 mA Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2:All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND. Note 3:A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC . Note 4:For VIN(−)≥ VIN(+) the digital output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near fullscale. The spec al- lows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC t o5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5:With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, seeFigure 3. Note 6:The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams). Note 7:All typical values are for TA =25˚C. Note 8:Accuracy is guaranteed at fCLK =410 kHz. At higher clock frequencies accuracy can degrade. Note 9:The VREF/2 pin is the center point of a two resistor divider (each resistor is 2.4kΩ ) connected from VCC to ground. Total ladder input resistance is the sum of these two equal resistors. Note 10:Human body model, 100 pF discharged through a 1.5 kΩ resistor. www.national.com3

Typical Performance Characteristics TRI-STATE Test Circuits and Waveforms Logic Input Threshold Voltage vs Supply Voltage DS005675-14 Delay From Falling Edge of RD to Output Data Valid vs Load Capacitance DS005675-15 CLK IN Schmitt Trip Levels vs Supply Voltage DS005675-16 Output Current vs Temperature DS005675-17 DS005675-3 t1H ,C L=10 pF DS005675-4 tr=20 ns DS005675-5 t0H ,C L=10 pF DS005675-6 tr=20 ns www.national.com 4

TRI-STATE Test Circuits and Waveforms(Continued) Timing Diagrams DS005675-7 Output Enable and Reset INTR DS005675-8 *All timing is measured from the 50% voltage points. www.national.com5

Note 12:CS shown twice for clarity. Note 13:SAR = Successive Approximation Register. FIGURE 3. www.national.com 8

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Cavity Dual-In-Line Package (J) (Side Brazed) Order Number ADC1001CCJ or ADC1001CCJ-1 ADC1001 10-Bit µP Compatible A/D Converter National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.