ADC0801_1 NSC | Alldatasheet
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Technical content
Features
n Compatible with 8080 µP derivatives — no interfacing logic needed - access time - 135 ns n Easy interface to all microprocessors, or operates “stand alone” n Differential analog voltage inputs n Logic inputs and outputs meet both MOS and TTL voltage level specifications n Works with 2.5V (LM336) voltage reference n On-chip clock generator n 0V to 5V analog input voltage range with single 5V supply n No zero adjust required n 0.3" standard width 20-pin DIP package n 20-pin molded chip carrier or small outline package n Operates ratiometrically or with 5 VDC , 2.5 VDC ,o r analog span adjusted voltage reference Key Specifications n Resolution 8 bits n Total error ±1⁄4 LSB, ±1⁄2 LSB and ±1 LSB n Conversion time 100 µs Connection Diagram
Ordering Information
TEMP RANGE 0˚C TO 70˚C 0˚C TO 70˚C −40˚C TO +85˚C ±1⁄4 Bit Adjusted ADC0801LCN ERROR ±1⁄2 Bit Unadjusted ADC0802LCWM ADC0802LCN ±1⁄2 Bit Adjusted ADC0803LCN ±1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ PACKAGE OUTLINE M20B — Small Outline N20A — Molded DIP Z-80® is a registered trademark of Zilog Corp. ADC080X Dual-In-Line and Small Outline (SO) Packages DS005671-30 See Ordering Information November 1999 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters © 2001 National Semiconductor Corporation DS005671 www.national.com
Error Specification (Includes Full-Scale, Zero Error, and Non-Linearity) Part Full- V REF /2=2.500 VDC VREF /2=No Connection Number Scale (No Adjustments) (No Adjustments) Adjusted ADC0801 ±1⁄4 LSB ADC0802 ±1⁄2 LSB ADC0803 ±1⁄2 LSB ADC0804 ±1 LSB ADC0805 ±1 LSB DS005671-1
8080 Interface
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 2
Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) (Note 3) 6.5V Voltage Logic Control Inputs −0.3V to +18V At Other Input and Outputs −0.3V to (V CC +0.3V) Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260˚C Dual-In-Line Package (ceramic) 300˚C Surface Mount Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C Storage Temperature Range −65˚C to +150˚C Package Dissipation at T A =25˚C 875 mW ESD Susceptibility (Note 10) 800V Operating Ratings(Notes 1, 2) Temperature Range T MIN ≤TA≤TMAX ADC0804LCJ −40˚C ≤TA≤+85˚C ADC0801/02/03/05LCN −40˚C ≤TA≤+85˚C ADC0804LCN 0˚C ≤TA≤+70˚C ADC0802/04LCWM 0˚C ≤TA≤+70˚C Range of VCC 4.5 VDC to 6.3 VDC
Electrical Characteristics
The following specifications apply for VCC =5 VDC ,TMIN ≤TA≤TMAX and fCLK =640 kHz unless otherwise specified. Parameter Conditions Min Typ Max Units ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. ±1⁄4 LSB (See Section 2.5.2) ADC0802: Total Unadjusted Error (Note 8) VREF /2=2.500 VDC ±1⁄2 LSB ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj. ±1⁄2 LSB (See Section 2.5.2) ADC0804: Total Unadjusted Error (Note 8) VREF /2=2.500 VDC ±1 LSB ADC0805: Total Unadjusted Error (Note 8) VREF /2-No Connection ±1 LSB VREF /2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 k Ω ADC0804 (Note 9) 0.75 1.1 k Ω Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 V CC +0.05 V DC DC Common-Mode Error Over Analog Input Voltage ±1/16 ±1⁄8 LSB Range Power Supply Sensitivity V CC =5 VDC ±10% Over ±1/16 ±1⁄8 LSB Allowed VIN(+) and VIN(−) Voltage Range (Note 4) The following specifications apply for VCC =5 VDC and TMIN ≤TA≤TMAX unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TC Conversion Time f CLK =640 kHz (Note 6) 103 114 µs TC Conversion Time (Notes 5, 6) 66 73 1/f CLK fCLK Clock Frequency V CC =5V, (Note 5) 100 640 1460 kHz Clock Duty Cycle 40 60 % CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s Mode CS =0 V DC ,fCLK =640 kHz tW(WR)L Width of WR Input (Start Pulse Width)CS =0 VDC (Note 7) 100 ns tACC Access Time (Delay from Falling C L=100 pF 135 200 ns Edge of RD to Output Data Valid) t1H ,t0H TRI-STATE Control (Delay C L=10 pF, RL=10k 125 200 ns from Rising Edge of RD to (See TRI-STATE Test Hi-Z State) Circuits) tWI,tRI Delay from Falling Edge 300 450 ns of WR or RD to Reset of INTR C IN Input Capacitance of Logic 5 7.5 pF Control Inputs ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com3
The following specifications apply for VCC =5 VDC and TMIN ≤TA≤TMAX unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units C OUT TRI-STATE Output 5 7.5 pF Capacitance (Data Buffers) CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] V IN (1) Logical “1” Input Voltage V CC =5.25 VDC 2.0 15 V DC (Except Pin 4 CLK IN) VIN (0) Logical “0” Input Voltage V CC =4.75 VDC 0.8 V DC (Except Pin 4 CLK IN) IIN (1) Logical “1” Input Current V IN=5 VDC 0.005 1 µA DC (All Inputs) IIN (0) Logical “0” Input Current V IN=0 VDC −1 −0.005 µA DC (All Inputs) CLOCK IN AND CLOCK R V T+ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 V DC Threshold Voltage VT− CLK IN (Pin 4) Negative 1.5 1.8 2.1 V DC Going Threshold Voltage VH CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 V DC (VT+)−(VT−) VOUT (0) Logical “0” CLK R Output I O =360 µA 0.4 V DC Voltage V CC =4.75 VDC VOUT (1) Logical “1” CLK R Output I O =−360 µA 2.4 V DC Voltage V CC =4.75 VDC DATA OUTPUTS AND INTR VOUT (0) Logical “0” Output Voltage Data Outputs I OUT =1.6 mA, VCC =4.75 VDC 0.4 V DC INTR Output IOUT =1.0 mA, VCC =4.75 VDC 0.4 V DC VOUT (1) Logical “1” Output Voltage I O =−360 µA, VCC =4.75 VDC 2.4 V DC VOUT (1) Logical “1” Output Voltage I O =−10 µA, VCC =4.75 VDC 4.5 V DC IOUT TRI-STATE Disabled Output V OUT =0 VDC −3 µA DC Leakage (All Data Buffers) V OUT =5 VDC 3µ A DC ISOURCE VOUT Short to Gnd, TA =25˚C 4.5 6 mA DC ISINK VOUT Short to VCC ,TA =25˚C 9.0 16 mA DC POWER SUPPLY I CC Supply Current (Includes f CLK =640 kHz, Ladder Current) V REF /2=NC, TA =25˚C and CS =5V ADC0801/02/03/04LCJ/05 1.1 1.8 mA ADC0804LCN/LCWM 1.9 2.5 mA Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2:All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd. Note 3:A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC . Note 4:For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC t o5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5:Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. Note 6:With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, seeFigure 4and section 2.0. ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 4
Note 7:The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 9:The VREF /2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ . In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ . Note 10:Human body model, 100 pF discharged through a 1.5 kΩ resistor. Typical Performance Characteristics Logic Input Threshold Voltage vs. Supply Voltage DS005671-38 Delay From Falling Edge of RD to Output Data Valid vs. Load Capacitance DS005671-39 CLK IN Schmitt Trip Levels vs. Supply Voltage DS005671-40 fCLK vs. Clock Capacitor DS005671-41 Full-Scale Error vs Conversion Time DS005671-42 Effect of Unadjusted Offset Error vs. V REF /2 Voltage DS005671-43 Output Current vs Temperature DS005671-44 Power Supply Current vs Temperature(Note 9) DS005671-45 Linearity Error at Low VREF /2 Voltages DS005671-46 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com5
TRI-STATE Test Circuits and Waveforms Timing Diagrams (All timing is measured from the 50% voltage points) t1H DS005671-47 t1H ,C L=10 pF DS005671-48 tr=20 ns t0H DS005671-49 t0H ,C L=10 pF DS005671-50 tr=20 ns DS005671-51 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 6
Timing Diagrams (All timing is measured from the 50% voltage points) (Continued) Typical Applications Output Enable and Reset with INTR DS005671-52 Note: Read strobe must occur 8 clock periods (8/fCLK ) after assertion of interrupt to guarantee reset of INTR .
6800 Interface
Ratiometeric with Full-Scale Adjust DS005671-54 Note: before using caps at VIN or VREF /2, see section 2.3.2 Input Bypass Capacitors. ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com7
Typical Applications(Continued) Absolute with a 2.500V Reference DS005671-55 *For low power, see also LM385–2.5 Absolute with a 5V Reference DS005671-56 Zero-Shift and Span Adjust: 2V≤ VIN ≤ 5V DS005671-57 Span Adjust: 0V≤ VIN ≤ 3V DS005671-58 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 8
Typical Applications(Continued) Directly Converting a Low-Level Signal DS005671-59 VREF /2=256 mV A µP Interfaced Comparator DS005671-60 For: VIN(+)>VIN(−) Output=FFHEX For: V IN(+)<VIN(−) Output=00HEX 1 mV Resolution with µP Controlled Range DS005671-61 VREF /2=128 mV
1 LSB=1 mV
V DAC ≤VIN≤(VDAC +256 mV) 0 ≤ VDAC < 2.5V ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com9
Typical Applications(Continued) Digitizing a Current Flow DS005671-62 Self-Clocking Multiple A/Ds DS005671-63 * Use a large R value to reduce loading at CLK R output. External Clocking DS005671-64 100 kHz≤fCLK ≤1460 kHz ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 10
Typical Applications(Continued) Self-Clocking in Free-Running Mode DS005671-65 *After power-up, a momentary grounding of the WR input is needed to guarantee operation. µP Interface for Free-Running A/D DS005671-66 Operating with “Automotive” Ratiometric Transducers DS005671-67 *VIN(−)=0.15 VCC 15% of VCC ≤VXDR ≤85% of VCC Ratiometric with VREF /2 Forced DS005671-68 µP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis) DS005671-69 *See Figure 5to select R value DB7=“1” for VIN(+)>VIN(−)+(VREF /2) Omit circuitry within the dotted area if hysteresis is not needed ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com11
Typical Applications(Continued) Handling ±10V Analog Inputs DS005671-70 *Beckman Instruments#694-3-R10K resistor array Low-Cost, µP Interfaced, Temperature-to-Digital Converter DS005671-71 µP Interfaced Temperature-to-Digital Converter DS005671-72 *Circuit values shown are for 0˚C≤TA≤+128˚C ***Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage. ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 12
Typical Applications(Continued) Handling ±5V Analog Inputs DS005671-33 *Beckman Instruments#694-3-R10K resistor array Read-Only Interface DS005671-34 µP Interfaced Comparator with Hysteresis DS005671-35 Protecting the Input DS005671-9 Diodes are 1N914 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com13
Typical Applications(Continued) Analog Self-Test for a System DS005671-36 A Low-Cost, 3-Decade Logarithmic Converter DS005671-37 *LM389 transistors A, B, C, D = LM324A quad op amp ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 14
Typical Applications(Continued) 3-Decade Logarithmic A/D Converter DS005671-73 Noise Filtering the Analog Input DS005671-74 fC =20 Hz Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order, low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Multiplexing Differential Inputs DS005671-75 Output Buffers with A/D Data Enabled DS005671-76 *A/D output data is updated 1 CLK period prior to assertion of INTR Increasing Bus Drive and/or Reducing Time on Bus DS005671-77 *Allows output data to set-up at falling edge of CS ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com15
Typical Applications(Continued) Functional Description
1.0 UNDERSTANDING A/D ERROR SPECS
A perfect A/D transfer characteristic (staircase waveform) is shown in Figure 1. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53 mV with 2.5V tied to the V REF /2 pin). The digital output codes that correspond to these inputs are shown as D−1, D, and D+1. For the perfect A/D, not only will center-value (A−1, A, A+1,.... ) analog inputs produce the correct output digital codes, but also each riser (the transitions between adjacent output codes) will be located ±1⁄2 LSB away from each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided for a range of analog input voltages that extend Sampling an AC Input Signal DS005671-78 Note 11:Oversample whenever possible [keep fs> 2f(−60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter. Note 12:Consider the amplitude errors which are introduced within the passband of the filter. 70% Power Savings by Clock Gating DS005671-79 (Complete shutdown takes≈ 30 seconds.) Power Savings by A/D and VREF Shutdown DS005671-80 *Use ADC0801, 02, 03 or 05 for lowest power consumption. Note: Logic inputs can be driven to VCC with A/D supply at zero volts. Buffer prevents data bus from overdriving output of A/D when in shutdown mode. ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 16
2.0 FUNCTIONAL DESCRIPTION
- All of the package pinouts are shown and the major logic
control paths are drawn in heavier weight lines. reset signal for the start F/F. FIGURE 3. Clarifying the Error Specs of an A/D Converter
buffer then supplies the INTR input signal. is not started during this interval). a few propagation delays (approximately 300 ns).
2.1 Digital Control Inputs
pulse at the RD input (pin 2). Note 13:CS shown twice for clarity. Note 14:SAR = Successive Approximation Register. FIGURE 4. Block Diagram
2.2 Analog Differential Voltage Inputs and
differential input (see section 2.4 Reference Voltage).
2.3 Analog Inputs
voltage by the forward voltage of this diode).
2.3.2 Input Bypass Capacitors
2.3.3 Input Source Resistance
FIGURE 5. Analog Input Impedance
back loop — from the output of an op amp, if used.
2.3.4 Noise
sistance and input bypass capacitor in place.
2.4 Reference Voltage
2.4.1 Span Adjust
voltage twice the voltage at pin 9. voltage can be made equal to1⁄2 of the 3V span or 1.5 VDC .
2.4.2 Reference Accuracy Requirements
range parts are also available. FIGURE 6. The VREFERENCE Design on the IC
2.5 Errors and Reference Voltage Adjustments
2.5.1 Zero Error
2.5.2 Full-Scale
2.5.3 Adjusting for an Arbitrary Analog Input Voltage
VMIN =the low end (the offset zero) of the analog range.
2.6 Clocking Option
*Add if VREF /2≤ 1V DC with LM358 to draw 3 mA to ground. FIGURE 7. Adapting the A/D Analog Input Voltages to Match an Arbitrary Input Signal Range
avoided as this will disturb normal converter operation.
2.7 Restart During a Conversion
fore the data of the previous conversion remains in this latch. The INTR output simply remains at the “1” level.
2.8 Continuous Conversions
power-up cycle to guarantee operation.
2.9 Driving the Data Bus
also greatly adds to the stray capacitance of the data bus. using clock extending circuits (6800). with PNP inputs are recommended.
2.10 Power Supplies
2.11 Wiring and Hook-Up Precautions
leads may be necessary in many applications. for measuring the zero error).
3.0 TESTING THE A/D CONVERTER
be used. This provides an LSB value of 20 mV. output code is just changing from1111 1110 to 1111 1111. This value of VREF /2 should then be used for all the tests. and the 4 least significant (LS). counted for in the interpretation of the test results. FIGURE 8. Self-Clocking the A/D
lishing internal limits on the allowed error for each code.
4.0 MICROPROCESSOR INTERFACING
vided separately for each type of microprocessor.
4.1 Interfacing 8080 Microprocessor Derivatives (8048,
FIGURE 9. Basic A/D Tester
Note 16:*Pin numbers for the DP8228 system controller, others are INS8080A. instruction when an interrupt is acknowledged as required by the accompanying sample program. FIGURE 12. ADC0801_INS8080A CPU Interface
Functional Description(Continued) Note 18:The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack. Note 19:All address used were arbitrarily chosen. The standard control bus signals of the 8080 CS, RD and WR) can be directly wired to the digital control inputs of the A/D and the bus timing requirements are met to allow both starting the converter and outputting the data onto the data bus. A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and/or must drive capacitive loads larger than 100 pF.
4.1.1 Sample 8080A CPU Interfacing Circuitry and
The following sample program and associated hardware shown in Figure 12may be used to input data from the converter to the INS8080A CPU chip set (comprised of the INS8080A microprocessor, the INS8228 system controller and the INS8224 clock generator). For simplicity, the A/D is controlled as an I/O device, specifically an 8-bit bi-directional port located at an arbitrarily chosen port address, E0. The TRI-STATE output capability of the A/D eliminates the need for a peripheral interface device, however address decoding is still required to generate the appropriate CS for the con- verter. It is important to note that in systems where the A/D con- verter is 1-of-8 or less I/O mapped devices, no address decoding circuitry is necessary. Each of the 8 address bits (A0 to A7) can be directly used as CS inputs — one for each I/O device.
4.1.2 INS8048 Interface
The INS8048 interface technique with the ADC0801 series (see Figure 13) is simpler than the 8080A CPU interface. There are 24 I/O lines and three test input lines in the 8048. With these extra I/O lines available, one of the I/O lines (bit 0 of port 1) is used as the chip select signal to the A/D, thus eliminating the use of an external address decoder. Bus control signals RD, WR and INT of the 8048 are tied directly to the A/D. The 16 converted data words are stored at on-chip RAM locations from 20 to 2F (Hex). The RD and WR signals are generated by reading from and writing into a dummy address, respectively. A sample interface program is shown below. SAMPLE PROGRAM FOR Figure 12ADC0801–INS8080A CPU INTERFACE DS005671-99 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com27
4.2 Interfacing the Z-80
- General RD and WR strobes are provided and sepa-
Figure 14. Additional I/O advantages exist as software DMA routines FIGURE 13. INS8048 Interface FIGURE 14. Mapping the A/D as an I/O Device
4.3 Interfacing 6800 Microprocessor Derivatives
indicates that the current address is valid. from anywhere in the user’s program. MC6820 or MC6821 Peripheral Interface Adapter, (PIA).
5.0 GENERAL APPLICATIONS
5.1 Multiple ADC0801 Series to MC6800 CPU Interface
Note 20:Numbers in parentheses refer to MC6800 CPU pin out. Note 21:Number or letters in brackets refer to standard M6800 system common bus code. FIGURE 15. ADC0801-MC6800 CPU Interface
Note 22:In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program. FIGURE 16. ADC0801–MC6820 PIA Interface
Functional Description(Continued) The following schematic and sample subroutine (DATA IN) may be used to interface (up to) 8 ADC0801’s directly to the MC6800 CPU. This scheme can easily be extended to allow the interface of more converters. In this configuration the converters are (arbitrarily) located at HEX address 5000 in the MC6800 memory space. To save components, the clock signal is derived from just one RC pair on the first converter. This output drives the other A/Ds. All the converters are started simultaneously with a STORE instruction at HEX address 5000. Note that any other HEX address of the form 5XXX will be decoded by the circuit, pulling all the CS inputs low. This can easily be avoided by using a more definitive address decoding scheme. All the interrupts are ORed together to insure that all A/Ds have completed their conversion before the microprocessor is interrupted. The subroutine, DATA IN, may be called from anywhere in the user’s program. Once called, this routine initializes the CPU, starts all the converters simultaneously and waits for the interrupt signal. Upon receiving the interrupt, it reads the converters (from HEX addresses 5000 through 5007) and stores the data successively at (arbitrarily chosen) HEX addresses 0200 to 0207, before returning to the user’s pro- gram. All CPU registers then recover the original data they had before servicing DATA IN.
5.2 Auto-Zeroed Differential Transducer Amplifier
The differential inputs of the ADC0801 series eliminate the need to perform a differential to single ended conversion for a differential transducer. Thus, one op amp can be elimi- nated since the differential to single ended conversion is provided by the differential input of the ADC0801 series. In general, a transducer preamp is required to take advantage of the full A/D converter input dynamic range. SAMPLE PROGRAM FOR Figure 16ADC0801–MC6820 PIA INTERFACE DS005671-A2 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com31
Note 23:Numbers in parentheses refer to MC6800 CPU pin out. Note 24:Numbers of letters in brackets refer to standard M6800 system common bus code. FIGURE 17. Interfacing Multiple A/Ds in an MC6800 System
and this CMOS package is powered with a stable 5V source. Note 27:Switches are LMC13334 CMOS analog switches. Note 28:The 9 resistors used in the auto-zero section can be±5% tolerance. FIGURE 18. Gain of 100 Differential Transducer Preamp
A flow chart for the zeroing subroutine is shown inFigure 20. buffered with inverting gates. verges to within 5 mV of zero. Figure 21. All addresses used are compatible with the BLC 80/10 microcomputer system.
5.3 Multiple A/D Converters in a Z-80 Interrupt
whose INT is asserted will be read. FIGURE 19. Microprocessor Interface Circuitry for Differential Preamp
FIGURE 20. Flow Chart for Auto-Zero Routine
5.3 Multiple A/D Converters in a Z-80 Interrupt Driven
- It is assumed that the CPU automatically performs a RST 7 instruction when a valid interrupt is acknowledged (CPU is in interrupt mode 1). Hence, the subroutine starting address of X0038.
- The address bus from the Z-80 and the data bus to the Z-80 are assumed to be inverted by bus drivers.
- A/D data and identifying words will be stored in sequen- tial memory locations starting at the arbitrarily chosen address X 3E00.
- The stack pointer must be dimensioned in the main pro- gram as the RST 7 instruction automatically pushes the PC onto the stack and the subroutine uses an additional 6 stack addresses.
- The peripherals of concern are mapped into I/O space with the following port assignments: DS005671-A5 Note 29: All numerical values are hexadecimal representations.
FIGURE 21. Software for Auto-Zeroed Differential A/D
00 MM74C374 8-bit flip-flop
01 A/D 1
02 A/D 2
03 A/D 3
04 A/D 4
05 A/D 5
06 A/D 6
07 A/D 7
FIGURE 22. Multiple A/Ds with Z-80 Type Microprocessor
Functional Description(Continued) DS005671-A6 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com39
Physical Dimensionsinches (millimeters) unless otherwise noted Order Number ADC0802LCWM or ADC0804LCWM Molded Dual-In-Line Package (N) Order Number ADC0801LCN, ADC0802LCN, ADC0803LCN, ADC0804LCN or ADC0805LCN ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com 40
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.