ADC0803LCN

ADC0804LCWMX TI | Alldatasheet

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 8-BitµP CompatibleA/DConverters Check forSamples: ADC0801, ADC0802 ,ADC0803, ADC0804, ADC0805 1FEATURES DESCRIPTION The ADC0801, ADC0802, ADC0803, ADC0804 and• Compatible with8080 µP derivatives– no ADC0805 are CMOS 8-bitsuccessiveapproximationinterfacinglogicneeded – access time135 ns A/D convertersthatuse a differentialpotentiometric• Easy interfacetoallmicroprocessors,or ladder — similarto the 256R products.These operates“stand alone” convertersare designedto allowoperationwiththe NSC800 and INS8080A derivativecontrolbus with• Differentialanalog voltageinputs TRI-STATE outputlatchesdirectlydrivingthe data• Logic inputsand outputsmeet both MOS and bus.These A/Ds appearlikememory locationsorI/OTTL voltagelevelspecifications portstothemicroprocessorand no interfacinglogicis

• Works with2.5V(LM336) voltagereference needed.
• On-chip clockgenerator Differentialanalogvoltageinputsallowincreasingthe
• 0V to5V analog inputvoltagerange with common-mode rejectionand offsettingthe analog single5V supply zero inputvoltagevalue.In addition,the voltage referenceinputcan be adjustedto allowencoding• No zeroadjustrequired any smalleranalogvoltagespan to the full8 bitsof• 0.3"standardwidth20-pinDIP package resolution.
• 20-pinmolded chipcarrieror smalloutline package CONNECTION DIAGRAM
• Operates ratiometricallyor with5 VDC ,2.5VDC , or analog span adjustedvoltagereference ADC080X Dual-In-Lineand Small Outline(SO) Packages See OrderingInformationKEY SPECIFICATIONS
• Resolution:8 Bits
• Totalerror:±1/4LSB, ±1/2LSB and ±1 LSB
• Conversion Time: 100 µs Table1. ORDERING INFORMATION TEMP RANGE 0°C TO 70°C 0°C to70°C −40°C TO +85°C ±1/4BitAdjusted ADC0801LCN ERROR ±1/2BitUnadjusted ADC0802LCWM ADC0802LCN ±1/2BitAdjusted ADC0803LCN ±1BitUnadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ PACKAGE OUTLINE M20B — SmallOutline N20A — Molded DIP Z-80® isa registeredtrademarkofZilogCorp. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. TYPICAL APPLICATIONS

8080 Interface

ERROR SPECIFICATION (IncludesFull-Scale,Zero Error,and Non-Linearity) VREF /2= 2.500VDC VREF /2= No ConnectionFULL-SCALEPART NUMBER ADJUSTED (No Adjustments) (No Adjustments) ADC0801 ±1⁄4 LSB ADC0802 ±1⁄2 LSB ADC0803 ±1⁄2 LSB ADC0804 ±1 LSB ADC0805 ±1 LSB ABSOLUTE MAXIMUM RATINGS IfMilitary/Aerospacespecifieddevicesarerequired,contacttheNationalSemiconductor SalesOffice/Distributorsfor availabilityand specifications. VALUE UNIT Supplyvoltage(VCC )(1) 6.5 V Logiccontrolinputs –0.3to+18 V Voltage Atotherinputand outputs –0.3to(VCC +0.3) V Dual-In-LinePackage (plastic 260 °C Dual-In-LinePackage (ceramic) 300 °CLead Temperature (Soldering,10 seconds) SurfaceMount Package Vapor Phase (60seconds) 215 °C Infrared(15seconds) 220 °C StorageTemperatureRange –65 to+150 °C Package DissipationatTA = 25°C 875 mW ESD Susceptibility(2) 800 V (1) A zenerdiodeexists,internally,fromVCC toGND and has a typicalbreakdown voltageof7 VDC . (2) Human body model,100 pF dischargedthrougha 1.5kΩ resistor.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 OPERATING RATINGS (1)(2) overoperatingfree-airtemperaturerange(unlessotherwisenoted) TemperatureRange TMIN ≤ TA ≤ TMAX ADC0804LCJ –40°C ≤ TA ≤ +85°C ADC0801/02/03/05LCN –40°C ≤ TA ≤ +85°C ADC0804LCN 0°C ≤ TA ≤ +70°C ADC0802/04LCWM 0°C ≤ TA ≤ +70°C Range ofVCC 4.5VDC to6.3VDC (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsdo not applywhen operatingthedevicebeyond itsspecifiedoperatingconditions. (2) Allvoltagesaremeasured withrespecttoGND, unlessotherwisespecified.The separateA GND pointshouldalwaysbe wiredtotheD GND.

ELECTRICAL CHARACTERISTICS

The followingspecificationsapplyforVCC = 5 VDC ,TMIN ≤ TA ≤ TMAX and fCLK = 640 kHz (unlessotherwisespecified). PARAMETER CONDITIONS MIN TYP MAX UNITS ADC0801: TotalAdjustedError(1) WithFull-ScaleAdj.(See Full-Scale) ±1/4 LSB ADC0802: TotalUnadjusted VREF /2=2.500VDC ±1/2 LSBError(1) ADC0803: TotalAdjustedError(1) WithFull-ScaleAdj.(SeeFull-Scale) ±1/2 LSB ADC0804: TotalUnadjusted VREF /2=2.500VDC ±1 LSBError(1) ADC0805: TotalUnadjusted VREF /2-NoConnection ±1 LSBError(1) ADC0801/02/03/05 2.5 8 VREF /2InputResistance(Pin9) kΩ ADC0804 (2) 0.75 1.1 GND –0.0AnalogInputVoltageRange V(+)orV(–)(3) VCC +0.05 VDC5 DC Common-Mode Error Over AnalogInputVoltageRange ±1/16 ±1/8 LSB VCC =5 VDC ±10% Over AllowedVIN(+)and VIN(–)VoltagePower SupplySensitivity ±1/16 ±1/8 LSBRange (3) (1) None oftheseA/Ds requiresa zeroadjust(seeZeroError).To obtainzerocode atotheranaloginputvoltagessee Errorsand ReferenceVoltageAdjustmentsand Figure51. (2) The VREF /2pinisthecenterpointofa two-resistordividerconnectedfromVCC toground.InallversionsoftheADC0801, ADC0802, ADC0803, and ADC0805, and intheADC0804LCJ, each resistoristypically16 kΩ.InallversionsoftheADC0804 exceptthe ADC0804LCJ, each resistoristypically2.2kΩ. (3) ForVIN(−)≥ VIN(+)thedigitaloutputcode willbe 0000 0000.Two on-chipdiodesaretiedtoeach analoginput(seeblockdiagram) whichwillforwardconductforanaloginputvoltagesone diodedropbelowgroundorone diodedropgreaterthantheVCC supply.Be careful,duringtestingatlowVCC levels(4.5V),as highlevelanaloginputs(5V)can cause thisinputdiodetoconduct–especiallyat elevatedtemperatures,and cause errorsforanaloginputsnearfull-scale.The spec allows50 mV forwardbiasofeitherdiode.This means thatas longas theanalogVIN does notexceed thesupplyvoltageby more than50 mV, theoutputcode willbe correct.To achievean absolute0 VDC to5 VDC inputvoltagerangewillthereforerequirea minimum supplyvoltageof4.950VDC overtemperature variations,initialtoleranceand loading. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS The followingspecificationsapplyforVCC =5 VDC and TMIN ≤ TA≤TMAX (unlessotherwisespecified) PARAMETER CONDITIONS MIN TYP MAX UNITS fCLK = 640 kHz (1) 103 114 µs TC ConversionTime See (2)(1) 66 73 1/fCLK ClockFrequency 100 640 1460 kHz fCLK VCC = 5V (2) ClockDutyCycle 40% 60% INTR tiedtoWR withCS = 0 VDC,CR ConversionRate inFree-RunningMode 8770 9708 conv/sfCLK = 640 kHz tW( WR)L WidthofWR Input(StartPulseWidth) CS = 0 VDC (3) 100 ns Access Time (DelayfromFallingEdge ofRDtACC C L = 100 pF 135 200 nstoOutputData Valid) TRI-STATE Control(DelayfromRisingEdge of C L = 10 pF,R L = 10k (See TRI-STATEt1H,t0H 125 200 nsRD toHi-ZState) TEST CIRCUITS AND WAVEFORMS ) DelayfromFallingEdge ofWR orRD toResettWI,tRI 300 450 nsofINTR C IN InputCapacitanceofLogicControlInputs 5 7.5 pF C OUT TRI-STATE OutputCapacitance(DataBuffers) 5 7.5 pF CONTROL INPUTS [Note:CLK IN (Pin4)istheinputofa Schmitttriggercircuitand isthereforespecifiedseparately] VIN (1) Logical“1”InputVoltage(ExceptPin4 CLK IN) VCC = 5.25VDC 2 15 VDC VIN (0) Logical“0”InputVoltage(ExceptPin4 CLK IN) VCC = 4.75VDC 0.8 VDC IIN (1) Logical“1”InputCurrent(AllInputs) VIN = 5 VDC 0.005 1 µADC IIN (0) Logical“0”InputCurrent(AllInputs) VIN = 0 VDC –1 –0.005 µADC CLOCK IN AND CLOCK R CLK IN (Pin4)PositiveGoing ThresholdVT+ 2.7 3.1 3.5 VDCVoltage CLK IN (Pin4)NegativeGoing ThresholdVT− 1.5 1.8 2.1 VDCVoltage VH CLK IN (Pin4)Hysteresis(VT+)–(VT−) 0.6 1.3 2 VDC VOUT (0) Logical“0”CLK R OutputVoltage IO = 360 µA,VCC = 4.75VDC 0.4 VDC VOUT (1) Logical“1”CLK R OutputVoltage IO = −360 µA,VCC = 4.75VDC 2.4 VDC DATA OUTPUTS AND INTR Logical“0”OutputVoltage VOUT (0) Data Outputs IOUT = 1.6mA, VCC = 4.75VDC 0.4 VDC INTR Output IOUT = 1.0mA, VCC = 4.75VDC 0.4 VDC IO = −360 µA,VCC = 4.75VDC 2.4 VDC VOUT (1) Logical“1”OutputVoltage IO = −10 µA,VCC = 4.75VDC 4.5 VDC VOUT = 0 VDC –3 µADCTRI-STATE DisabledOutputLeakage (AllDataIOUT Buffers) VOUT = 5 VDC 3 µADC ISOURCE VOUT ShorttoGND, TA = 2 5°C 4.5 6 mA DC ISINK VOUT ShorttoVCC ,TA = 25°C 9 16 mA DC POWER SUPPLY SupplyCurrent(IncludesLadderCurrent) fCLK = 640 kHz,VREF /2= NC,ICC ADC0801/02/03/04LCJ/05 1.1 1.8 mATA = 25°C and CS = 5 V ADC0804LCN/LCWM 1.9 2.5 mA (1) AccuracyisspecifiedatfCLK = 640 kHz.Athigherclockfrequenciesaccuracycan degrade.Forlowerclockfrequencies,thedutycycle limitscan be extendedso longas theminimum clockhightimeintervalorminimum clocklowtimeintervalisno lessthan275 ns. (2) Withan asynchronousstartpulse,up to8 clockperiodsmay be requiredbeforetheinternalclockphases arepropertostartthe conversionprocess.The startrequestisinternallylatched,see Figure48 and FUNCTIONAL DESCRIPTION . (3) The CS inputisassumed tobrackettheWR strobeinputand thereforetimingisdependenton theWR pulsewidth.An arbitrarilywide pulsewidthwillholdtheconverterina resetmode and thestartofconversionisinitiatedby thelowtohightransitionoftheWR pulse (seeTIMING DIAGRAMS ).

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS spacer Logic InputThresholdVoltagevs Delay From FallingEdge ofRD toOutput Supply Voltage Data Validvs Load Capacitance Figure1. Figure2. CLK IN SchmittTripLevelsvs Supply Voltage fCLK vs Clock Capacitor Figure3. Figure4. Full-ScaleErrorvs EffectofUnadjusted OffsetError Conversion Time VREF /2Voltage Figure5. Figure6. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) spacer Output Current Power Supply Currentvs Temperature Temperature(1) Figure7. Figure8. LinearityErroratLow VREF /2Voltages Figure9. (1) The VREF /2pinisthecenterpointofa two-resistordividerconnectedfromVCC toground.InallversionsoftheADC0801, ADC0802, ADC0803, and ADC0805, and intheADC0804LCJ, each resistoristypically16 kΩ.InallversionsoftheADC0804 exceptthe ADC0804LCJ, each resistoristypically2.2kΩ.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 TRI-STATE TEST CIRCUITS AND WAVEFORMS SPACER SPACER TIMING DIAGRAMS Alltimingismeasured fromthe50% voltagepoints Note: Read strobemust occur8 clockperiods(8/fCLK )afterassertionofinterrupttospecifyresetofINTR. Figure10. Ouatput Enable and Reset withINTR Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS *Forlowpower,see alsoLM385 –2.5 Figure11.6800 Interface Figure12.Absolutewitha 2.500VReference Note:beforeusingcaps atVIN orVREF /2,see sectionInputBypass Capacitors. Figure13.RatiometericwithFull-ScaleAdjust Figure14.Absolutewitha 5V Reference Figure15. Zero-Shiftand Span Adjust:2V ≤ VIN ≤ 5V

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 TYPICAL APPLICATIONS (continued) Figure16. Span Adjust:0V ≤ VIN ≤ 3V VREF /2= 256 mV Figure17. DirectlyConvertinga Low-Level Signal For:VIN(+)>VIN(−);Output= FFHEX For:VIN(+)< VIN(−);Output= 00HEX Figure18. A µP InterfacedComparator Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS (continued) VREF /2=128mV; 1 LSB =1 mV; VDAC ≤ VIN ≤ (VDAC + 256 mV); 0 ≤ VDAC < 2.5V Figure19. 1 mV ResolutionwithµP ControlledRange Figure20. Digitizinga CurrentFlow *Use a largeR valuetoreduceloadingatCLK R output. Figure21. Self-ClockingMultipleA/Ds

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J ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 TYPICAL APPLICATIONS (continued) *Afterpower-up,a momentary groundingoftheWR inputisneeded to ensureoperation. Figure22.Self-ClockinginFree-RunningMode Figure23.µP InterfaceforFree-RunningA/D 100 kHz ≤ fCLK ≤ 1460 kHz *VIN(−)= 0.15VCC 15% ofVCC ≤ VXDR ≤ 85% ofVCC Figure24.Externalclocking Figure25.Operatingwith“Automotive” Ratiometric Transducers Figure26. RatiometricwithVREF /2Forced Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS (continued) *See Figure48 toselectR valueDB7 = “1”forVIN(+)>VIN(−)+(VREF /2).Omit circuitrywithinthedottedareaif hysteresisisnotneeded. Figure27. µP Compatible Differential-InputComparator withPre-SetVOS (withor withoutHysteresis) *Beckman Instruments#694-3-R10Kresistorarray Figure28.Handling±10V Analog Inputs Figure29.Low-Cost,µP Interfaced,Temperature-to-Digital Converter *Circuitvaluesshown arefor0°C ≤ TA ≤ +128°C **Cancalibrateeach sensortoalloweasy replacement,thenA/D can be calibratedwitha pre-setinputvoltage. Figure30. µP InterfacedTemperature-to-DigitalConverter

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 TYPICAL APPLICATIONS (continued) *Beckman Instruments#694-3-R10Kresistorarray Figure31. Handling±5V Analog Inputs Figure32.Read-Only Interface Figure33.µP InterfacedComparator withHysteresis Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS (continued) Diodesare1N914 Figure34.ProtectingtheInput Figure35.Analog Self-Testfora System *LM389 transistorsA,B,C, D = LM324A quad op amp Figure36. A Low-Cost,3-Decade LogarithmicConverter

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 TYPICAL APPLICATIONS (continued) fC =20 Hz Uses Chebyshev implementationforsteeperroll-offunity-gain,2nd order,low-passfilter Addinga separatefilterforeach channelincreasessystemresponsetimeifan analogmultiplexerisused Figure37. 3-Decade LogarithmicA/D Converter *A/Doutputdataisupdated1 CLK periodpriortoassertionofINTR Figure38.Noise FilteringtheAnalog Input Figure39.Output BufferswithA/D Data Enabled *Allowsoutputdatatoset-upatfallingedge ofCS Figure40.MultiplexingDifferentialInputs Figure41.IncreasingBus Driveand/or Reducing Time on Bus Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS (continued) (1) Oversample whenever possible[keepfs> 2f(−60)]toeliminateinputfrequencyfolding(aliasing)and toallowforthe skirtresponseofthefilter. (2) Considertheamplitudeerrorswhichareintroducedwithinthepassband ofthefilter. Figure42. Sampling an AC InputSignal (Completeshutdowntakes≈ 30 seconds.) Figure43. 70% Power Savings by Clock Gating *Use ADC0801, 02,03 or05 forlowestpower consumption. Note:Logicinputscan be driventoVCC withA/D supplyatzerovolts. Bufferpreventsdatabus fromoverdrivingoutputofA/D when inshutdownmode. Figure44. Power Savings by A/D and VREF Shutdown

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 FUNCTIONAL DESCRIPTION UnderstandingA/D ErrorSpecs A perfectA/D transfercharacteristic(staircasewaveform)isshown inFigure45.The horizontalscaleisanalog inputvoltageand theparticularpointslabeledareinstepsof1 LSB (19.53mV with2.5V tiedtotheVREF/2 pin). The digitaloutputcodes thatcorrespondtotheseinputsareshown as D −1,D, and D+1. For theperfectA/D,not onlywillcenter-value(A−1,A,A+1, ....)analoginputsproducethecor-rectoutputdigitalcodes,butalsoeach riser(thetransitionsbetween adjacentoutputcodes)willbe located±1⁄2 LSB away from each center-value.As shown, therisersareidealand have no width.Correctdigitaloutputcodes willbe providedfora rangeofanalog inputvoltagesthatextend±1⁄2 LSB fromtheidealcenter-values.Each tread(therangeofanaloginputvoltage thatprovidesthesame digitaloutputcode)istherefore1 LSB wide. Figure46 shows a worstcase errorplotfortheADC0801. Allcenter-valuedinputsareguaranteedtoproducethe correctoutputcodes and theadjacentrisersare specifiedtobe no closertothecenter-valuepointsthan±1/4 LSB. Inotherwords,ifwe applyan analoginputequaltothecenter-value±1/4LSB, we guaranteethattheA/D willproducethecorrectdigitalcode.The maximum rangeofthepositionofthecode transitionisindicatedby the horizontalarrowand itisspecifiedtobe no more than1/2LSB. The errorcurveofFigure47 shows a worstcase errorplotfortheADC0802. Here we guaranteethatifwe apply an analoginputequaltotheLSB analogvoltagecenter-valuetheA/D willproducethecorrectdigitalcode. Next to each transferfunctionisshown the correspondingerrorplot.Many peoplemay be more familiarwith errorplotsthantransferfunctions.The analoginputvoltagetotheA/D isprovidedby eithera linearramp orby thediscreteoutputstepsofa highresolutionDAC. Noticethattheerroriscontinuouslydisplayedand includes thequantizationuncertaintyoftheA/D.For example theerroratpoint1 ofFigure45 is+1⁄2 LSB because the digitalcode appeared 1⁄2 LSB in advance of the center-valueof the tread.The errorplotsalways have a constantnegativeslopeand theabruptup-sidestepsarealways1 LSB inmagnitude. Figure45.ClarifyingtheErrorSpecs ofan A/D ConverterAccuracy=±0 LSB: A PerfectA/D Figure46.ClarifyingtheErrorSpecs ofan A/D ConverterAccuracy =±1⁄4 LSB Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com Figure47.ClarifyingtheErrorSpecs ofan A/D ConverterAccuracy = ±1⁄2 LSB FunctionalDescription The ADC0801 seriescontainsa circuitequivalentof the 256R network.Analog switchesare sequenced by successiveapproximationlogictomatch theanalogdifferenceinputvoltage[VIN(+)− VIN(−)]toa corresponding tapon theR network.The most significantbitistestedfirstand after8 comparisons(64clockcycles)a digital8- bitbinarycode (11111111 = full-scale)istransferredtoan outputlatchand thenan interruptisasserted(INTR makes a high-to-lowtransition).A conversioninprocesscan be interruptedby issuinga second startcommand. The devicemay be operatedin the free-runningmode by connectingINTR to the WR inputwithCS=0. To ensurestart-upunderallpossibleconditions,an externalWR pulseisrequiredduringthefirstpower-upcycle. On thehigh-to-lowtransitionoftheWR inputtheinternalSAR latchesand theshiftregisterstagesarereset.As longas theCS inputand WR inputremainlow,theA/D willremainina resetstate.Conversionwillstartfrom1 to8 clockperiodsafteratleastone oftheseinputsmakes a low-to-hightransition. A functionaldiagramoftheA/D converterisshown inFigure48.Allofthepackage pinoutsare shown and the majorlogiccontrolpathsaredrawn inheavierweightlines. The converterisstartedby havingCS and WR simultaneouslylow.Thissetsthe startflip-flop(F/F)and the resulting“1” levelresetsthe 8-bitshiftregister,resetsthe Interrupt(INTR)F/F and inputsa “1” to the D flop, F/F1,which isat the inputend of the 8-bitshiftregister.Internalclocksignalsthen transferthis“1” to the Q outputofF/F1.The AND gate,G1, combines this“1” outputwitha clocksignaltoprovidea resetsignaltothe startF/F.Ifthesetsignalisno longerpresent(eitherWR orCS isa “1”)thestartF/F isresetand the8-bitshift registerthencan have the“1” clockedin,which startstheconversionprocess.Ifthesetsignalwere tostillbe present,thisresetpulsewould have no effect(bothoutputsofthestartF/F would momentarilybe ata “1”level) and the8-bitshiftregisterwould continuetobe heldintheresetmode. Thislogicthereforeallowsforwide CS and WR signalsand theconverterwillstartafteratleastone ofthesesignalsreturnshighand theinternalclocks againprovidea resetsignalforthestartF/F.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 (1) CS shown twiceforclarity. (2) SAR = SuccessiveApproximationRegister. Figure48. Block Diagram Afterthe“1”isclockedthroughthe8-bitshiftregister(whichcompletestheSAR search)itappearsas theinput totheD-typelatch,LATCH 1.As soon as this“1”isoutputfromtheshiftregister,theAND gate,G2, causes the new digitalword totransfertotheTRI-STATE outputlatches.When LATCH 1 issubsequentlyenabled,theQ outputmakes a high-to-lowtransitionwhich causes the INTR F/F to set.An invertingbufferthen suppliesthe INTR inputsignal. Note thatthisSET controloftheINTR F/F remainslow for8 oftheexternalclockperiods(astheinternalclocks run at1/8ofthefrequencyoftheexternalclock).Ifthedataoutputiscontinuouslyenabled(CS and RD both heldlow),theINTR outputwillstillsignaltheend ofconversion(bya high-to-lowtransition),because theSET inputcan controltheQ outputoftheINTR F/F even thoughtheRESET inputisconstantlyata M "1M " levelin thisoperatingmode. ThisINTR outputwillthereforestaylow forthe durationof the SET signal,which is8 periodsoftheexternalclockfrequency(assumingtheA/D isnotstartedduringthisinterval). When operatinginthefree-runningorcontinuousconversionmode (INTR pintiedtoWR and CS wiredlow– see ContinuousConversions),theSTART F/F isSET by thehigh-to-lowtransitionoftheINTR signal.Thisresetsthe SHIFT REGISTER whichcauses theinputtotheD-typelatch,LATCH 1,togo low.As thelatchenableinputis stillpresent,theQ outputwillgo high,whichthenallowstheINTR F/F tobe RESET. Thisreducesthewidthof theresultingINTR outputpulsetoonlya few propagationdelays(approximately300 ns). When dataistobe read,thecombinationofbothCS and RD beinglow willcause theINTR F/F tobe resetand theTRI-STATE outputlatcheswillbe enabledtoprovidethe8-bitdigitaloutputs. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com DigitalControlInputs The digitalcontrolinputs(CS, RD, and WR) meet standardT2L logicvoltagelevels.These signalshave been renamed when compared tothestandardA/D Startand OutputEnablelabels.Inaddition,theseinputsareactive low toallowan easy interfacetomicroprocessorcontrolbusses.For non-microprocessorbased applications,the CS input(pin1)can be groundedand thestandardA/D Startfunctionisobtainedby an activelow pulseapplied attheWR input(pin3)and theOutputEnablefunctioniscaused by an activelowpullattheRD input(pin2). Analog DifferentialVoltageInputsand Common-Mode Rejection ThisA/D has additionalapplicationsflexibilitydue totheanalogdifferentialvoltageinput.The VIN(−)input(pin7) can be used toautomaticallysubtracta fixedvoltagevaluefromtheinputreading(tarecorrection).Thisisalso usefulin4 mA –20 mA currentloopconversion.Inaddition,common-mode noisecan be reducedby use ofthe differentialinput. The timeintervalbetween samplingVIN(+)and VIN(−)is4-1/2clockperiods.The maximum errorvoltagedue to thisslighttimedifferencebetween theinputvoltagesamplesisgivenby: (1) Where: ∆Ve istheerrorvoltagedue tosamplingdelay VP isthepeak valueofthecommon-mode voltage fcm isthecommon-mode frequency As an example,tokeep thiserrorto1/4LSB (∼5 mV) when operatingwitha 60 Hz common-mode frequency, fcm ,and usinga 640 kHz A/D clock,fCLK ,would allowa peak valueofthecommon-mode voltage,VP,which is givenby: (2) or (3) whichgivesVP–1.9V. The allowedrangeofanaloginputvoltagesusuallyplacesmore severerestrictionson inputcommon-mode noise levels. An analoginputvoltagewitha reducedspan and a relativelylargezerooffsetcan be handledeasilyby making use ofthedifferentialinput(seeReferenceVoltage). Analog Inputs— InputCurrent Normal Mode Due totheinternalswitchingaction,displacementcurrentswillflowattheanaloginputs.Thisisdue toon-chip straycapacitancetogroundas shown inFigure49.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 rON ofSW 1 and SW 2 .5 kΩ r=rON C STRAY × 5 kΩ x 12 pF = 60 ns Figure49. Analog InputImpedance The voltageon thiscapacitanceisswitchedand willresultincurrentsenteringtheVIN(+)inputpinand leaving theVIN(−) inputwhich willdepend on theanalogdifferentialinputvoltagelevels.These currenttransientsoccur attheleadingedge oftheinternalclocks.They rapidlydecay and do notcause errorsas theon-chipcomparator isstrobedattheend oftheclockperiod. FaultMode IfthevoltagesourceappliedtotheVIN(+)orVIN(−)pinexceedstheallowedoperatingrangeofVCC +50 mV, large inputcurrentscan flowthrougha parasiticdiodeto the VCC pin.Ifthesecurrentscan exceed the 1 mA max allowedspec,an externaldiode(1N914)shouldbe added tobypass thiscurrenttotheVCC pin(withthecurrent bypassed withthisdiode,thevoltageattheVIN(+)pincan exceed theVCC voltageby theforwardvoltageofthis diode). InputBypass Capacitors Bypass capacitorsattheinputswillaveragethesechargesand cause a DC currenttoflowthroughtheoutput resistancesoftheanalogsignalsources.Thischargepumping actionisworse forcontinuousconversionswith theVIN(+)inputvoltageatfull-scale.For continuousconversionswitha 640 kHz clockfrequencywiththeVIN(+) inputat5V, thisDC currentisata maximum ofapproximately5 µA. Therefore,bypass capacitorsshouldnotbe used attheanaloginputsor theVREF /2pinforhighresistancesources(> 1 kΩ).Ifinputbypass capacitorsare necessaryfornoisefilteringand highsourceresistanceisdesirabletominimizecapacitorsize,thedetrimental effectsofthevoltagedrop acrossthisinputresistance,which isdue totheaveragevalueoftheinputcurrent, can be eliminatedwitha full-scaleadjustmentwhilethegivensourceresistorand inputbypasscapacitorareboth in place.This ispossiblebecause the average valueof the inputcurrentisa preciselinearfunctionof the differentialinputvoltage. InputSource Resistance Largevaluesofsourceresistancewhere an inputbypass capacitorisnotused,willnotcause errorsas theinput currentssettleoutpriortothecomparisontime.Ifa low pass filterisrequiredinthesystem,use a low valued seriesresistor(≤ 1 kΩ) fora passiveRC sectionor add an op amp RC activelow pass filter.For low source resistanceapplications,(≤ 1 kΩ),a 0.1μF bypass capacitorattheinputswillpreventnoisepickupdue toseries leadinductanceofa longwire.A 100Ω seriesresistorcan be used toisolatethiscapacitor— boththeR and C areplacedoutsidethefeedbackloop— fromtheoutputofan op amp, ifused. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com Noise The leadsto the analog inputs(pins6 and 7) shouldbe kept as shortas possibleto minimizeinputnoise coupling.Both noiseand undesireddigitalclockcouplingtotheseinputscan cause system errors.The source resistancefortheseinputsshould,ingeneral,be keptbelow 5 kΩ.Largervaluesofsourceresistancecan cause undesiredsystem noisepickup.Inputbypass capacitors,placedfromtheanaloginputstoground,willeliminate system noisepickupbut can createanalog scaleerrorsas these capacitorswillaverage the transientinput switchingcurrentsof the A/D (see Analog Inputs— InputCurrent).Thisscaleerrordepends on both a large sourceresistanceand theuse ofan inputbypass capacitor.Thiserrorcan be eliminatedby doinga full-scale adjustmentoftheA/D (adjustVREF /2fora properfull-scalereading— see Full-Scale)withthesourceresistance and inputbypasscapacitorinplace.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 ReferenceVoltage Span Adjust For maximum applicationsflexibility,theseA/Ds have been designedtoaccommodate a 5 VDC ,2.5VDC or an adjustedvoltagereference.Thishas been achievedinthedesignoftheIC as shown inFigure50. Figure50. The VREFERENCE Design on theIC NoticethatthereferencevoltagefortheIC iseither1/2ofthevoltageappliedtotheVCC supplypin,orisequalto thevoltagethatisexternallyforcedattheVREF /2pin.Thisallowsfora ratiometricvoltagereferenceusingthe VCC supply,a 5 VDC referencevoltagecan be used fortheVCC supplyor a voltagelessthan2.5VDC can be appliedtotheVREF /2inputforincreasedapplicationflexibility.The internalgaintotheVREF /2inputis2,making thefull-scaledifferentialinputvoltagetwicethevoltageatpin9. An example of the use of an adjustedreferencevoltageisto accommodate a reduced span — or dynamic voltagerange of the analoginputvoltage.Ifthe analoginputvoltagewere to range from 0.5 VDC to 3.5 VDC , insteadof0V to5 VDC ,thespan would be 3V as shown inFigure51.With 0.5VDC appliedtotheVIN(−) pinto absorbtheoffset,thereferencevoltagecan be made equalto1/2ofthe3V span or1.5VDC. The A/D now will encode theVIN(+)signalfrom 0.5V to3.5V withthe0.5V inputcorrespondingtozeroand the3.5VDC input correspondingto full-scale.The full8 bitsof resolutionare thereforeappliedover thisreduced analog input voltagerange. ReferenceAccuracy Requirements The convertercan be operatedina ratiometricmode oran absolutemode. Inratiometricconverterapplications, themagnitudeofthereferencevoltageisa factorinboththeoutputofthesourcetransducerand theoutputof theA/D converterand thereforecancelsoutinthefinaldigitaloutputcode.The ADC0805 isspecifiedparticularly foruse inratiometricapplicationswithno adjustmentsrequired.In absoluteconversionapplications,both the initialvalueand thetemperaturestabilityofthereferencevoltageareimportantfactorsintheaccuracyoftheA/D converter.ForVREF /2voltagesof2.4VDC nominalvalue,initialerrorsof±10 mV DC willcause conversionerrorsof ±1 LSB due tothegainof2 oftheVREF /2input.Inreducedspan applications,theinitialvalueand thestabilityof theVREF /2inputvoltagebecome even more important.For example,ifthespan isreducedto2.5V,theanalog inputLSB voltagevalueiscorrespondinglyreducedfrom 20 mV (5V span)to10 mV and 1 LSB attheVREF /2 inputbecomes 5 mV. As can be seen,thisreducesthe allowedinitialtoleranceof the referencevoltageand requirescorrespondinglylessabsolutechange withtemperaturevariations.Note thatspans smallerthan 2.5V placeeven tighterrequirementson theinitialaccuracyand stabilityofthereferencesource. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com Ingeneral,themagnitudeofthereferencevoltagewillrequirean initialadjustment.Errorsdue toan improper valueofreferencevoltageappear as full-scaleerrorsintheA/D transferfunction.IC voltageregulatorsmay be used forreferencesiftheambienttemperaturechanges arenotexcessive.The LM336B 2.5V IC referencediode (fromNationalSemiconductor)has a temperaturestabilityof1.8mV typ(6mV max) over0°C ≤TA≤+70°C. Other temperaturerangepartsarealsoavailable. a)Analog InputSignalExample *Add ifVREF/2 ≤ 1 VDC withLM358 todraw 3 mA to ground. b)Accommodating an Analog Inputfrom 0.5V (DigitalOut = 00HEX )to3.5V (DigitalOut=FF HEX ) Figure51.Adapting theA/D Analog InputVoltagestoMatch an ArbitraryInputSignalRange Errorsand ReferenceVoltageAdjustments Zero Error The zero of the A/D does not requireadjustment.Ifthe minimum analoginputvoltagevalue,VIN(MIN), isnot ground,a zerooffsetcan be done.The convertercan be made tooutput0000 0000 digitalcode forthisminimum inputvoltageby biasingtheA/D VIN(−) inputatthisVIN(MIN)value(seeApplicationssection).Thisutilizesthe differentialmode operationoftheA/D. The zeroerroroftheA/D converterrelatestothelocationofthefirstriserofthetransferfunctionand can be measured by groundingtheVIN(−)inputand applyinga smallmagnitudepositivevoltagetotheVIN(+)input.Zero erroristhedifferencebetween theactualDC inputvoltagethatisnecessarytojustcause an outputdigitalcode transitionfrom0000 0000 to0000 0001 and theideal1/2LSB value(1/2LSB = 9.8mV forVREF /2=2.500VDC ). Full-Scale The full-scaleadjustmentcan be made by applyinga differentialinputvoltagethatis11/2 LSB lessthan the desiredanalogfull-scalevoltagerange and thenadjustingthemagnitudeoftheVREF /2input(pin9 or theVCC supplyifpin9 isnotused)fora digitaloutputcode thatisjustchangingfrom1111 1110 to1111 1111. Adjustingforan ArbitraryAnalog InputVoltageRange IftheanalogzerovoltageoftheA/D isshiftedaway fromground(forexample,toaccommodate an analoginput signalthatdoes notgo toground)thisnew zeroreferenceshouldbe properlyadjustedfirst.A VIN(+)voltagethat equalsthisdesiredzero referenceplus1/2 LSB (where the LSB iscalculatedforthe desiredanalogspan,1 LSB=analog span/256)isappliedtopin6 and thezeroreferencevoltageatpin7 shouldthenbe adjustedtojust obtainthe00HEX to01HEX code transition. The full-scaleadjustmentshouldthenbe made (withtheproperVIN(−)voltageapplied)by forcinga voltagetothe VIN(+)inputwhichisgivenby:

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/c45 /c43 /c43 /c45 /c61 /c233 /c249 /c230 /c246 /c230 /c246 /c45 /c234 /c250 /c231 /c247 /c231 /c247 /c231 /c247 /c231 /c247 /c45/c234 /c250 /c232 /c248 /c232 /c248/c235 /c251 /c64 CLK CC T T CC T T V V VRC ln V V V R 10 kΩ ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 (4) where: VMAX = The highend oftheanaloginputrangeand VMIN = thelowend (theoffsetzero)oftheanalogrange.(Botharegroundreferenced.) The VREF /2(orVCC )voltageisthenadjustedtoprovidea code change fromFE HEX toFFHEX .Thiscompletesthe adjustmentprocedure ClockingOption The clockforthe A/D can be derivedfrom the CPU clockor an externalRC can be added to provideself- clocking.The CLK IN (pin4)makes use ofa Schmitttriggeras shown inFigure52. Figure52. Self-ClockingtheA/D Heavy capacitiveor DC loadingof the clockR pin shouldbe avoidedas thiswilldisturbnormal converter operation.Loads lessthan50 pF,such as drivingup to7 A/D converterclockinputsfroma singleclockR pinof 1 converter,are allowed.For largerclocklineloading,a CMOS or low power TTL bufferor PNP inputlogic shouldbe used tominimizetheloadingon theclockR pin(donotuse a standardTTL buffer). RestartDuring a Conversion IftheA/D isrestarted(CS and WR go low and returnhigh)duringa conversion,theconverterisresetand a new conversionisstarted.The outputdata latchisnot updated ifthe conversioninprocessisnot allowedto be completed,thereforethedataofthepreviousconversionremainsinthislatch.The INTR outputsimplyremains atthe“1”level. Continuous Conversions For operationinthefree-runningmode an initializingpulseshouldbe used,followingpower-up,toensurecircuit operation.Inthisapplication,theCS inputisgroundedand theWR inputistiedtotheINTR output.ThisWR and INTR node shouldbe momentarilyforcedtologiclowfollowinga power-upcycletoensureoperation. DrivingtheData Bus ThisMOS A/D,likeMOS microprocessorsand memories,willrequirea bus driverwhen thetotalcapacitanceof thedatabus getslarge.Othercircuitry,whichistiedtothedatabus,willadd tothetotalcapacitiveloading,even inTRI-STATE (highimpedance mode).Backplanebussingalsogreatlyadds tothestraycapacitanceofthedata bus. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com There aresome alternativesavailabletothedesignertohandlethisproblem.Basically,thecapacitiveloadingof thedatabus slowsdown theresponsetime,even thoughDC specificationsarestillmet.For systemsoperating witha relativelyslowCPU clockfrequency,more timeisavailableinwhichtoestablishproperlogiclevelson the bus and thereforehighercapacitiveloadscan be driven(seetypicalcharacteristicscurves). At higherCPU clockfrequenciestimecan be extendedforI/Oreads (and/orwrites)by insertingwaitstates (8080)orusingclockextendingcircuits(6800). Finally,iftimeisshortand capacitiveloadingishigh,externalbus driversmust be used.These can be TRI- STATE buffers(lowpower Schottkysuch as the DM74LS240 seriesisrecommended) or specialhigherdrive currentproductswhich are designed as bus drivers.High currentbipolarbus driverswithPNP inputsare recommended. Power Supplies Noisespikeson theVCC supplylinecan cause conversionerrorsas thecomparatorwillrespondtothisnoise.A low inductancetantalumfiltercapacitorshouldbe used closeto the converterVCC pinand valuesof 1 µF or greaterare recommended. Ifan unregulatedvoltageisavailableinthesystem,a separateLM340LAZ-5.0,TO- 92,5V voltageregu-latorfortheconverter(andotheranalogcircuitry)willgreatlyreducedigitalnoiseon theVCC supply. Wiringand Hook-Up Precautions Standarddigitalwirewrap socketsare not satisfactoryforbreadboardingthisA/D converter.Socketson PC boardscan be used and alllogicsignalwiresand leadsshouldbe grouped and keptas faraway as possible from the analogsignalleads.Exposed leadsto the analoginputscan cause undesireddigitalnoiseand hum pickup,thereforeshieldedleadsmay be necessaryinmany applications. A singlepointanalogground thatisseparatefrom thelogicground pointsshouldbe used.The power supply bypass capacitorand theself-clockingcapacitor(ifused)shouldbothbe returnedtodigitalground.Any VREF /2 bypass capacitors,analog inputfiltercapacitors,or inputsignalshieldingshouldbe returnedto the analog groundpoint.A testforpropergroundingistomeasure thezeroerroroftheA/D converter.Zero errorsinexcess of 1/4 LSB can usuallybe tracedto improperboard layoutand wiring(see Zero Errorformeasuringthe zero error). TESTING THE A/D CONVERTER There aremany degreesofcomplexityassociatedwithtest-ingan A/D converter.One ofthesimplesttestsisto applya known analoginputvoltagetotheconverterand use LEDs todisplaytheresultingdigitaloutputcode as shown inFigure53. For ease oftesting,theVREF /2(pin9)shouldbe suppliedwith2.560VDC and a VCC supplyvoltageof5.12VDC shouldbe used.Thisprovidesan LSB valueof20 mV. Ifa full-scaleadjustmentistobe made, an analoginputvoltageof5.090VDC (5.120–1/⁄2 LSB) shouldbe applied totheVIN(+)pinwiththeVIN(−)pingrounded.The valueoftheVREF /2inputvoltageshouldthenbe adjusteduntil thedigitaloutputcode isjustchangingfrom1111 1110 to1111 1111.ThisvalueofVREF /2shouldthenbe used forallthetests. The digitaloutputLED displaycan be decoded by dividingthe8 bitsinto2 hex characters,the4 most significant (MS) and the4 leastsignificant(LS).Table2 shows thefractionalbinaryequivalentofthesetwo 4-bitgroups.By addingthe voltagesobtainedfrom the "VM" and "VLS" columns inTable 2 , the nominalvalueof the digital display(when VREF /2= 2.560V)can be determined.For example,foran outputLED displayof1011 0110 orB6 (inhex),thevoltagevaluesfrom thetableare 3.520+ 0.120or 3.640VDC .These voltagevaluesrepresentthe center-valuesof a perfectA/D converter.The effectsof quantizationerrorhave to be accountedforin the interpretationofthetestresults.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 Figure53. Basic A/D Tester For a higherspeed testsystem,ortoobtainplotteddata,a digital-to-analogconverterisneeded forthetestset- up.An accurate10-bitDAC can serveas theprecisionvoltagesourcefortheA/D.ErrorsoftheA/D undertest can be expressedas eitheranalogvoltagesordifferencesin2 digitalwords. A basicA/D testerthatuses a DAC and providestheerroras an analogoutputvoltageisshown inFigure52. The 2 op amps can be eliminatedifa labDVM witha numericalsubtractionfeatureisavailableto read the differencevoltage,"A–C",directly.The analoginputvoltagecan be suppliedby a low frequencyramp generator and an X-Y plottercan be used toprovideanalogerror(Y axis)versusanaloginput(X axis). For operationwitha microprocessorora computer-basedtestsystem,itismore convenienttopresenttheerrors digitally.Thiscan be done withthecircuitofFigure55,where theoutputcode transitionscan be detectedas the 10-bitDAC isincremented.Thisprovides1⁄4 LSB stepsforthe8-bitA/D undertest.Iftheresultsofthistestare automaticallyplottedwiththeanaloginputon theX axisand theerror(inLSB ’s)as theY axis,a usefultransfer functionoftheA/D undertestresults.Foracceptancetesting,theplotisnotnecessaryand thetestingspeed can be increasedby establishinginternallimitson theallowederrorforeach code. MICROPROCESSOR INTERFACING To dicusstheinterfacewith8080A and 6800 microprocessors,a common sample subroutinestructureisused. The microprocessorstartstheA/D,readsand storestheresultsof16 successiveconversions,thenreturnstothe user’s program.The 16 databytesarestoredin16 successivememory locations.AllData and Addresseswillbe given in hexadecimal form. Software and hardware detailsare pro- vided separatelyfor each type of microprocessor. Interfacing8080 MicroprocessorDerivatives(8048,8085) Thisconverterhas been designedtodirectlyinterfacewithderivativesofthe8080 microprocessor.The A/D can be mapped intomemory space (usingstandardmemory addressdecodingforCS and theMEMR and MEMW strobes)oritcan be controlledas an I/Odeviceby usingtheI/OR and I/OW strobesand decodingtheaddress bitsA0 → A7 (oraddressbitsA8 → A15 as theywillcontainthesame 8-bitaddressinformation)toobtainthe CS input.UsingtheI/Ospace provides256 additionaladdressesand may allowa simpler8-bitaddressdecoder butthedatacan onlybe inputtotheaccumulator.To make use oftheadditionalmemory referenceinstructions, theA/D shouldbe mapped intomemory space.An example ofan A/D inI/Ospace isshown inFigure56. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com Figure54. A/D TesterwithAnalog ErrorOutput Figure55. Basic “Digital” A/D Tester Table2.Decoding theDigitalOutput LEDs OUTPUT VOLTAGE CENTER VALUESFRACTIONAL BINARY VALUE FOR WITH VREF /2=2.560VDCHEX BINARY MS GROUP LS GROUP VMS GROUP (1) VLS GROUP (1) F 1 1 1 1 15/16 15/256 4.800 0.300 E 1 1 1 0 7/8 7/128 4.480 0.280 D 1 1 0 1 13/16 13/256 4.160 0.260 C 1 1 0 0 3/4 3/64 3.840 0.240 B 1 0 1 1 11/16 11/256 3.520 0.220 A 1 0 1 0 5/8 5/128 3.200 0.200 9 1 0 0 1 9/16 9/256 2.880 0.180 8 1 0 0 0 1/2 1/32 2.560 0.160 7 0 1 1 1 7/16 7/256 2.240 0.140 6 0 1 1 0 3/8 3/128 1.920 0.120 5 0 1 0 1 5/16 2/256 1.600 0.100 4 0 1 0 0 1/4 1/64 1.280 0.080 3 0 0 1 1 163 3/256 0.960 0.060 2 0 0 1 0 1/8 1/128 0.640 0.040 1 0 0 0 1 1/16 1/256 0.320 0.020 0 0 0 0 0 0 0 (1) DisplayOutput=VMS Group + VLS Group

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 (1) *Pinnumbers fortheDP8228 systemcontroller,othersareINS8080A (2) Pin 23 of the INS8228 must be tiedto +12V througha 1 kΩ resistorto generatethe RST 7 instructionwhen an interruptisacknowledgedas requiredby theaccompanyingsample program. Figure56. ADC0801_INS8080A CPU Interface Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com SAMPLE PROGRAM FOR Figure56 ADC0801 –INS8080A CPU INTERFACE Note:The stackpointermust be dimensionedbecause a RST 7 instructionpushes thePC ontothestack. Note:Alladdressused were arbitrarilychosen. The standardcontrolbus signalsofthe8080 CS, RD and WR) can be directlywiredtothedigitalcontrolinputs oftheA/D and thebus timingrequirementsaremet toallowbothstartingtheconverterand outputtingthedata ontothedatabus.A bus drivershouldbe used forlargermicroprocessorsystemswhere thedatabus leavesthe PC boardand/ormust drivecapacitiveloadslargerthan100 pF. Sample 8080A CPU InterfacingCircuitryand Program The followingsample program and associatedhardwareshown inFigure56 may be used toinputdatafromthe converterto the INS8080A CPU chipset (comprisedof the INS8080A microprocessor,the INS8228 system controllerand theINS8224 clockgenerator).For simplicity,theA/D iscontrolledas an I/Odevice,specificallyan 8-bitbi-directionalportlocatedatan arbitrarilychosen portaddress,E0. The TRI-STATE outputcapabilityofthe A/D eliminatestheneed fora peripheralinterfacedevice,however addressdecodingisstillrequiredtogenerate theappropriateCS fortheconverter. Itisimportanttonotethatinsystemswhere theA/D converteris1-of-8orlessI/Omapped devices,no address decodingcircuitryisnecessary.Each ofthe8 addressbits(A0 toA7) can be directlyused as CS inputs— one foreach I/Odevice. INS8048 Interface The INS8048 interfacetechniquewiththe ADC0801 series(see Figure57) issimplerthan the 8080A CPU interface.Thereare24 I/Olinesand threetestinputlinesinthe8048.WiththeseextraI/Olinesavailable,one of theI/Olines(bit0 ofport1)isused as thechipselectsignaltotheA/D,thuseliminatingtheuse ofan external addressdecoder.Bus controlsignalsRD, WR and INT ofthe8048 aretieddirectlytotheA/D.The 16 converted datawords arestoredaton-chipRAM locationsfrom20 to2F (Hex).The RD and WR signalsaregeneratedby readingfromand writingintoa dummy address,respectively.A sample interfaceprogramisshown below.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 Figure57. INS8048 Interface SAMPLE PROGRAM FOR Figure57 INS8048 INTERFACE InterfacingtheZ-80 The Z-80 controlbus isslightlydifferentfrom thatofthe8080.GeneralRD and WR strobesare providedand separatememory request,MREQ, and I/Orequest,IORQ, signalsareused whichhave tobe combined withthe generalizedstrobestoprovidetheequivalent8080 signals.An advantageofoperatingtheA/D inI/Ospace with theZ-80 isthattheCPU willautomaticallyinsertone waitstate(theRD and WR strobesareextendedone clock period)to allowmore time forthe I/O devicesto respond.Logicto map the A/D in I/O space isshown in Figure58. Figure58. Mapping theA/D as an I/ODevice forUse withtheZ-80CPU AdditionalI/Oadvantagesexistas softwareDMA routinesareavailableand use can be made oftheoutputdata transferwhich existson theupper 8 addresslines(A8 toA15) duringI/Oinputinstructions.For example,MUX channelselectionfortheA/D can be accomplishedwiththisoperatingmode. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com Interfacing6800 MicroprocessorDerivatives(6502,etc.) The controlbus forthe6800 microprocessorderivativesdoes notuse theRD and WR strobesignals.Insteadit employs a singleR/W lineand additionaltiming,ifneeded,can be derivedfromtheφ2 clock.AllI/Odevicesare memory mapped inthe 6800 system,and a specialsignal,VMA, indicatesthatthe currentaddressisvalid. Figure59 shows an interfaceschematicwhere theA/D ismemory mapped inthe6800 system.For simplicity, theCS decodingisshown using1/2DM8092. Note thatinmany 6800 systems,an alreadydecoded 4/5lineis broughtouttothecommon bus atpin21.Thiscan be tieddirectlytotheCS pinoftheA/D,providedthatno otherdevicesareaddressedatHX ADDR: 4XXX or5XXX. The followingsubroutineperformsessentiallythesame functionas inthecase ofthe8080A interfaceand itcan be calledfromanywhere intheuser’s program. InFigure60 theADC0801 seriesisinterfacedtotheM6800 microprocessorthrough(thearbitrarilychosen)Port B oftheMC6820 orMC6821 PeripheralInterfaceAdapter,(PIA). Here theCS pinoftheA/D isgroundedsincethePIA isalreadymemory mapped intheM6800 system and no CS decodingisnecessary.AlsonoticethattheA/D outputdatalinesare connectedtothemicroprocessorbus underprogramcontrolthroughthePIA and thereforetheA/D RD pincan be grounded. A sample interfaceprogram equivalenttothepreviousone isshown below Figure60.The PIA Data and Control RegistersofPortB arelocatedatHEX addresses8006 and 8007,respectively. GENERAL APPLICATIONS The followingapplicationsshow some interestinguses fortheA/D.The factthatone particularmicroprocessoris used isnot meant to be restrictive.Each of these applicationcircuitswould have itscounterpartusingany microprocessorthatisdesired. MultipleADC0801 SeriestoMC6800 CPU Interface To transferanalogdatafrom severalchannelstoa singlemicroprocessorsystem,a multipleconverterscheme presentsseveraladvantagesover the conventionalmultiplexersingle-converterapproach.With the ADC0801 series,the differentialinputsallowindividualspan adjustmentforeach channel.Furthermore,allanaloginput channelsaresensed simultaneously,whichessentiallydividesthemicroproces-sor’s totalsystem servicingtime by thenumber ofchannels,sinceallconversionsoccursimultaneously.Thisscheme isshown inFigure61. *Numbers inparenthesesrefertoMC6800 CPU pinout. **Number orlettersinbracketsrefertostandardM6800 systemcommon bus code. Figure59. ADC0801-MC6800 CPU Interface

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 SAMPLE PROGRAM FOR Figure59 ADC0801-MC6800 CPU INTERFACE Inorderforthemicroprocessortoservicesubroutinesand inter-rupts,thestackpointermust be dimensioned intheuser’s program. Figure60. ADC0801 –MC6820 PIA Interface Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com SAMPLE PROGRAM FOR Figure60 ADC0801 –MC6820 PIA INTERFACE The followingschematicand sample subroutine(DATA IN)may be used tointerface(upto)8 ADC0801 ’s directly to the MC6800 CPU. Thisscheme can easilybe extendedto allowthe interfaceof more converters.In this configurationthe convertersare (arbitrarily)locatedat HEX address5000 inthe MC6800 memory space.To save components,theclocksignalisderivedfromjustone RC pairon thefirstconverter.Thisoutputdrivesthe otherA/Ds. Alltheconvertersarestartedsimultaneouslywitha STORE instructionatHEX address5000.Note thatany other HEX addressoftheform 5XXX willbe decoded by thecircuit,pullingalltheCS inputslow.Thiscan easilybe avoidedby usinga more definitiveaddressdecodingscheme. AlltheinterruptsareORed togethertoinsurethat allA/Ds have completedtheirconversionbeforethemicroprocessorisinterrupted. The subroutine,DATA IN, may be calledfrom anywhere in the user’s program.Once called,thisroutine initializestheCPU, startsalltheconverterssimultaneouslyand waitsfortheinterruptsignal.Upon receivingthe interrupt,itreadstheconverters(fromHEX addresses5000 through5007) and storesthedatasuccessivelyat (arbitrarilychosen)HEX addresses0200 to0207,beforereturningtotheuser’s pro-gram.AllCPU registersthen recovertheoriginaldatatheyhad beforeservicingDATA IN. Auto-ZeroedDifferentialTransducer Amplifierand A/D Converter The differentialinputsof the ADC0801 serieseliminatethe need to performa differentialto singleended conversionfora differentialtransducer.Thus,one op amp can be eliminatedsincethedifferentialtosingleended conversionisprovidedby the differentialinputof the ADC0801 series.In general,a transducerpreamp is requiredtotakeadvantageofthefullA/D converterinputdynamicrange.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 *Numbers inparenthesesrefertoMC6800 CPU pinout. **NumbersoflettersinbracketsrefertostandardM6800 systemcommon bus code. Figure61. InterfacingMultipleA/Ds inan MC6800 System Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com SAMPLE PROGRAM FOR Figure61 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM SAMPLE PROGRAM FOR Figure61 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM Note: In order for the microprocessorto servicesubroutinesand interrupts,the stack pointermust be dimensionedintheuser’s program. For amplificationofDC inputsignals,a majorsystem erroristheinputoffsetvoltageoftheamplifiersused for the preamp. Figure62 isa gainof 100 differentialpreamp whose offsetvoltageerrorswillbe cancelledby a zeroingsubroutinewhichisperformedby theINS8080A microprocessorsystem.The totalallowableinputoffset voltageerrorforthispreamp isonly50 µV for/⁄4 LSB error.Thiswould obviouslyrequireverypreciseamplifiers. The expressionforthedifferentialoutputvoltageofthepreamp is:

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 R2 = 49.5R1 SwitchesareLMC13334 CMOS analogswitches. The 9 resistorsused intheauto-zerosectioncan be ±5% tolerance. Figure62. Gain of100 DifferentialTransducer Preamp (5) where IX isthecurrentthroughresistorR X.Alloftheoffseterrortermscan be cancelledby making ±IXR X= VOS1 + VOS3 − VOS2 .Thisistheprincipleofthisauto-zeroingscheme. The INS8080A uses the3 I/Oportsofan INS8255 ProgramablePeripheralInterface(PPI)tocontroltheauto zeroingand inputdatafromtheADC0801 as shown inFigure63.The PPI isprogrammed forbasicI/Ooperation (mode 0) withPortA beingan inputportand PortsB and C beingoutputports.Two bitsofPortC are used to alternatelyopen orclosethe2 switchesattheinputofthepreamp.SwitchSW1 isclosedtoforcethepreamp’s differentialinputto be zero duringthe zeroingsubroutineand then opened and SW2 is then closed for conversionoftheactualdifferentialinputsignal.Using2 switchesinthismanner eliminatesconcernfortheON resistanceoftheswitchesas theymust conductonlytheinputbiascurrentoftheinputamplifiers. OutputPortB isused as a successiveapproximationregisterby the 8080 and the binaryscaledresistorsin serieswitheach outputbitcreatea D/A converter.Duringthezeroingsubroutine,thevoltageatVx increasesor decreasesas requiredtomake thedifferentialoutputvoltageequaltozero.Thisisaccomplishedby ensuring thatthevoltageattheoutputofA1 isapproximately2.5V so thata logic"1"(5V)on any outputofPortB will sourcecurrentintonode VX thusraisingthe voltageat VX and making the outputdifferentialmore negative. Conversely,a logic"0"(0V)willpullcurrentout of node VX and decreasethe voltage,causingthe differential outputtobecome more positive.For theresistorvaluesshown, VX can move ±12 mV witha resolutionof50 µV, whichwillnulltheoffseterrortermto/⁄4 LSB offull-scalefortheADC0801. Itisimportantthatthevoltagelevels thatdrivetheauto-zeroresistorsbe constant.Also,forsymmetry,a logicswing of0V to5V isconvenient.To achievethis,a CMOS bufferisused forthelogicoutputsignalsofPortB and thisCMOS package ispowered witha stable5V source.BufferamplifierA1 isnecessaryso thatitcan sourceorsinktheD/A outputcurrent. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com Figure63. MicroprocessorInterfaceCircuitryforDifferentialPreamp A flowchartforthe zeroingsubroutineisshown inFigure64. Itmust be noted thatthe ADC0801 serieswill outputan allzerocode when itconvertsa negativeinput[VIN(−)≥ VIN(+)].Also,a logicinversionexistsas allof theI/Oportsarebufferedwithinvertinggates. Basically,ifthedatareadiszero,thedifferentialoutputvoltageisnegative,so a bitinPortB isclearedtopullVX more negativewhichwillmake theoutputmore positiveforthenextconversion.Ifthedatareadisnotzero,the outputvoltageispositiveso a bitinPortB issettomake VX more positiveand theoutputmore negative.This continuesfor8 approximationsand thedifferentialoutputeventuallyconvergestowithin5 mV ofzero. The actualprogram isgiveninFigure65.Alladdressesused arecompatiblewiththeBLC 80/10microcomputer system.Inparticular:

• PortA and theADC0801 areatportaddressE4
• PortB isatportaddressE5
• PortC isatportaddressE6
• PPI controlword portisatportaddressE7
• Program Counterautomaticallygoes toADDR:3C3D upon acknowledgmentofan interruptfromtheADC0801 MultipleA/D Convertersina Z-80InterruptDrivenMode Indataacquisitionsystems where more thanone A/D converter(orotherperipheraldevice)willbe interrupting pro-gram executionof a microprocessor,thereisobviouslya need forthe CPU to determinewhich device requiresservicing.Figure66 and theaccompanying softwareisa method ofdeterminingwhich of7 ADC0801 convertershas completeda conversion(INTR asserted)and isrequestingan interrupt.Thiscircuitallowsstarting the A/D convertersin any sequence,but willinputand storevaliddata from the converterswitha priority sequence ofA/D 1 beingread first,A/D 2 second,etc.,throughA/D 7 which would have thelowestpriorityfor databeingread.Onlytheconverterswhose INT isassertedwillbe read.

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 The key to decoding circuitryis the DM74LS373, 8-bitD type flip-flop.When the Z-80 acknowledges the interrupt,theprogram isvectoredtoa datainputZ-80 subroutine.Thissubroutinewillread a peripheralstatus word from the DM74LS373 which containsthe logicstateof the INTR outputsof allthe converters.Each converterwhich initiatesan interruptwillplacea logic"0"ina uniquebitpositioninthe statusword and the subroutinewilldeterminethe identityof the converterand execute a data read.An identifierword (which indicateswhichA/D thedatacame from)isstoredinthenextsequentialmemory locationabove thelocationof thedataso theprogramcan keep trackoftheidentityofthedataentered. Figure64. Flow ChartforAuto-ZeroRoutine Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 www.ti.com NOTE: Allnumericalvaluesarehexadecimalrepresentations. Figure65. SoftwareforAuto-ZeroedDifferentialA/D The followingnotesapply:

• Itisassumed thattheCPU automaticallyperformsa RST 7 instructionwhen a validinterruptisacknowledged (CPU isininterruptmode 1).Hence,thesubroutinestartingaddressofX0038.
• The addressbus fromtheZ-80and thedatabus totheZ-80areassumed tobe invertedby bus drivers.
• A/D dataand identifyingwords willbe storedinsequentialmemory locationsstartingatthearbitrarilychosen addressX 3E00.
• The stackpointermust be dimensionedinthemain program as theRST 7 instructionautomaticallypushes thePC ontothestackand thesubroutineuses an additional6 stackaddresses.
• The peripheralsofconcernaremapped intoI/Ospace withthefollowingportassignments: HEX PORT ADDRESS PERIPHERAL HEX PORT ADDRESS PERIPHERAL

00 MM74C374 8-bitflip-flop 04 A/D 4

01 A/D 1 05 A/D 5

02 A/D 2 06 A/D 6

03 A/D 3 07 A/D 7

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ADC0801,ADC0802 ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013 Thisportaddressalsoservesas theA/D identifyingword intheprogram. Figure66. MultipleA/Ds withZ-80Type Microprocessor Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:ADC0801, ADC0802 ADC0803, ADC0804, ADC0805

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples ADC0801LCN/NOPB ACTIVE PDIP NFH 20 18 Pb-Free (RoHS) SN Level-1-NA-UNLIM -40 to 85 ADC0801LCN ADC0802LCN ACTIVE PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0802LCN ADC0802LCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 ADC0802LCN ADC0802LCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 ADC0802 LCWM ADC0803LCN ACTIVE PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0803LCN ADC0803LCN/NOPB ACTIVE PDIP NFH 20 18 Pb-Free (RoHS) SN Level-1-NA-UNLIM -40 to 85 ADC0803LCN ADC0804LCN ACTIVE PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0804LCN ADC0804LCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 ADC0804LCN ADC0804LCWM ACTIVE SOIC DW 20 36 TBD Call TI Call TI -40 to 85 ADC0804 LCWM ADC0804LCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0804 LCWM ADC0804LCWMX ACTIVE SOIC DW 20 1000 TBD Call TI Call TI -40 to 85 ADC0804 LCWM ADC0804LCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC0804 LCWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

www.ti.com 11-Apr-2013 Addendum-Page 2 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC0804LCWMX SOIC DW 20 1000 367.0 367.0 45.0 ADC0804LCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 2

www.ti.com N20A (Rev G)

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