ADC0803

ADC0803 TI | Alldatasheet

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ADC0803, ADC0805 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH DIFFERENTIAL INPUTS SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00688-Bit Resolution /C0068Ratiometric Conversion /C0068100-µs Conversion Time /C0068135-ns Access Time /C0068Guaranteed Monotonicity /C0068High Reference Ladder Impedance 8 kΩ Typical /C0068No Zero Adjust Requirement /C0068On-Chip Clock Generator /C0068Single 5-V Power Supply /C0068Operates With Microprocessor or as Stand-Alone /C0068Designed to Be interchangeable With National Semiconductor and Signetics ADC0803 and ADC0805

description

The ADC0803 and ADC0805 are CMOS 8-bit, successive-approximation, analog-to-digital converters that use a modified potentiometric (256R) ladder. These devices are designed to operate from common microprocessor control buses with the 3-state output latches driving the data bus. The devices can be made to appear to the microprocessor as a memory location or an I/O port. Detailed information on interfacing to most popular microprocessors is readily available from the factory. A differential analog voltage input allows increased common-mode rejection and offset of the zero-input analog voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller analog voltage spans or to make use of an external reference, ratiometric conversion is possible with the REF/2 input open. Without an external reference, the conversion takes place over a span from V CC to ANLG GND. The devices can operate with an external clock signal or with an additional resistor and capacitor, using an on-chip clock generator. The ADC0803C and ADC0805C are characterized for operation from 0°C to 70°C. The ADC0803I and ADC0805I are characterized for operation from –40°C to 85°C. Copyright  1986, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. CS RD WR CLK IN INTR IN+ IN– ANLG GND REF/2 DGTL GND VCC (OR REF) CLK OUT DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) N PACKAGE (TOP VIEW) DATA OUTPUTS

ADC0803, ADC0805 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH DIFFERENTIAL INPUTS SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram (positive logic) Clk Osc Clk Gen Comp D VCC DAC LE 8-Bit Shift Register SAR Latch Ladder and Decoder 7IN – 6IN + 8ANLG GND 9REF/2 20VCC 10DGTL GND 4CLK IN 19CLK OUT WR RD CS INTR5 Interrupt Flip-Flop R 3-State Output Latch ENLE DB7 (MSB)11 DB612 DB513 DB414 DB315 DB216 DB117 DB0 (LSB)18 R R S C1CLK A CLK B CLK B CLK CLK A Start Flip-Flop CLK A CLK C1R S Σ

ADC0803, ADC0805 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH DIFFERENTIAL INPUTS SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) NOTE 1: All voltage values are with respect to digital ground (DGTL GND) with DGTL GND and ANLG GND connected together unless otherwise noted. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 5 6.3 V Analog input voltage (see Note 2) –0.05 VCC = 0.05 V Voltage at REF/2 (see Note 3), VREF/2 0.25 2.5 V High-level input voltage at CS, RD, or WR, VIH 2 15 V Low-level input voltage at CS, RD, or WR, VIL 0.8 V Analog ground voltage (see Note 4) –0.05 0 1 V Clock iput frequency (see Note 5), fclock 100 640 1460 kHz Duty cycle for fclock above 640 kHz (see Note 5) 40% 60% Pulse durartion, clock input (high or low) for fclock below 640 kHz, tW (CLK) 275 781 ns Pulse durartion, WR input low, tW (WR) 100 ns O perating free air temperature TA ADC080_C 0 70 °COperating free–air temperature, TA ADC080_I –40 85 NOTES: 2. When the differential input voltage (VI+ – VI–) is less than or equal to 0 V, the output code is 0000 0000. 3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one-half of the VCC when REF/2 is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs. Thus, the differential input voltage range when REF/2 is open and VCC = 5 V is 0 V to 5 V. VREF/2 for an input voltage range from 0.5 V to 3.5 V (full-scale differential voltage of 3 V) is 1.5 V. 4. These values are with respect to DGTL GND. 5. Total unadjusted error is specified only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns to 937 ns). For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should be observed for an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK) remains within limits.

ADC0803, ADC0805 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH DIFFERENTIAL INPUTS SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

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electrical characteristics over recommended range of operating free-air temperature, VCC = 5 V, fclock = 640 kHz, VREF/2 = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High level output voltage All outputs VCC = 4.75 V, IOH = –360 µA 2.4 VVOH High-level output voltage DB and INTR VCC = 4.75 V, IOH = –10 µA 4.5 V Data outputs VCC = 4.75 V, IOL = 1.6 mA 0.4 VOL Low-level output voltage INTR output VCC = 4.75 V, IOL = 1 mA 0.4 V CLK OUT VCC = 4.75 V, IOL = 360 µA 0.4 VT+ Clock positive-going threshold voltage 2.7 3.1 3.5 V VT– Clock negative-going threshold voltage 1.5 1.8 2.1 V VT+ –V T– Clock input hysteresis 0.6 1.3 2 V IIH High-level input current 0.005 1 µA IIL Low-level input current –0.005 –1 µA IOZ Off state output current VO = 0 –3 µAIOZ Off-state output current VO = 5 V 3 µA IOHS Short-current output currentOutput high VO = 0, TA = 25°C –4.5 –6 mA IOLS Short-circuit output currentOutput low VO = 5 V, TA = 25°C 9 16 mA ICC Supply current plus reference currentVREF/2 = open, TA = 25°C, CS = 5 V 1.1 1.8 mA R REF/2 Input resistance to reference ladder See Note 6 2.5 8 kΩ C i Input capacitance (control) 5 7.5 pF C o Output capacitance (DB) 5 7.5 pF NOTE 6: Resistance is calculated from the current drawn from a 5-V supply applied to ANLG GND and REF/2. operating characteristics over recommended operating free-air temperature, VCC = 5 V, VREF/2 = 2.5 V, fclock = 640 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Supply-voltage-variation error VCC = 4.5 to 5.5 V, See Note 7 +1/16 ±1/8 LSB Total adusted error ADC0803 With full scale adjustSee Notes 7 and 8 ±1/4 LSBTotal adusted error ADC0803 With full-scale adjust, See Notes 7 and 8 ±1/2 LSB Total unadjusted error ADC0805 VREF/2 = 2.5 V, See Notes 7 and 8 ±1/2 LSBTotal unadjusted error ADC0805 VREF/2 open, See Notes 7 and 8 ±1 LSB DC common-mode error See Notes 7 and 8 ±1/16 ±1/8 LSB ten Output enable time TA = 25°C, C L = 100 pF 135 200 ns tdis Output disable time TA = 25°C, CL = 10 pF,R L = 10 kΩ 125 200 ns td(INTR) Delay time to reset INTR TA = 25°C 300 450 nx t Conversion cycle time fclock = 100 kHz to 1.46 MHz, clock tconv Con version cycle time TA = 25°C, See Note 9 73 cycles CR Free-running conversion rate INTR connected to WR, CS at 0 V 66 8770 conv/s † All typical values are at TA = 25°C. NOTES: 7. These parameters are specified over the recommended analog input voltage range. 8. All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristics. 9. Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock periods before conversion starts. After conversion is complete, part of another clock period is required before a high-to-low transition of INTR completes the cycle.

8 Clock Periods (Min)

Figure 1. Read Operation Timing Diagram Figure 2. Write Operation Timing Diagram

ADC0803, ADC0805 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH DIFFERENTIAL INPUTS SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

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The ADC0803 and ADC0805 each contain a circuit equivalent to 256-resistor network. Analog switches are sequenced by successive-approximation logic to match an analog differential input voltage (VI+ – VI–) to a corresponding tap on the 256R network. The most significant bit (MSB) is tested first. After eight spelled out comparisons (64 clock periods), an eight-bit binary code (1111 1111 = full scale) is transferred to an output latch and the interrupt (INTR ) output goes low. The device can be operated in a free-running mode by connecting the INTR output to the write (WR) input and holding the conversion start (CS) input at a low level. To ensure start up under all conditions, a low-level WR input is required during the power-up cycle. Taking CS low any time after that will interrupt a conversion in process. When WR goes low, the internal successive-approximation register (SAR) and 8-bit shift register are reset. As long as both CS and WR remain low, the analog-to-digital converter remains in a reset state. One to eight clock periods after CS or WR makes a low-to-high transition, conversion starts. When CS and WR are low, the start flip-flop is set and the interrupt flip-flop and 8-bit register are reset. The next clock pulse transfers a logic high to the output of the start flip-flop. The logic high is ANDed with the next clock pulse, placing a logic high on the reset input of the start flip-flop. If either CS or WR have gone high, the set signal to the start flip-flop is removed, causing it to be reset. A logic high is placed on the D input of the eight-bit shift register and the conversion process is started. If CS and WR are still low, the start flip-flop, the 8-bit shift register, and the SAR remain reset. This action allows for wide CS and WR inputs, with conversion starting from one to eight clock periods after one of the inputs goes high. When the logic high input has been clocked through the 8-bit shift register, which completes the SAR search, it is applied to an AND gate controlling the output latches and to the D input of a flip-flop. On the next clock pulse, the digital word is transferred to the 3-state output latches and the interrupt flip-flop is set. The output of the interrupt flip-flop is inverted to provide an INTR output that is high during conversion and low when the conversion is complete. When a low is at both CS and RD, an output is applied to the DB0 through DB7 outputs and the interrupt flip-flop is reset. When either CS or RD return to a high state, the DB0 through DB7 outputs are disabled (returned to the high-impedance state). The interrupt flip-flop remains reset.

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