ADC080X NSC | Alldatasheet
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= snninsaalcsannalauacismataggatiniaadinses- os == : t a I o | 2} - | | h 8 7Nationa , < Semiconductor s 2 ‘ 8 | ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 2 | 8-Bit .P Compatible A/D Converters SB 2 | General Description : : © | The ADC0801, ADCO802, ADC0803, ADCO804 and ® Differential analog voltage inputs B ;ADCO805 are CMOS 8-bit successive approximation A/D Logic inputs and outputs moet both MOS and TTL volt- * > | converters that use a differential potentiometric ladder— age level specifications & | similar to the 256R products. These converters are de- Works with 2.5V (M336) voltage reference _ & | signed to allow operation with the NSC800 and INS8080A iw On.chip clock genorator i Q | Gerivative control bus with TRESTATE® output latches d- gov tg SV analog input voltage range with single 5V 8 rectly driving the data bus. These A/Ds appear like memory supply S enters eens to the microprocessor and no inter- @ No zaro adjust required 3 Diff . i i 1 hi @ 0.3" standard width 20-pin DIP Package & | Ditferential analog voltage inputs allow increasing the com- i 20-pin molded chip carrier or small outline package © | mon-mode rejection and offsetting the analog zero input Bowral i i Vee 25; Q | voltage value. In addition, the voltage reference input can ™ i perates eee ly or m 5 Voc. ‘De, OF ana- | be adjusted to allow encoding any smalier analog voltage log span adjusted voltage reference span to the full 8 bits of resolution. . Key Specifications Features = Resolution 8 bits = Compatible with 8080 P derivatives—no interfacing ™ Total error +% LSB, 4% LSB and +1 LSB | logic needed - access time - 135 ns ™ Conversion time 100 ws ™ Easy interface to all microprocessors, or operates “stand alone” Sa en nen — Typical Applications f 1° w hei = ——— : : 9 4I Re, | z a vel | os [eC “TR “| oe eon NT traxsoucen rs | vd AMALOG INPUT. x _ | TTS bey eal fe" ona 1 wana F a] Vace@ 0 ste section = = | one ‘OGKo| i BORD totettiies Error Specification (Includes Full-Scale, | Zero Error, and Non-Linearity) Q Full. : | | | | Part scale--| VREF/2=2.500 Voc | Vaer/2=No Connection rm q Number (No Adjustments) (No Adjustments) | tau, 2:22" rae Ee ' SF cee
ie . f OSS SF - a > 1 - ‘ Absolute Maximum Ratings (notes 1&2) 8 If Military/Aerospace specified devices are required, Storage Temperature Range 6s'Croriscc |Z please contact the National Semiconductor Sales Package Dissipation at Ta = 25°C srinw | 2 Office/Distributors for availability and specifications. = ~ ESO Susceptibility (Note 10) soov | > Supply Voitage (Veg) (Note 3) , 65V ft Voltage . . rel Logic Control Inputs -0.dV 10 +18V Operating Ratings notes + ¢ 2) S At Other Input and Outputs ~0.3V to (Veg +0.3V) Temperature Range TMINS TAS Tmax ° Lead Temp, (Soldering, 10 seconds) A0C0801/02LJ ~S5°CaTas t1a5¢ | & Dual-in-Line Package (plastic) 260°C ADCO801/02/03/04LCJ "40°C Tas tase |B Dual-In-Line Package (ceramic) 300°C ADC0801/02/03/05LCN 40°CsTan+esc | S ‘ Surface Mount Pack: AODCO804LCN OCsTa~ 470°C =} i ur'ace Mount Package . ADC0802/03/04LCV OCsTast7oc |B Vapor Phase (60 seconds) 215°C ‘ : 3 | [ ities ote ADC0802/03/04LCWM OCsTast700 |B bye jennie) Range of Voc 4.5 Voc 106.3 Voc > : Electrical Characteristics fe) The following specifications apply for Veg = 5 Vg, Twins Ta S Tmax and {cL = 640 kHz unless otherwise specified s i cr — Parameter Conditions [Min | Typ | Max units | = ‘ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj, <4 sa IG a (See Section 2.5.2) | th u r=) ADC0802: Total Unadjusted Error (Note 8) | _Vaer/2=2,500 Yoo a se iss. |2 ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj, ; iss |@ (See Section 2.5.2) t% ADCO804: Total Unadjusted Error (Note 8) | Vec/2=2.500 Voc | es LsB ADCO805: Total Unadjusted Error (Note 8) | Vagr/2-No Connection rs ee LsB Vaer/2 Input Resistance (Pin 9) ADC0801/02/03/05 25 8.0 KA \\ |__ Analog input Voltage Range (Note 4) V(+) or V(—) Gnd-0.05 Voc i | | OC Common-Mode Error Over Analog Input Voltage t%6 £% LsB | Range | Power Supply Sensitivity Voc=5Vp¢ 10% Over %e +% iss Allowed Vin( +) and Vin —) | Voltage Range (Note 4) | AC Electrical Characteristics 7 | __The following specitications-apply for Voo=5 Vog and Ta=25*C unless otherwise specitied. | |__Symbol Parameter Conditions [min | typ | Max | Unite ™ & oa |_Tc foux=640KHz (Notes) | 09 | ata | s zs | foux Clock Frequency Voc = 8V, (Note 5) 100 1460 kHz C= _ 4 | Clock Duty Cycle (Note 5) 40 60 % LI RC A a / ] CR Conversion Rate in Free-Running TNTR tied to WR with 8770 9708 | conv/s Mode CS=0 Voc, fox = 640 kHz Ww(WF)._| Width of WA Input (Start Pulse Width) | _C5=0Vpc (Noto 7) a tace Access Time (Delay trom Falling 135 | 200 ns Edge of RD to Output Data Valid) tito | TRISTATE Control (Delay C.=10 pF, RL = 10k 125 | 200 ns from Rising Edge of RD to (See TRI-STATE Test Hi-Z State) Circuits) wi te Delay from Falling Edge 300 ns i | of Wh or FD to Reset of INTR I oy Input Capacitance of Logic 5 75 pF i Control Inputs Cour TRI-STATE Output 7.5 .| PF. i Capacitance (Data Buffers) | CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger crcult and ls therefore specified separately) i | | Vin (a) Logical "1" Input Voltage 2.0 Voc | (Except Pin 4 CLK IN) d | i | 2.23
The following specifications apply for Voc = SVoc and Twin < Ta S Tax. unless otherwise specified symbot_[ Parameter | Conditions [win [tye | mex [done CONTROL INPUTS (Note: CLK IN (Pin 4 s the input of a Schmitt tigger crcuN and is therefore specified separately] Vin (0) Logical "0" Input Voltage Voo= 4.75 Voc Voc (Except Pin 4 CLK IN) hy Logical “1” Input Currant Vin =5 Voc Adc {All inputs) un (0) Logical “0” Input Current Vin =9 Voc — Adc (All inputs) CLOCK IN AND CLOCK R. a vy+ CLK IN (Pin 4) Positva Going 27 as Voc Threshold Voltage - ? vy CLK IN (Pin 4) Negatve 1s 21 Voc 1 Going Threshold Voitage Vin CLIN (Pin 4) Hysteresis, 20 Voc Wr+)-(Vr-) Your (0) | Logical "0" CLK R Output lo= 360 pA os Voc Voltage Veo =4 75 Voc Your (i) | Logicat"1 CLK R Output lo= 360 pa 24 Voc Voitage Voo= 475 Voc DATA OUTPUTS AND INTR Vour (0) | Logical “0 Output Voltage Data Outputs lour= 1.6 MA, Vor =4.75 Voc o4 Voc % INTR Output lout = 1.0 mA, Vor = 4.75 Voc o4 Voc Nouri) | Lopes" Oupuvonage | io= “104A Voc=475Voe [«s [| | voc tour TRISTATE Disabled Output Vour=0 Ve Adc _ Leakage (AN Data Butters) Vout™ 5 Voc 3 Age ‘sousce |_| vey StonoGra Tanase | as |e | oc tmx _[|___T Vour Stertto Vers Ta=asie | v0 | ve | Age POWER SUPPLY lee Supply Current (Includes foun = 640 kH2, Ladder Current) Vner/2= NC, Ty = 25°C and CS= sv A0C0801/02/03/04LCJ/05 ‘ " 18 mA ‘ADCOBO4LCN/LCW/LCWM 19 25 mA Perce Laks Mameruim Rat echcate lets boro whieh damage w te deve may ooaa, OC aNd AC eecicalsowGMcatons do nO bop shes operaing : the ence beyond ks pected peraing constons 1 Mote 2: AX votages a'¢ maasurad wh respect 10 Grd, unless oterws specified. The separate A Grd point shoukd aways be wred to the 0 Get Mote 3A rene Gods ems, muamaty, Hom Voc 16 God and has 4 typcal breakdown vohage Ot 7 Voc mee FS Nek-12 Ved) Ggtal OAD code wi ba 0000 0000. Two onchip axes aie bed i eect analog Vput (se SCA agri which wil forward STR ian ist wotages one dae crop below govnd ox ona Goce crop greeter Pan te Vox mwoty Be carvia. dariy ainsi tow Vox wees we sey SER rat rng roves (SV) can cane Wis wet code 0 concaci-eapeciay at elevated temperaniren ard cause ators Wy araiop rpuns hes herieue the Fe ST re tas of ee: ce. Tes means tht es tong as the analog Vv does Not excwed the suey vohage by mors tan 50 mV. ve suas Seer LET Te thay an ttc © Voc 10 § Vor monn ottge range wit Hereiore requre & muir miphy vokage ot 650 Vine ove laments ‘veriatona, ital tolerance and bain. TOES Ee eee tax = S40 AL Nghe cock quencies accurscy can degrade. For lowe dock Irequencien, the city eye lta can be ‘srtendad #o long as fee miimurn cock Mh te inkaral or mirmam lock low tne Faecal wre loea Bear ore se ToS tem an szmetronous start pute, up wo 8 dock periods mey be required betore he intemal lock phase are proper 10 sian te comerion proces. The start request ts tarred leiched, seu Figure 2 and vecton 20 SZ TS routs assures to tract ne WR srobe rout and twereore timing ls dependent onthe WF pute wit. An erica wie pulse wom wat hols ine converter & reeet mode and the st of conversion a Iviaed by the low 1 High ranation of he WH puss (ewe tig Gegraray ote &: None of ewe A/Os requires 4 er achat (New secon 251) To obtain rer coos al ter analog Input wotages tes ancien 25 and Figure $ mo cteae a LRO7? Bin ie te center Bont of Wwo-estor ver connected fom Ver: 10 ground. In al versione of the ADCDEN}, ADCDNO2, ADCDEGD, and ADCOGOS, ec the ADCDGOALC. each roar pay 18 Kf. bn a versone of the ADCOROM wrcept Poe ADCOOOMLCA, sack loustore Koconr ee at Mote 16: Heenan body model, 100 BF dachargad tough 8 15 kA relator, -5.11-