ADC0803-N

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Analog-to-Digital Converters

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Sample & Buy T echnical Documents Tools & Software Support & Community ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 SNOSBI1C – NOVEMBER 2009–REVISED JUNE 2015 ADC080x8-Bit,µP-Compatible,Analog-to-DigitalConverters

1 Features 3 Description

The ADC0801, ADC0802, ADC0803, ADC0804, and 1• Compatible With 8080-µP Derivatives – No ADC0805 devices are CMOS 8-bit successiveInterfacing Logic Needed – Access Time 135 ns approximation converters (ADC) that use a differential• Easy Interface to All Microprocessors, or Operates potentiometric ladder — similar to the 256R products. as a Stand-Alone Deivce These converters are designed to allow operation with the NSC800 and INS8080A derivative control• Differential Analog Voltage Inputs bus with Tri-state output latches directly driving the• Logic Inputs and Outputs Meet Both MOS and data bus. These ADCs appear like memory locationsTTL Voltage-Level Specifications or I/O ports to the microprocessor and no interfacing• Works With 2.5-V (LM336) Voltage Reference logic is needed.

On-Chip Clock Generator Differential analog voltage inputs allow increasing the
0-V to 5-V Analog Input Voltage Range With common-mode rejection and offsetting the analog Single 5-V Supply zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding• No Zero Adjust Required any smaller analog voltage span to the full 8 bits of• 0.3-Inch Standard Width 20-Pin DIP Package resolution.• 20-Pin Molded Chip Carrier or Small Outline Package Device Information(1)
Operates Ratiometrically or With 5 VDC, 2.5 VDC, PART NUMBER PACKAGE BODY SIZE (NOM) or Analog Span Adjusted Voltage Reference ADC0801, PDIP (20) 26.073 mm × 6.604 mmADC0803• Key Specifications PDIP (20) 26.073 mm × 6.604 mmADC0802,– Resolution: 8 Bits ADC0804 SOIC (20) 12.80 mm × 7.50 mm– Total Error: ±1/4 LSB, ±1/2 LSB and ±1 LSB (1) For all available packages, see the orderable addendum at– Conversion Time: 100 µs the end of the data sheet.

2 Applications

Operates With Any 8-Bit µP Processors or as a Stand-Alone Device
Interface to Temp Sensors, Voltage Sources, and Transducers Typical Application Schematic ADC0801 Specified With ±¼ LSB Accuracy An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 SNOSBI1C – NOVEMBER 2009– REVISED JUNE 2015 www.ti.com Table of Contents

4 Revision History

Changes from Revision B (Feburary 2013) to Revision C Page

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

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Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

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5 Pin Configuration and Functions

NO. NAME

1 CS I Chip Select

2 RD I Read

3 WR I Write

4 CLK IN I External Clock input or use internal clock gen with external RC elements

5 INTR O Interrupt request

6 VIN(+) I Differential analog input+

7 VIN(–) I Differential analog input–

8 A GND I Analog ground pin

9 VREF/2 I Reference voltage input for adjustment to correct full scale reading

10 D GND I Digital ground pin

11 DB7 O Data bit 7

12 DB6 O Data bit 6

13 DB5 O Data bit 5

14 DB4 O Data bit 4

15 DB3 O Data bit 3

16 DB2 O Data bit 2

17 DB1 O Data bit 1

18 DB0 (LSB) O Data bit 0

19 CLK R I RC timing resistor input pin for internal clock gen

20 VCC (or VREF) I +5V supply voltage, also upper reference input to the ladder

ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 SNOSBI1C – NOVEMBER 2009– REVISED JUNE 2015 www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Supply voltage (VCC)(3) 6.5 V Logic control inputs –0.3 18 Voltage V At other input and outputs –0.3 (VCC +0.3) Dual-In-Line Package (plastic 260 Lead Temperature Dual-In-Line Package (ceramic) 300 (Soldering, 10 Surface Mount Package Vapor Phase (60 seconds) 215 °Cseconds) Infrared (15 seconds) 220 Storage Temperature –65 150 Package Dissipation at TA = 25°C 875 mW (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, contact the Sales Office/Distributors for availability and specifications. (3) A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±800 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC 4.5 5 5.5 V Analog Input Voltage GND – 0.05 VCC + 0.05 VDC

6.4 Thermal Information

ADC080x ADC0802, ADC0804 THERMAL METRIC(1) UNITNFH (PDIP) DW (SOIC)

20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 38.5 63.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 23.4 27.2 °C/W RθJB Junction-to-board thermal resistance 19.5 31.8 °C/W ψJT Junction-to-top characterization parameter 8.7 5.7 °C/W ψJB Junction-to-board characterization parameter 19.4 31.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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6.5 Operating Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2). MIN MAX UNIT ADC0804LCJ –40 85 ADC0801/02/03/05LCN –40 85 Temperature °C ADC0804LCN 0 70 ADC0802/04LCWM 0 70 Range of VCC 4.5 6.3 VDC (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. (2) All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND.

6.6 Electrical Characteristics

The following specifications apply for VCC = 5 VDC, TMIN ≤ TA ≤ TMAX and fCLK = 640 kHz (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC0801: Total Adjusted Error(1) With Full-Scale Adj. (See Full-Scale) ±1/4 ADC0802: Total Unadjusted VREF/2=2.500 VDC ±1/2Error(1) ADC0803: Total Adjusted Error(1) With Full-Scale Adj. (See Full-Scale) ±1/2 LSB ADC0804: Total Unadjusted Error VREF/2=2.500 VDC ±1(1) ADC0805: Total Unadjusted Error VREF/2-No Connection ±1(1) ADC0801/02/03/05 2.5 8 VREF/2 Input Resistance (Pin 9) kΩ ADC0804 (2) 0.75 1.1 Analog Input Voltage Range V(+) or V(–)(3) GND–0.05 VCC+0.05 VDC DC Common-Mode Error Over Analog Input Voltage Range ±1/16 ±1/8 LSB VCC=5 VDC ±10% Over Allowed VIN(+) and VIN(–)Power Supply Sensitivity ±1/16 ±1/8 LSBVoltage Range(3) (1) None of these ADCs requires a zero adjust (see Zero Error). To obtain zero code at other analog input voltages see Errors and Reference Voltage Adjustments. (2) The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ. (3) For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.

6.7 AC Electrical Characteristics

The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCLK = 640 kHz(1) 103 114 µs TC Conversion Time See (2)(1) 66 73 1/fCLK Clock Frequency 100 640 1460 kHz fCLK VCC = 5V(2) Clock Duty Cycle 40% 60% INTR tied to WR with CS = 0 VDC,CR Conversion Rate in Free-Running Mode 8770 9708 conv/sfCLK = 640 kHz (1) Accuracy is specified at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. (2) With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched. Refer to Detailed Description. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 SNOSBI1C – NOVEMBER 2009– REVISED JUNE 2015 www.ti.com The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tW(WR) Width of WR Input (Start Pulse Width) CS = 0 VDC (3) 100 L Access Time (Delay from Falling Edge of RD totACC CL = 100 pF 135 200Output Data Valid) ns t1H, Tri-State Control (Delay from Rising Edge of RD CL = 10 pF, RL = 10k (See Tri-State 125 200t0H to Hi-Z State) Test Circuits and Waveforms) Delay from Falling Edge of WR or RD to ResettWI, tRI 300 450of INTR CIN Input Capacitance of Logic Control Inputs 5 7.5 pF COUT Tri-State Output Capacitance (Data Buffers) 5 7.5 CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical “1”Input Voltage (Except Pin 4 CLK IN) VCC = 5.25 VDC 2 15 VDC VIN (0) Logical “0”Input Voltage (Except Pin 4 CLK IN) VCC = 4.75 VDC 0.8 IIN (1) Logical “1”Input Current (All Inputs) VIN = 5 VDC 0.005 1 µADC IIN (0) Logical “0”Input Current (All Inputs) VIN = 0 VDC –1 –0.005 CLOCK IN AND CLOCK R VT+ CLK IN (Pin 4) Positive Going Threshold Voltage 2.7 3.1 3.5 CLK IN (Pin 4) Negative Going ThresholdVT− 1.5 1.8 2.1Voltage VH CLK IN (Pin 4) Hysteresis (VT+)–(VT−) 0.6 1.3 2 VDC VOUT Logical “0”CLK R Output Voltage IO = 360 µA, VCC = 4.75 VDC 0.4(0) VOUT Logical “1”CLK R Output Voltage IO = −360 µA, VCC = 4.75 VDC 2.4(1) DATA OUTPUTS AND INTR Data Outputs IOUT = 1.6 mA, VCC = 4.75 VDC 0.4VOUT Logical “0”Output (0) Voltage INTR Output IOUT = 1.0 mA, VCC = 4.75 VDC 0.4 VDC IO = −360 µA, VCC = 4.75 VDC 2.4VOUT Logical “1”Output Voltage(1) IO = −10 µA, VCC = 4.75 VDC 4.5 VOUT = 0 VDC –3Tri-State Disabled Output Leakage (All DataIOUT µADCBuffers) VOUT = 5 VDC 3 ISOURC VOUT Short to GND, TA = 2 5°C 4.5 6 E mADC ISINK VOUT Short to VCC, TA = 25°C 9 16 POWER SUPPLY Supply Current ADC0801/02/03/04LCJ/05 1.1 1.8fCLK = 640 kHz, VREF/2 = NC,ICC (Includes Ladder mATA = 25°C and CS = 5 VADC0804LCN/LCWM 1.9 2.5Current) (3) The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse.

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6.8 Typical Characteristics

Figure 4. Delay From Falling Edge of RD to Output DataFigure 3. Logic Input Threshold Voltage vs Supply Voltage Figure 5. CLK IN Schmitt Trip Levels vs Supply Voltage Figure 6. fCLK vs Clock Capacitor Figure 7. Full-Scale Error vs Conversion Time Figure 8. Effect of Unadjusted Offset Error vs VREF/2 Voltage

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7 Parameter Measurement Information

7.1 Tri-State Test Circuits and Waveforms

Figure 12. RD to Data Output Falling Edge Test Figure 13. RD to Data Output Falling Edge Test Figure 14. RD to Data Output Rising Edge Test Figure 15. RD to Data Output Rising Edge Test

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8 Detailed Description

8.1 Overview

The ADC0801 series are versatile 8-Bit µP compatible general purpose ADC converters operate on single 5-V supply. These devices are treated as a memory location or I/O port to a micro-processor system without additional interface logic. The outputs are Tri-state latched which facilitate interfacing to micro-processor control bus. The converter is designed with a differential potentiometric ladder, a circuit equivalent of the 256R network. It contains analog switches sequenced by successive approximation logic. A functional diagram of the ADC converter is shown in Functional Block Diagram. All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines. The differential analog voltage input has good common mode-rejection and permits offsetting the analog zero-input voltage value. Moreover, the input reference voltage can be adjusted to allow encoding small analog voltage span to the full 8-bits resolution. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. Using a SAR logic the most significant bit is tested first and after 8 comparisons (64 clock cycles) a digital 8-bit binary code (1111 1111 = full-scale) is transferred to an output latch and then an interrupt is asserted (INTR makes a high-to-low transition). A conversion in process can be interrupted by issuing a second start command. The device may be operated in the free-running mode by connecting INTR to the WR input with CS=0. On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. As long as the CS input and WR input remain low, the ADC will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low-to-high transition. The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q output of F/F1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 8-bit shift register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would momentarily be at a “1”level) and the 8-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F/F. After the “1” is clocked through the 8-bit shift register (which completes the SAR search) it appears as the input to the D-type latch, LATCH 1. As soon as this “1”is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Tri-state output latches. When LATCH 1 is subsequently enabled, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR input signal. Note this SET control of the INTR F/F remains low for 8 of the external clock periods (as the internal clocks run at 1/8 of the frequency of the external clock). If the data output is continuously enabled (CS and RD both held low), the INTR output will still signal the end of conversion (by a high-to-low transition), because the SET input can control the Q output of the INTR F/F even though the RESET input is constantly at a M "1M " level in this operating mode. This INTR output will therefore stay low for the duration of the SET signal, which is 8 periods of the external clock frequency (assuming the ADC is not started during this interval). When operating in the free-running or continuous conversion mode (INTR pin tied to WR and CS wired low – see Continuous Conversions), the START F/F is SET by the high-to-low transition of the INTR signal. This resets the SHIFT REGISTER which causes the input to the D-type latch, LATCH 1, to go low. As the latch enable input is still present, the Q output will go high, which then allows the INTR F/F to be RESET. This reduces the width of the resulting INTR output pulse to only a few propagation delays (approximately 300 ns). When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the Tri-state output latches will be enabled to provide the 8-bit digital outputs. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

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8.2 Functional Block Diagram

(1) CS shown twice for clarity. (2) SAR = Successive Approximation Register.

8.3 Feature Description

8.3.1 Understanding ADC Error Specs

A perfect ADC transfer characteristic (staircase waveform) is shown in Figure 16 and Figure 17. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digital output codes that correspond to these inputs are shown as D−1, D, and D+1. For the perfect ADC, not only will center- value (A−1, A, A+1, . . . . ) analog inputs produce the cor- rect output digital codes, but also each riser (the transitions between adjacent output codes) will be located ±1⁄2 LSB away from each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided for a range of analog input voltages that extend ±1⁄2 LSB from the ideal center-values. Each tread (the range of analog input voltage that provides the same digital output code) is therefore 1 LSB wide. Figure 19 shows a worst case error plot for the ADC0801. All center-valued inputs are guaranteed to produce the correct output codes and the adjacent risers are specified to be no closer to the center-value points than ±1/4 LSB. In other words, if we apply an analog input equal to the center-value ±1/4 LSB, we guarantee that the ADC will produce the correct digital code. The maximum range of the position of the code transition is indicated by the horizontal arrow and it is specified to be no more than 1/2 LSB. The error curve of Figure 21 shows a worst case error plot for the ADC0802. Here we guarantee that if we apply an analog input equal to the LSB analog voltage center-value the ADC will produce the correct digital code.

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8.3.2 Digital Control Inputs

8.4 Device Functional Modes

8.4.1 Analog Input Modes

8.4.1.1 Normal Mode

stray capacitance to ground as shown in Figure 22. Figure 22. Analog Input Impedance is strobed at the end of the clock period.

8.4.1.2 Fault Mode

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The following sections give example circuits and suggestions for using the ADC080X in typical application situation with a typical 8-bit micro-processor.

9.1.1 Testing the ADC Converter

There are many degrees of complexity associated with testing an ADC converter. One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Figure 23. For ease of testing, the VREF/2 (pin 9) should be supplied with 2.560 VDC and a VCC supply voltage of 5.12 VDC should be used. This provides an LSB value of 20 mV. If a full-scale adjustment is to be made, an analog input voltage of 5.090 VDC (5.120–1/⁄2 LSB) should be applied to the VIN(+) pin with the VIN(−) pin grounded. The value of the VREF/2 input voltage should then be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111. This value of VREF/2 should then be used for all the tests. The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters, the 4 most significant (MS) and the 4 least significant (LS). Table 1 shows the fractional binary equivalent of these two 4-bit groups. By adding the voltages obtained from the "VM" and "VLS" columns in Table 1, the nominal value of the digital display (when VREF/2 = 2.560V) can be determined. For example, for an output LED display of 1011 0110 or B6 (in hex), the voltage values from the table are 3.520 + 0.120 or 3.640 VDC. These voltage values represent the center-values of a perfect ADC converter. The effects of quantization error have to be accounted for in the interpretation of the test results. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

Figure 23. Basic ADC Tester can be expressed as either analog voltages or differences in 2 digital words. A basic ADC tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 35. and an X-Y plotter can be used to provide analog error (Y axis) versus analog input (X axis). can be increased by establishing internal limits on the allowed error for each code.

9.1.2 Microprocessor Interfacing

To discuss the interface with 8080A and 6800 microprocessors, a common sample subroutine structure is used.

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9.1.2.1 Interfacing 8080 Microprocessor Derivatives (8048, 8085)

the ADC should be mapped into memory space. An example of an ADC in I/O space is shown in Figure 26. Figure 24. ADC Tester with Analog Error Output Figure 25. Basic “Digital” ADC Tester Table 1. Decoding the Digital Output LEDs

Table 1. Decoding the Digital Output LEDs (continued) interrupt is acknowledged as required by the accompanying sample program. Figure 26. ADC0801_INS8080A CPU Interface

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Note: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack. Note: All address used were arbitrarily chosen. Figure 27. Sample Program for Figure 26 ADC0801–INS8080A CPU Interface PCB and/or must drive capacitive loads larger than 100 pF.

9.1.2.2 Sample 8080A CPU Interfacing Circuitry and Program

the appropriate CS for the converter.

9.1.2.3 INS8048 Interface

Figure 28. INS8048 Interface Figure 29. Sample Program for Figure 28 INS8048 Interface

9.1.2.4 Interfacing the Z-80

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9.2 Typical Applications

Figure 31. Generic Interface Between ADC and 8-Bit µPs

9.2.1.1 Design Requirements

dynamic voltage range of the analog input voltage is also depicted.

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Table 2. Design Parameters

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Analog Differential Voltage Inputs and Common-Mode Rejection

∆Ve is the error voltage due to sampling delay
VP is the peak value of the common-mode voltage
fcm is the common-mode frequency (1) As an example, to keep this error to 1/4 LSB (∼5 mV) when operating with a 60 Hz common-mode frequency, fcm, and using a 640 kHz ADC clock, fCLK, would allow a peak value of the common-mode voltage, VP, which is given by: (2) or (3) which gives VP–1.9 V. The allowed range of analog input voltages usually places more severe restrictions on input common-mode noise levels. An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making use of the differential input (see Reference Voltage).

9.2.1.2.2 Analog Inputs — Input Current

are placed outside the feedback loop — from the output of an op amp, if used. and input bypass capacitor in place.

9.2.1.2.3 Reference Voltage

adjusted voltage reference. This has been achieved in the design of the IC as shown in Figure 32. Figure 32. The VREFERENCE Design on the IC

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the full-scale differential input voltage twice the voltage at pin 9. 0°C≤TA≤+70°C. Other temperature range parts are also available. Figure 33. Analog Input Signal Example

*Add if VREF/2 ≤ 1 VDC with LM358 to draw 3 mA to ground. Figure 34. Accommodating an Analog Input from 0.5V (Digital Out = 00HEX) to 3.5 V (Digital Out=FFHEX)

9.2.1.2.4 Errors and Reference Voltage Adjustments

differential mode operation of the ADC. transition from 0000 0000 to 0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8 mV for VREF/2=2.500 VDC). supply if pin 9 is not used) for a digital output code that is just changing from 1111 1110 to 1111 1111.

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obtain the 00HEX to 01HEX code transition.

VMAX = The high end of the analog input range
VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.) (4) The VREF/2 (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure

9.2.1.2.5 Clocking Option

clocking. The CLK IN (pin 4) makes use of a Schmitt trigger as shown in Figure 35. Figure 35. Self-Clocking the ADC should be used to minimize the loading on the clock R pin (do not use a standard TTL buffer).

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9.2.1.2.6 Restart During a Conversion

If the ADC is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a new conversion is started. The output data latch is not updated if the conversion in process is not allowed to be completed, therefore the data of the previous conversion remains in this latch. The INTR output simply remains at the “1”level.

9.2.1.2.7 Continuous Conversions

For operation in the free-running mode an initializing pulse should be used, following power up, to ensure circuit operation. In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and INTR node should be momentarily forced to logic low following a power-up cycle to ensure operation.

9.2.1.2.8 Driving the Data Bus

This MOS ADC, like MOS microprocessors and memories, will require a bus driver when the total capacitance of the data bus gets large. Other circuitry, which is tied to the data bus, will add to the total capacitive loading, even in Tri-state (high impedance mode). Backplane bussing also greatly adds to the stray capacitance of the data bus. There are some alternatives available to the designer to handle this problem. Basically, the capacitive loading of the data bus slows down the response time, even though DC specifications are still met. For systems operating with a relatively slow CPU clock frequency, more time is available in which to establish proper logic levels on the bus and therefore higher capacitive loads can be driven (see typical characteristics curves). At higher CPU clock frequencies time can be extended for I/O reads (and/or writes) by inserting wait states (8080) or using clock extending circuits (6800). Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be Tri-state buffers (low power Schottky such as the DM74LS240 series is recommended) or special higher drive current products which are designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended.

9.2.1.2.9 Wiring and Hook-Up Precautions

Standard digital wire wrap sockets are not satisfactory for breadboarding this ADC converter. Sockets on PCBs can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and hum pickup, therefore shielded leads may be necessary in many applications. A single point analog ground that is separate from the logic ground points should be used. The power supply bypass capacitor and the self-clocking capacitor (if used) should both be returned to digital ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero errors in excess of 1/4 LSB can usually be traced to improper board layout and wiring (see Zero Error for measuring the zero error).

9.2.2 Multiple ADC0801 Series to MC6800 CPU Interface

To transfer analog data from several channels to a single microprocessor system, a multiple converter scheme presents several advantages over the conventional multiplexer single-converter approach. With the ADC0801 series, the differential inputs allow individual span adjustment for each channel. Furthermore, all analog input channels are sensed simultaneously, which essentially divides the total system servicing time of the microprocessor by the number of channels, because all conversions occur simultaneously. This scheme is shown in Figure 40.

28 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

Figure 38. ADC0801–MC6820 PIA Interface Figure 39. Sample Program for Figure 38 ADC0801–MC6820 PIA Interface derived from just one RC pair on the first converter. This output drives the other ADCs.

30 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

all ADCs have completed their conversion before the microprocessor is interrupted. recover the original data they had before servicing DATA IN.

9.2.3 Auto-Zeroed Differential Transducer Amplifier and ADC Converter

required to take advantage of the full ADC converter input dynamic range. *Numbers in parentheses refer to MC6800 CPU pin out. **Numbers of letters in brackets refer to standard M6800 system common bus code. Figure 40. Interfacing Multiple ADCs in an MC6800 System

Figure 41. Sample Program for Figure 40 Interfacing Multiple ADC’s in an MC6800 System Figure 42. Sample Program for Figure 40 Interfacing Multiple ADC’s in an MC6800 System dimensioned in the user’s program. voltage error for this preamp is only 50 µV for /⁄4 LSB error. This would obviously require very precise amplifiers.

Switches are LMC13334 CMOS analog switches. The 9 resistors used in the auto-zero section can be ±5% tolerance. Figure 43. Gain of 100 Differential Transducer Preamp

IX is the current through resistor RX (5) All of the offset error terms can be cancelled by making ±IXRX= VOS1 + VOS3 − VOS2. This is the principle of this auto-zeroing scheme. The INS8080A uses the 3 I/O ports of an INS8255 Programable Peripheral Interface (PPI) to control the auto zeroing and input data from the ADC0801 as shown in Figure 44. The PPI is programmed for basic I/O operation (mode 0) with Port A being an input port and Ports B and C being output ports. Two bits of Port C are used to alternately open or close the 2 switches at the input of the preamp. Switch SW1 is closed to force the preamp’s differential input to be zero during the zeroing subroutine and then opened and SW2 is then closed for conversion of the actual differential input signal. Using 2 switches in this manner eliminates concern for the ON resistance of the switches as they must conduct only the input bias current of the input amplifiers. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

source current into node VX thus raising the voltage at VX and making the output differential more negative. with a stable 5V source. Buffer amplifier A1 is necessary so that it can source or sink the D/A output current. Figure 44. Microprocessor Interface Circuitry for Differential Preamp the I/O ports are buffered with inverting gates. continues for 8 approximations and the differential output eventually converges to within 5 mV of zero.

ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1C – NOVEMBER 2009– REVISED JUNE 2015

Port A and the ADC0801 are at port address E4
Port B is at port address E5
Port C is at port address E6
PPI control word port is at port address E7
Program Counter automatically goes to ADDR:3C3D upon acknowledgment of an interrupt from the ADC0801

9.2.4 Multiple ADC Converters in a Z-80 Interrupt Driven Mode

In data acquisition systems where more than one ADC converter (or other peripheral device) will be interrupting pro- gram execution of a microprocessor, there is obviously a need for the CPU to determine which device requires servicing. Figure 47 and the accompanying software is a method of determining which of 7 ADC0801 converters has completed a conversion (INTR asserted) and is requesting an interrupt. This circuit allows starting the ADC converters in any sequence, but will input and store valid data from the converters with a priority sequence of ADC 1 being read first, ADC 2 second, etc., through ADC 7 which would have the lowest priority for data being read. Only the converters whose INT is asserted will be read. The key to decoding circuitry is the DM74LS373, 8-bit D type flip-flop. When the Z-80 acknowledges the interrupt, the program is vectored to a data input Z-80 subroutine. This subroutine will read a peripheral status word from the DM74LS373 which contains the logic state of the INTR outputs of all the converters. Each converter which initiates an interrupt will place a logic "0" in a unique bit position in the status word and the subroutine will determine the identity of the converter and execute a data read. An identifier word (which indicates which ADC the data came from) is stored in the next sequential memory location above the location of the data so the program can keep track of the identity of the data entered. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

Figure 45. Flow Chart for Auto-Zero Routine

NOTE: All numerical values are hexadecimal representations. Figure 46. Software for Auto-Zeroed Differential ADC

It is assumed that the CPU automatically performs a RST 7 instruction when a valid interrupt is acknowledged (CPU is in interrupt mode 1). Hence, the subroutine starting address of X0038.
The address bus from the Z-80 and the data bus to the Z-80 are assumed to be inverted by bus drivers.
ADC data and identifying words will be stored in sequential memory locations starting at the arbitrarily chosen address X 3E00.
The stack pointer must be dimensioned in the main program as the RST 7 instruction automatically pushes the PC onto the stack and the subroutine uses an additional 6 stack addresses.
The peripherals of concern are mapped into I/O space with the following port assignments:

Table 3. Port Assignment Where Peripherals are Mapped into I/O Space

00 MM74C374 8-bit flip-flop 04 ADC 4

01 ADC 1 05 ADC 5

Table 3. Port Assignment Where Peripherals are Mapped into I/O Space (continued)

02 ADC 2 06 ADC 6

03 ADC 3 07 ADC 7

This port address also serves as the ADC identifying word in the program. Figure 47. Multiple ADCs With Z-80 Type Microprocessor

ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 www.ti.com SNOSBI1C – NOVEMBER 2009– REVISED JUNE 2015 Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

9.3 System Examples

Figure 48. 6800 Interface Figure 49. Absolute With a 2.5-V Reference Figure 50. Ratiometeric With Full-Scale Adjust Figure 51. Absolute With a 5-V Reference

Figure 56. 1-mV Resolution With µP-Controlled Figure 57. Digitizing a Current Flow

Use a large R value to reduce loading at CLK R output.

Figure 58. Self-Clocking Multiple ADCs Figure 59. Self-Clocking in Free-Running Mode

within the dotted area if hysteresis is not needed. Figure 64. µP-Compatible Differential-Input Figure 65. Handling ±10-V Analog Inputs can be calibrated with a pre-set input voltage. Figure 66. Low-Cost, µP-Interfaced, Temperature- Figure 67. µP-Interfaced Temperature-to-Digital

Figure 72. Analog Self-Test for a System Figure 73. A Low-Cost, 3-Decade Logarithmic Figure 74. 3-Decade Logarithmic ADC Converter Figure 75. Noise Filtering the Analog Input

ADC0801,ADC0802,ADC0803,ADC0804,ADC0805 SNOSBI1C – NOVEMBER 2009– REVISED JUNE 2015 www.ti.com

10 Power Supply Recommendations

Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a test socket as an unlimited current surge through the resulting forward diode within the device could cause fusing of the internal conductors and result in a destroyed unit. Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A low-inductance, low-ESR tantalum bypass capacitor should be used close to the converter VCC pin, and a 10-µF is recommended. If an unregulated voltage is available in the system, a separate 5-V voltage regulator for the converter (and other analog circuitry) will greatly reduce digital noise on the VCC supply.

11 Layout

11.1 Layout Guidelines

All logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and 60-Hz pickup. Shielded leads for the analog inputs may be required in sensitive applications. A single-point analog ground should be used that is also separated from the logic ground points. The power supply bypass capacitor should be returned to digital ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero errors in excess of 1/4 LSB is generally traceable to improper PCB layout and/or wiring. To minimize potential offset issues, TI recommends to route the signal traces differentially next to each other so that they will see the same thermal gradients and the same number of feedthroughs. Furthermore, inductance is determined by the size of the loop of current. Providing a path for return currents next to the signal trace will reduce the inductance. A solid ground plane is very advantageous in this regard. Ensure to minimize the loop area formed by the bypass capacitor connection between VCC and ground. The ground pin should be connected to the PCB ground plane at the pin of the device.

Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805

12 Device and Documentation Support

12.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 4. Related Links

12.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 25-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ADC0802LCN LIFEBUY PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0802LCN ADC0802LCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 ADC0802LCN ADC0802LCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 ADC0802 LCWM ADC0803LCN LIFEBUY PDIP NFH 20 18 TBD Call TI Call TI -40 to 85 ADC0803LCN ADC0803LCN/NOPB ACTIVE PDIP NFH 20 18 Pb-Free (RoHS) CU SN Level-1-NA-UNLIM -40 to 85 ADC0803LCN ADC0804LCN NRND PDIP NFH 20 18 TBD Call TI Call TI 0 to 70 ADC0804LCN ADC0804LCN/NOPB ACTIVE PDIP NFH 20 18 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 ADC0804LCN ADC0804LCWM NRND SOIC DW 20 36 TBD Call TI Call TI 0 to 70 ADC0804 LCWM ADC0804LCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 ADC0804 LCWM ADC0804LCWMX NRND SOIC DW 20 1000 TBD Call TI Call TI 0 to 70 ADC0804 LCWM ADC0804LCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 ADC0804 LCWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 25-Dec-2015 Addendum-Page 2 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC0804LCWMX SOIC DW 20 1000 367.0 367.0 45.0 ADC0804LCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2015 Pack Materials-Page 2

www.ti.com N20A (Rev G)

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Product Information

ADC0803-N specifications and overview.

Summary

Analog-to-Digital Converters

Description

Analog-to-Digital Converters

Source title ADC0803-N Datasheet(PDF) - Texas Instruments

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