ADC0801S040TS | DigiCamel IC Datasheet

Online Datasheet

Read ADC0801S040TS online.

ADC0801S040 IDT | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 18

Technical content

Single 8 bits ADC, up to 40 MHz Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC0801S040 is an 8-bit universal analog-to-digital converter (ADC) for video and general purpose applications. It converts the analog input signal from 2.7 V to 5.5 V into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/Transistor-Transistor Logic (TTL) compatible. A sleep mode allows reduction of the device power consumption to 4 mW. 2. Features  8-bit resolution  Oper ation between 2.7 V and 5.5 V  Sa mpling rate up to 40 MHz  DC sampling allowed  High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz)  CMOS/TT L compatible digital inputs and outputs  Exte rnal reference voltage regulator  Power dissip ation only 30 mW (typical value)  L ow analog input capacitance, no buffer amplifier required  Slee p mode (4 mW)  No samp le-and-hold circuit required 3. Applications  Video data digitizing  Came ra  Camcorder  Rad io communication  Car alarm system

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 3 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz 6. Block diagram Rlad RB RM RT VI VDDD VDDA CMOS OUTPUTSLATCHES CLOCK DRIVER 014aaa495 CLK SLEEP ADC0801S040

20 VDDO

analog ground digital ground VSSD VSSO output ground analog voltage input data outputs LSB MSB 19 D7 18 D6 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0 ANALOG - TO - DIGITAL CONVERTER Fig 1. Block diagram

7.1 Pinning

7.2 Pin description

Table 3. Pin description

3ADC0801S040_3 © IDT 2012. All rights reserved. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). the supply voltage VDD remains as indicated. Table 5. Thermal characteristics Table 3. Pin description …continued Table 6. Characteristics = 1.84 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified.

3ADC0801S040_3 © IDT 2012. All rights reserved. to code 255 at Tamb = 25 C. resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. parallel and fed with the same reference source, the matching between each of them is optimized. than 2 LSB, nor any significant attenuation is observed in the reconstructed signal. wave signal) in order to sample the signal and obtain correct output data. signal-to-noise ratio: S/N = ENOB  6.02 + 1.76 dB. [7] Measurement carried out using video analyzer VM700A, wher e video analog signal is r econstructed through a DAC. [8] Output data acquisition: the output data is available af ter the maximum delay time of td(o). = 1.84 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified.

Additional information relating to Table 6

Table 7. Output coding and input voltage (typical values; referenced to V SSA) Table 8. Mode selection

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 10 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz sample N + 1sample N CLK 014aaa508 sample N + 2 sample N + 1sample N sample N + 2 50 % VI DATA D0 to D7 VDDO 0 V 50 %DATA N + 1 DATA N DATA N − 1 DATA N − 2 td(o) tw(clk)H tw(clk)L td(s) th(o) Fig 4. Timing diagram

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 11 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz LOW HIGH HIGH LOW ADC0801S040 VDDD VDDD SLEEP SLEEP output data output data 10 % 50 % 50 % 90 % 50 % tdLZ tdZL tdHZ tdZH 20 pF 3.3 kΩ S1TEST VDDDtdLZ VDDDtdZL GNDtdZH tdHZ GND 014aaa496 frequency on pin SLEEP = 100 kHz. Fig 5. Timing diagram and test condit ions of 3-state output delay time 014aaa501 −0.047 0.065 −0.160 0.178 0.291 A (LSB) −0.272 codes 0 27220468 136 Fig 6. Typical Integral Non-Linearity (INL) performance

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 12 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz 014aaa502 −0.025 0.032 −0.84 0.091 0.150 A (LSB) −0.143 codes 0 27220468 136 Fig 7. Typical Differential Non-Linearity (DNL) performance 014aaa497 code 255 code 0 50 % 50 %CLK VI ts(LH) ts(HL) 50 % 50 % 5 ns 5 ns 2 ns 2 ns Fig 8. Analog input se ttling-time diagram

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 13 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz f (MHz) 0 20.015.05.0 10.0 014aaa503 −80 −40 A (dB) −120 Effective bits: 7.32; THD = 51.08 dB. Fig 9. Typical fast Fourier transform (f clk = 40 MHz; fi = 4.43 MHz) 014aaa498 VDDO D7 to D0 VSSO VDDA VI VSSA 014aaa505 Fig 10. CMOS data outputs Fig 11. VI analog input 014aaa499 VDDO VSSO SLEEP VDDA RT RM RB VSSA 014aaa506 RL RL RL RL Fig 12. SLEEP 3-state input Fig 13. RB, RM and RT inputs

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 14 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz VDDD CLK 1/2 VDDD VSSD 014aaa507 Fig 14. CLK input

12.1 Application diagrams

RB(1) RM(1) VI RT(1) VDDO VSSO 10 11 ADC0801S040 014aaa500 The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) RB, RM, RT are decoupled to VSSA. Fig 15. Application diagram

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 16 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz 13. Package outline UNIT A1 A2 A3 bp cD (1) E(1) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 1.4 1.2 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 1 0.26.6 6.2 0.65 0.45 0.48 0.18 o o0.13 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 SOT266-1 MO-152 99-12-27 03-02-19 w M θ A bp D HE Lp Q detail X E Z e c L v M A X (A )3 A y 0.25 11 0 20 11 pin 1 index 0 2.5 5 mm scale SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 A max. 1.5 Fig 16. Package outline SOT266-1 (SSOP20)

3ADC0801S040_3 © IDT 2012. All rights reserved. Table 9. Revision history Modifications: Corrections made to table notes in Figure• 1. Corrections made to Table• 3. Corrections made to symbol in Table• 4. Corrections made to Table• 6.

3ADC0801S040_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 18 of 18 Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz 16. Contents 11 Additional informa tion relating to Table 6 . . . 9

Product Information

ADC0801S040TS specifications and overview.

Summary

Single 8 bits ADC, up to 40 MHz

Description

Single 8 bits ADC, up to 40 MHz

Source title ADC0801S040TS Datasheet(PDF) - Integrated Device Technology

Related Parts

More parts from the same family.

Browse manufacturer