ADC0800PCD

ADC0800 NSC | Alldatasheet

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Technical content

Features

Y g5V, 10V input ranges Y No missing codes Y Ratiometric conversion Y TRI-STATE outputs Y Fast T Ce50 ms Y Contains output latches Y TTL compatible Y Supply voltages 5 V DC and b12 V DC Y Resolution 8 bits Y Linearity g1 LSB Y Conversion speed 40 clock periods Y Clock range 50 to 800 kHz Block Diagram TL/H/5670–1 (00000000ea full-scale) TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V DD)V SSb22V Supply Voltage (V GG)V SSb22V Voltage at Any Input V SSa0.3V to V SSb22V Input Current at Any Pin (Note 2) 5 mA Package Input Current (Note 2) 20 mA Power Dissipation (Note 3) 875 mW ESD Susceptibility (Note 4) 500V Storage Temperature 150 Lead Temperature (Soldering, 10 sec.) 300 §C Operating Ratings (Note 1) Temperature Range T MIN s TA s TMAX ADC0800PD b55§C s TA s a125§C ADC0800PCD 0 §C s TA s a70§C

Electrical Characteristics

These specifications apply for V SSe5.0 V DC,V GGeb12.0 V DC,V DDe0V DC, a reference voltage of 10.000 V DC across the on-chip R-network (V R-NETWORK TOP e5.000 V DC and V R-NETWORK BOTTOM eb5.000 V DC), and a clock frequency of 800 kHz. For all tests, a 475 X resistor is used from pin 5 to V R-NETWORK BOTTOM eb 5V DC. Unless otherwise noted, these specifications apply over an ambient temperature range of b55§Ct o a125§C for the ADC0800PD and 0 §Ct o a70§C for the ADC0800PCD. Parameter Conditions Min Typ Max Units Non-Linearity T Ae25§C, (Note 8) g1 LSB Over Temperature, (Note 8) g2 LSB Differential Non-Linearity g(/2 LSB Zero Error g2 LSB Zero Error Temperature Coefficient (Note 9) 0.01 %/ §C Full-Scale Error g2 LSB Full-Scale Error Temperature Coefficient (Note 9) 0.01 %/ §C Input Leakage 1 mA Logical ‘‘1’’ Input Voltage All Inputs V SSb1.0 V SS V Logical ‘‘0’’ Input Voltage All Inputs V GG VSSb4.2 V Logical Input Leakage T Ae25§C, All Inputs, V ILe 1 mA VSSb10V Logical ‘‘1’’ Output Voltage All Outputs, I OHe100 mA 2.4 V Logical ‘‘0’’ Output Voltage All Outputs, I OLe1.6 mA 0.4 V Disabled Output Leakage T Ae25§C, All Outputs, V OLe 2 mA VSS@10V Clock Frequency 0 §CsTAsa70§C 50 800 kHz b55§CsTAsa125§C 100 500 kHz Clock Pulse Duty Cycle 40 60 % TRI-STATE Enable/Disable Time 1 ms Start Conversion Pulse (Note 10) 1 3 (/2 Clock Periods Power Supply Current T Ae25§C2 0 m A Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: When the input voltage (V IN) at any pin exceeds the power supply rails (V IN k Vb or V IN l Va) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries wit ha5m A current limit to four. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX, iJA, and the ambient temperature, T A. The maximum allowable power dissipation at any temperature is P D e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T JMAX e 125§C, and the typical junction-to-ambient thermal resistance of the ADC0800PD and ADC0800PCD when board mounted is 66 §C/W. Note 4: Human body model, 100 pF discharged through a 1.5 k X resistor. Note 5: Typicals are at 25 §C and represent most likely parametric norm. Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 7: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 8: Non-linearity specifications are based on best straight line. Note 9: Guaranteed by design only. Note 10: Start conversion pulse duration greater than 3 (/2 clock periods will cause conversion errors.

TL/H/5670–2 Data is complementary binary (full scale is all ‘‘0’s’’ output). Application Hints OPERATION The ADC0800 contains a network with 256-300 X resistors in series. Analog switch taps are made at the junction of each resistor and at each end of the network. In operation, a reference (10.00V) is applied across this network of 256 resistors. An analog input (V IN) is first compared to the cen- ter point of the ladder via the appropriate switch. If V IN is larger than V REF/2, the internal logic changes the switch points and now compares V IN and */4 VREF. This process, known as successive approximation, continues until the best match of V IN and V REF/N is made. N now defines a specific tap on the resistor network. When the conversion is complete, the logic loads a binary word corresponding to this tap into the output latch and an end of conversion (EOC) logic level appears. The output latches hold this data valid until a new conversion is completed and new data is loaded into the latches. The data transfer occurs in about 200 ns so that valid data is present virtually all the time in the latches. The data outputs are activated when the Output Enable is high, and in TRI-STATE when Output Enable is low. The Enable Delay time is approximately 200 ns. Each conversion requires 40 clock periods. The device may be operated in the free running mode by connecting the Start Conversion line to the End of Conversion line. However, to ensure start-up under all possible conditions, an external Start Conversion pulse is required during power up condi- tions. REFERENCE The reference applied across the 256 resistor network de- termines the analog input range. V REFe10.00V with the top of the R-network connected to 5V and the bottom connect- ed to b5V gives a g5V range. The reference can be level shifted between V SS and V GG. However, the voltage, ap- plied to the top of the R-network (pin 15), must not exceed V SS, to prevent forward biasing the on-chip parasitic silicon diodes that exist between the P-diffused resistors (pin 15) and the N-type body (pin 10, V SS). Use of a standard logic power supply for V SS can cause problems, both due to initial voltage tolerance and changes over temperature. A solution is to power the V SS line (15 mA max drain) from the output of the op amp that is used to bias the top of the R-network (pin 15). The analog input voltage and the volt- age that is applied to the bottom of the R-network (pin 5) must be at least 7V above the bVGG supply voltage to ensure adequate voltage drive to the analog switches. Other reference voltages may be used (such as 10.24V). If a 5V reference is used, the analog range will be 5V and accu- racy will be reduced by a factor of 2. Thus, for maximum accuracy, it is desirable to operate with at least a 10V refer- ence. For TTL logic levels, this requires 5V and b5V for the R-network. CMOS can operate at the 10 V DC VSS level and a single 10 V DC reference can be used. All digital voltage levels for both inputs and outputs will be from ground to V SS. ANALOG INPUT AND SOURCE RESISTANCE CONSIDERATIONS The lead to the analog input (pin 12) should be kept as short as possible. Both noise and digital clock coupling to this input can cause conversion errors. To minimize any input errors, the following source resistance considerations should be noted: For R Ss5k No analog input bypass capacitor re- quired, although a 0.1 mF input bypass capacitor will prevent pickup due to un- avoidable series lead inductance. For 5k kRSs20k A 0.1 mF capacitor from the input (pin 12) to ground should be used. For R Sl20k Input buffering is necessary. If the overall converter system requires lowpass filtering of the analog input signal, use a 20 k X or less series resistor for a passive RC section or add an op amp RC active low- pass filter (with its inherent low output resistance) to ensure accurate conversions. CLOCK COUPLING The clock lead should be kept away from the analog input line to reduce coupling. LOGIC INPUTS The logical ‘‘1’’ input voltage swing for the Clock, Start Con- version and Output Enable should be (V SSb1.0V).

Application Hints (Continued) ZERO AND FULL-SCALE ADJUSTMENT Zero Adjustment: This is the offset voltage required at the bottom of the R-network (pin 5) to make the 11111111 to 11111110 transition when the input voltage is (/2 LSB (20 mV for a 10.24V scale). In most cases, this can be accom- plished by havin ga1k X pot on pin 5. A resistor of 475 X can be used as a non-adjustable best approximation from pin 5 to ground. Full-Scale Adjustment: This is the offset voltage required at the top of the R-network (pin 15) to make the 00000001 to 00000000 transition when the input voltage is 1 (/2 LSB from full-scale (60 mV less than full-scale for a 10.24V scale). This voltage is guaranteed to be within g2 LSB for the ADC0800 without adjustment. In most cases, adjust- ment can be accomplished by having a 1 k X pot on pin 15. Typical Applications General Connection TL/H/5670–11 Hi-Voltage CMOS Output Levels 0V to 10V V IN range 0V to 10V output levels TL/H/5670–12 Ratiometric Input Signal with Tracking Reference TL/H/5670–4

Typical Applications (Continued) VREFe10 V DC With TTL Logic Levels *See application hints TL/H/5670–13A1 and A2 eLM358N dual op amp VREFe10 V DC With 10V CMOS Logic Levels *See application hints TL/H/5670–14 Input Level Shifting TL/H/5670–5 # Permits TTL compatible outputs with 0V to 10V input range (0V to b10V input range achieved by reversing polarity of zener diodes and returning the 6.8k resistor to V b).

ADC0800 8-Bit A/D Converter Physical Dimensions inches (millimeters) Hermetic Dual-In-Line Package (D) Order Number ADC0800PD or ADC0800PCD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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