ADC07D1520NOPB

ADC07D1520_12 TI1 | Alldatasheet

Document overview

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Technical content

Features

• Single +1.9V ±0.1V Operation
• Interleave Mode for 2x Sample Rate
• Multiple ADC Synchronization Capability
• Adjustment of Input Full-Scale Range, Clock Phase, and Offset
• Choice of SDR or DDR Output Clocking
• 1:1 or 1:2 Selectable Output Demux
• Second DCLK Output
• Duty Cycle Corrected Sample Clock
• Test pattern Key Specifications
• Resolution 7 Bits
• Max Conversion Rate 1.5 GSPS (max)
• Code Error Rate 10-18 (typ)
• ENOB @ 748 MHz Input 6.8 Bits (typ)
• DNL ±0.15 LSB (typ)
• Power Consumption (Non-DES Mode) — Operating in 1:2 Demux Mode 1.9 W (typ) — Power Down Mode 2.5 mW (typ)

Applications

• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-top boxes
• Communications Systems
• Test Instrumentation

Ordering Information

Industrial Temperature Range (-40°C < TA < +85°C) NS Package ADC07D1520CIYB/NOPB Lead-free 128-Pin Exposed Pad LQFP PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

301941 SLAS881A Copyright © 1999-2012, Texas Instruments Incorporated

2 Copyright © 1999-2012, Texas Instruments Incorporated

Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 3

Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description

3 OutV / SCLK

Output Voltage Amplitude and Serial Interface Clock. Tie this pin logic high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See 1.1.6 The LVDS Outputs. When the Extended Control Mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for details on the Extended Control Mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface. 29 PDQ Power Down Q-channel. A logic high on the PDQ pin puts only the Q-channel into the Power Down Mode.

4 OutEdge / DDR /

DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. See 1.1.5.2 OutEdge and Demultiplex Control Setting. When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the Extended Control Mode is enabled, this pin functions as the SDATA input. See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for details on the Extended Control Mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface.

15 DCLK_RST /

DCLK_RST+ DCLK Reset. When single-ended DCLK_RST is selected by floating or setting pin 52 logic high, a positive pulse on this pin is used to reset and synchronize the DCLK outputs of multiple converters. See 1.5 MULTIPLE ADC SYNCHRONIZATION for detailed description. When differential DCLK_RST is selected by setting pin 52 logic low, this pin receives the positive polarity of a differential pulse signal used to reset and synchronize the DCLK outputs of multiple converters. 26 PD Power Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode.

30 CAL

Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles high on this pin initiates the self calibration sequence. See 2.4.2 Calibration for an overview of calibration and

2.4.2.2 On-Command Calibration for a description of on-

command calibration. The calibration cycle may similarly be initiated via the CAL bit in the Calibration register (0h). ADC07D1520

4 Copyright © 1999-2012, Texas Instruments Incorporated

Pin No. Symbol Equivalent Circuit Description

14 FSR/ALT_ECE/

DCLK_RST- Full Scale Range Select, Alternate Extended Control Enable and DCLK_RST-. This pin has three functions. It can conditionally control the ADC full-scale voltage, enable the Extended Control Mode, or become the negative polarity signal of a differential pair in differential DCLK_RST mode. If pin 52 is floating or at logic high and pin 41 is floating, this pin can be used to set the full-scale-range or can be used as an alternate Extended Control Mode enable pin. When used as the FSR pin, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level . A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To enable the Extended Control Mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for information on the Extended Control Mode. Note that pin 41 overrides the Extended Control Mode enable of this pin. When pin 52 is held at logic low, this pin acts as the DCLK_RST- pin. When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. (Note 17)

127 CalDly / DES / SCS

Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. In non-extended control mode, this pin functions as the Calibration Delay select. A logic high or low the number of input clock cycles after power up before calibration begins (See 1.1.1 Calibration). When this pin is floating or connected to a voltage equal to VA/2, DES (Dual Edge Sampling) Mode is selected where the I-channel is sampled at twice the input clock rate and the Q-channel is control mode, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). (Note 17) CLK+ CLK- Differential clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See 1.1.2 Acquiring the Input for a description of acquiring the input and 2.3 THE CLOCK INPUTS for an overview of the clock inputs. ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 5

Pin No. Symbol Equivalent Circuit Description VINI- VINI+ VINQ+ VINQ− Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in Non-Extended Control Mode and the Input Full-Scale Voltage Adjust register in the Extended Control Mode. Refer to the VIN specification in the Converter Electrical Characteristics for the full-scale input range in the Non- Extended Control Mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the Extended Control Mode.

7 VCMO

Common Mode Voltage. This pin is the common mode output in d.c. coupling mode and also serves as the a.c. coupling mode select pin. When d.c. coupling is used at the analog inputs, the voltage output at this pin is required to be the common mode input voltage at VIN+ and VIN−. When a.c. coupling is used, this pin should be grounded. This pin is capable of sourcing or sinking 100 μA. See 2.2 THE ANALOG INPUT.

31 VBG

Bandgap output voltage. This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF.

126 CalRun

Calibration Running indication. This pin is at a logic high when calibration is running. (Note 17)

32 REXT

External bias resistor connection. Nominal value is 3.3 kΩ Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode). These pins may be used for die temperature measurements, however no specified accuracy is implied or guaranteed. Noise coupling from adjacent output data signals has been shown to affect temperature measurements using this feature. See 2.6.2 Thermal Management.

41 ECE

Extended Control Enable. This pin always enables or disables Extended Control Mode. When this pin is set logic high, the Extended Control Mode is inactive and all control of the device must be through control pins only . When it is set logic low, the Extended Control Mode is active. This pin overrides the Extended Control Enable signal set using pin 14. ADC07D1520

6 Copyright © 1999-2012, Texas Instruments Incorporated

Pin No. Symbol Equivalent Circuit Description

52 DRST_SEL

DCLK_RST select. This pin selects whether the DCLK is reset using a single-ended or differential signal. When this pin is floating or logic high, the DCLK_RST operation is single-ended and pin 14 functions as FSR/ALT_ECE. When this pin is logic low, the DCLK_RST operation becomes differential with functionality on pin 15 (DCLK_RST+) and pin 14 (DCLK_RST-). When in differential DCLK_RST mode, there is no pin-controlled FSR and the full-scale-range is defaulted to the higher VIN input level. When pin 41 is set logic low, the Extended Control Mode is active and the Full- Scale Voltage Adjust registers can be programmed. (Note 17) DI6− / DQ6− DI6+ / DQ6+ DI5− / DQ5− DI5+ / DQ5+ DI4− / DQ4− DI4+ / DQ4+ DI3− / DQ3− DI3+ / DQ3+ DI2− / DQ2− DI2+ / DQ2+ DI1− / DQ1− DI1+ / DQ1+ DI0− / DQ0− DI0+ / DQ0+ I- and Q-channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor. In Non-demultiplexed Mode, only these outputs are active. DId6− / DQd6− DId6+ / DQd6+ DId5− / DQd5− DId5+ / DQd5+ DId4− / DQd4− DId4+ / DQd4+ DId3− / DQd3− DId3+ / DQd3+ DId2− / DQd2− DId2+ / DQd2+ DId1− / DQd1− DId1+ / DQd1+ DId0− / DQd0− DId0+ / DQd0+ I- and Q-channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI and DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor. In Non-demultiplexed Mode, these outputs are disabled and are high impedance. When disabled, these outputs must be left floating. OR+/DCLK2+ OR-/DCLK2- Out Of Range, second Data Clock output. When functioning as OR+/-, a differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in Non-extended Control Mode or the Input Full-Scale Voltage Adjust register setting in the Extended Control Mode). This single out of range indication is for both the I- and Q-channels, unless PDQ is asserted, in which case it only applies to the I-channel input. When functioning as DCLK2+/-, DCLK2 is the exact replica of DCLK and outputs the same signal at the same rate. The functionality of these pins is selectable in Extended Control Mode only; default is OR+/-. ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 7

Pin No. Symbol Equivalent Circuit Description DCLK- DCLK+ Data Clock. Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronously to this signal. In 1:2 Demux Mode, this signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. In the Non-demux Mode, DCLK can only be in DDR mode and is at 1/2 the input clock rate. By default, the DCLK outputs are not active during the termination resistor trim section of the calibration cycle. If a system requires DCLK to run continuously during a calibration cycle, the termination resistor trim portion of the cycle can be disabled by setting the Resistor Trim Disable (RTD) bit to logic high in the Extended Configuration Register. This disables all subsequent termination resistor trims after the initial trim which occurs during power-on calibration. This output is not recommended as a system clock unless the resistor trim is disabled. 2, 5, 8, 13, 16, 17, 20, 25, 28, 33, 128 VA Analog power supply pins. Bypass these pins to ground. 40, 51, 62, 73, 88, 99, 110, 121 VDR Output Driver power supply pins. Bypass these pins to DR GND. 1, 6, 9, 12, 21, 24, 27 GND Ground return for VA. 42, 53, 64, 74, 87, 97, 108, 119 DR GND Ground return for VDR. 63, 98, 109, 120 NC No Connection. Make no connection to these pins. RSV+ / RSV- Reserved. These pins may be left unconnected and floating, or as recommended in 2.5.1 Terminating RSV Pins. ADC07D1520

8 Copyright © 1999-2012, Texas Instruments Incorporated

(Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) 2.2V Supply Difference V DR - VA 0V to 100 mV Voltage on Any Input Pin (Except VIN+, VIN- ) −0.15V to (VA +0.15V) Voltage on VIN+, VIN- (Maintaining Common Mode) -0.15V to 2.5V Ground Difference |GND - DR GND| 0V to 100 mV Input Current at Any Pin (Note 3) ±25 mA Package Input Current (Note 3) ±50 mA Maximum Package Power Dissipation at TA ≤ 85°C 2.35 W ESD Susceptibility (Note 4) Human Body Model Machine Model Charged Device Model 2500V 250V 1000V Storage Temperature −65°C to +150°C Operating Ratings (Note 1, Note 2) Ambient Temperature Range −40°C ≤ TA ≤ +85°C Supply Voltage (VA) +1.8V to +2.0V Driver Supply Voltage (VDR) +1.8V to VA Analog Input Common Mode Voltage VCMO ±50 mV VIN+, VIN- Voltage Range (Maintaining Common Mode) 0V to 2.15V (100% duty cycle) 0V to 2.5V (10% duty cycle) Ground Difference (|GND - DR GND|) 0V CLK Pins Voltage Range 0V to VA Differential CLK Amplitude 0.4VP-P to 2.0VP-P Package Thermal Resistance Package θJA θJC Top of Package θJC Thermal Pad 128-Lead, Exposed Pad LQFP 26°C / W 10°C / W 2.8°C / W For soldering information please refer to http://www.ti.com/lit/an/snoa549c/snoa549c.pdf.(Note 5) ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 9

Converter Electrical Characteristics The following specifications apply after calibration for VA = VDR = +1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870 mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1.5 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating; Non-extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 De- multiplex Mode; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Note 6, Note 7, Note 16, Note 18) Symbol Parameter Conditions Typical (Note 8) Limits Units (Limits) STATIC CONVERTER CHARACTERISTICS INL Integral Non-Linearity (Best fit) DC Coupled, 1 MHz Sine Wave Over- ranged ±0.3 ±0.9 LSB (max) DNL Differential Non-Linearity DC Coupled, 1 MHz Sine Wave Over- ranged ±0.15 ±0.6 LSB (max) Resolution with No Missing Codes 7 Bits VOFF Offset Error −0.75 LSB VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV PFSE Positive Full-Scale Error (Note 9) ±25 mV (max) NFSE Negative Full-Scale Error (Note 9) ±25 mV (max) FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20 ±15 %FS 1:2 DEMUX NON-DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ FPBW Full Power Bandwidth Non-DES Mode 2.0 GHz C.E.R. Code Error Rate 10−18 Error/Sample Gain Flatness d.c. to 748 MHz ±0.5 dBFS d.c. to 1.5 GHz ±1.0 dBFS ENOB Effective Number of Bits fIN = 373 MHz, VIN = FSR − 0.5 dB 6.8 6.3 Bits (min) fIN = 748 MHz, VIN = FSR − 0.5 dB 6.8 Bits SINAD Signal-to-Noise Plus Distortion Ratio fIN = 373 MHz, VIN = FSR − 0.5 dB 43 39.5 dB (min) fIN = 748 MHz, VIN = FSR − 0.5 dB 43 dB SNR Signal-to-Noise Ratio fIN = 373 MHz, VIN = FSR − 0.5 dB 43.2 40.8 dB (min) fIN = 748 MHz, VIN = FSR − 0.5 dB 43.2 dB THD Total Harmonic Distortion fIN = 373 MHz, VIN = FSR − 0.5 dB −55 -47 dB (max) fIN = 748 MHz, VIN = FSR − 0.5 dB −60 dB 2nd Harm Second Harmonic Distortion fIN = 373 MHz, VIN = FSR − 0.5 dB −63 dB fIN = 748 MHz, VIN = FSR − 0.5 dB −63 dB 3rd Harm Third Harmonic Distortion fIN = 373 MHz, VIN = FSR − 0.5 dB −58 dB fIN = 748 MHz, VIN = FSR − 0.5 dB −67 dB SFDR Spurious-Free Dynamic Range fIN = 373 MHz, VIN = FSR − 0.5 dB 57 45.5 dB (min) fIN = 748 MHz, VIN = FSR − 0.5 dB 61 dB IMD Intermodulation Distortion fIN1 = 365 MHz, VIN = FSR − 7 dB −50 dBfIN2 = 375 MHz, VIN = FSR − 7 dB Out of Range Output Code (VIN+) − (VIN−) > + Full Scale 127 (VIN+) − (VIN−) < − Full Scale 0 1:4 DEMUX DES MODE, DYNAMIC CONVERTER CHARACTERISTICS; FCLK = 1.5 GHZ FPBW Full Power Bandwidth DES Mode 1.3 GHz ENOB Effective Number of Bits fIN = 748 MHz, VIN = FSR − 0.5 dB 6.7 Bits SINAD Signal to Noise Plus Distortion Ratio fIN = 748 MHz, VIN = FSR − 0.5 dB 42 dB SNR Signal to Noise Ratio fIN = 748 MHz, VIN = FSR − 0.5 dB 43 dB THD Total Harmonic Distortion fIN = 748 MHz, VIN = FSR − 0.5 dB −52 dB 2nd Harm Second Harmonic Distortion fIN = 748 MHz, VIN = FSR − 0.5 dB −57 dB ADC07D1520

10 Copyright © 1999-2012, Texas Instruments Incorporated

Symbol Parameter Conditions Typical (Note 8) Limits Units (Limits) 3rd Harm Third Harmonic Distortion fIN = 748 MHz, VIN = FSR − 0.5 dB −57 dB SFDR Spurious Free Dynamic Range fIN = 748 MHz, VIN = FSR − 0.5 dB 52 dB ANALOG INPUT AND REFERENCE CHARACTERISTICS VIN Full Scale Analog Differential Input Range FSR pin 14 Low (Note 12) 650 590 mVP-P (min) 730 mVP-P (max) FSR pin 14 High 870 800 mVP-P (min) 940 mVP-P (max) VCMI Common Mode Input Voltage VCMO VCMO − 0.05 V (min) VCMO + 0.05 V (max) CIN Analog Input Capacitance, Normal operation (Note 10, Note 11) Differential 0.02 pF Each input pin to ground 1.6 pF Analog Input Capacitance, DES Mode (Note 10, Note 11) Differential 0.08 pF Each input pin to ground 2.2 pF RIN Differential Input Resistance 100 94 Ω (min) 106 Ω (max) ANALOG OUTPUT CHARACTERISTICS VCMO Common Mode Output Voltage ICMO = ±100 µA 1.26 0.95 V (min)

1.45 V (max)

Common Mode Output Voltage Temperature Coefficient TA = −40°C to +85°C 118 ppm/°C VCMO_LVL VCMO input threshold to set D.C. Coupling mode VA = 1.8V 0.60 V VA = 2.0V 0.66 V CLOAD VCMO Maximum VCMO Load Capacitance 80 pF VBG Bandgap Reference Output Voltage IBG = ±100 µA 1.26 1.20 V (min)

1.34 V (max)

TA = −40°C to +85°C, IBG = ±100 µA 28 ppm/°C CLOAD VBG Maximum Bandgap Reference load Capacitance 80 pF CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match 1 LSB Positive Full-Scale Match Zero offset selected in Control Register 1 LSB Negative Full-Scale Match Zero offset selected in Control Register 1 LSB Phase Matching (I, Q) fIN = 1.5 GHz < 1 Degree X-TALK Crosstalk from I-channel (Aggressor) to Q-channel (Victim) Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. −65 dB X-TALK Crosstalk from Q-channel (Aggressor) to I-channel (Victim) Aggressor = 867 MHz F.S. Victim = 100 MHz F.S. −65 dB LVDS CLK INPUT CHARACTERISTICS (Typical specs also apply to DCLK_RST) VID Differential Clock Input Level Sine Wave Clock 0.6 0.4 VP-P (min)

2.0 VP-P (max)

Square Wave Clock 0.6 0.4 VP-P (min) VOSI Input Offset Voltage 1.2 V CIN Input Capacitance (Note 10, Note 11) Differential 0.02 pF Each input to ground 1.5 pF ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 11

Symbol Parameter Conditions Typical (Note 8) Limits Units (Limits) DIGITAL CONTROL PIN CHARACTERISTICS VIH Logic High Input Voltage OutV, DCLK_RST, PD, PDQ, CAL, ECE, DRST_SEL 0.69 x VA V (min) OutEdge, FSR, CalDly 0.79 x VA V (min) VIL Logic Low Input Voltage OutV, DCLK_RST, PD, PDQ, CAL 0.28 x VA V (max) OutEdge, FSR, CalDly, ECE, DRST_SEL 0.21 x VA V (max) CIN Input Capacitance (Note 11, Note 13) Each input to ground 1.2 pF DIGITAL OUTPUT CHARACTERISTICS VOD LVDS Differential Output Voltage Measured differentially, OutV = VA, VBG = Floating (Note 15) 660 460 mVP-P (min) 975 mVP-P (max) Measured differentially, OutV = GND, VBG = Floating (Note 15) 580 300 mVP-P (min) 740 mVP-P (max) ΔVO DIFF Change in LVDS Output Swing Between Logic Levels ±1 mV VOS Output Offset Voltage See Figure 1 VBG = Floating 800 mV VBG = VA (Note 15) 1175 mV ΔVOS Output Offset Voltage Change Between Logic Levels ±1 mV IOS Output Short Circuit Current Output+ and Output− connected to 0.8V ±4 mA ZO Differential Output Impedance 100 Ohms VOH CalRun H level output IOH = −400 µA (Note 12) 1.65 1.5 V VOL CalRun L level output IOH = 400 µA (Note 12) 0.15 0.3 V POWER SUPPLY CHARACTERISTICS (NON-DES MODE) IA Analog Supply Current 1:2 Demux Mode; fCLK = 1.5 GHz PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High 810 560 1.3 930 630 mA (max) mA (max) mA IDR Output Driver Supply Current 1:2 Demux Mode; fCLK = 1.5 GHz PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High 190 107 0.025 295 163 mA (max) mA (max) mA PD Power Consumption 1:2 Demux Mode; fCLK = 1.5 GHz PD = PDQ = Low PD = Low, PDQ = High PD = PDQ = High 1.9 1.25 2.5 2.33 1.53 W (max) W (max) mW PSRR1 D.C. Power Supply Rejection Ratio Change in Full Scale Error with change in VA from 1.8V to 2.0V -30 dB ADC07D1520

12 Copyright © 1999-2012, Texas Instruments Incorporated

Symbol Parameter Conditions Typical (Note 8) Limits Units (Limits) A.C. ELECTRICAL CHARACTERISTICS fCLK (max) Maximum Input Clock Frequency Demux Mode (DES or Non-DES Mode) 1.5 GHz fCLK (min) Minimum Input Clock Frequency 1:2 Demux Non-DES Mode 200 MHz 1:4 Demux DES Mode 500 MHz Input Clock Duty Cycle fCLK(min) ≤ fCLK ≤ 1.5 GHz (Note 12) 20 % (min) 80 % (max) tCL Input Clock Low Time (Note 11) 333 133 ps (min) tCH Input Clock High Time (Note 11) 333 133 ps (min) DCLK Duty Cycle (Note 11) 50 45 % (min) 55 % (max) tSR Setup Time DCLK_RST± (Note 12) 90 ps tHR Hold Time DCLK_RST± (Note 12) 30 ps tPWR Pulse Width DCLK_RST± (Note 11) 4 Input Clock Cycles (min) tLHT Differential Low-to-High Transition Time 10% to 90%, CL = 2.5 pF 150 ps tHLT Differential High-to-Low Transition Time 10% to 90%, CL = 2.5 pF 150 ps tOSK DCLK-to-Data Output Skew 50% of DCLK transition to 50% of Data transition, SDR Mode and DDR Mode, 0° DCLK (Note 11) ±50 ps (max) tSU Data-to-DCLK Set-Up Time DDR Mode, 90° DCLK (Note 11) 400 ps tH DCLK-to-Data Hold Time DDR Mode, 90° DCLK (Note 11) 560 ps tAD Sampling (Aperture) Delay Input CLK+ Fall to Acquisition of Data 1.6 ns tAJ Aperture Jitter 0.4 ps (rms) tOD Input Clock-to Data Output Delay (in addition to Pipeline Delay) 50% of Input Clock transition to 50% of Data transition 4.0 ns Pipeline Delay (Latency) in 1:2 Demux Mode (Note 11, Note 14) DI Outputs 13 Input Clock Cycles DId Outputs 14 DQ Outputs Non-DES Mode 13 DES Mode 13.5 DQd Outputs Non-DES Mode 14 DES Mode 14.5 Pipeline Delay (Latency) in Non-Demux Mode (Note 11, Note 14) DI Outputs 13 Input Clock CyclesDQ Outputs Non-DES Mode 13 DES Mode 13.5 Over Range Recovery Time Differential VIN step from ±1.2V to 0V to get accurate conversion 1 Input Clock Cycle tWU PD low to Rated Accuracy Conversion (Wake-Up Time) Non-DES Mode (Note 11) 500 ns DES Mode (Note 11) 1 µs fSCLK Serial Clock Frequency (Note 11) 15 MHz tSSU Serial Data to Serial Clock Rising Setup Time (Note 11) 2.5 ns (min) tSH Serial Data to Serial Clock Rising Hold Time (Note 11) 1 ns (min) tSCS CS to Serial Clock Rising Setup Time 2.5 ns ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 13

Symbol Parameter Conditions Typical (Note 8) Limits Units (Limits) tHCS CS to Serial Clock Falling Hold Time 1.5 ns Serial Clock Low Time 30 ns (min) Serial Clock High Time 30 ns (min) tCAL Calibration Cycle Time 1.4 x 106 Clock Cycles tCAL_L CAL Pin Low Time See Figure 10 (Note 11) 1280 Clock Cycles (min) tCAL_H CAL Pin High Time See Figure 10 (Note 11) 1280 Clock Cycles (min) tCalDly Calibration delay determined by CalDly (pin 127) CalDly = Low See 1.1.1 Calibration, Figure 10, (Note 11)

226 Clock Cycles

(max) CalDly = High See 1.1.1 Calibration, Figure 10, (Note 11)

232 Clock Cycles

(max) ADC07D1520

14 Copyright © 1999-2012, Texas Instruments Incorporated

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins. Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. 30194104 Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded. Note 8: Typical figures represent most likely parametric norms at TA = 25°C and nominal supply voltages at the time of product characterization and are not guaranteed. Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error. Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. Note 11: This parameter is guaranteed by design and is not tested in production. Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. Note 14: The ADC07D1520 has two LVDS output buses, each of which clocks data out at one half the sample rate. The second bus (D0 through D6) has a pipeline latency that is one clock cycle less than the latency of the first bus (Dd0 through Dd6). Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to the supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical). Note 16: The maximum clock frequency for Non-Demux Mode is 1 GHz. Note 17: This feature is not tested for performance or functionality in production. Note 18: Production test coverage does not guarantee all possible combinations of Non-Extended and/or Extended mode device configuration settings. ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 15

signal present at the input pin is sampled inside the device. APERTURE JITTER (tAJ) is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise. one word about every four (4) years. CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period. at sample rate = 500 MSPS with a 1MHz input sine wave. below its low frequency value for a full-scale input. that code value step. The best fit method is used. intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. solute value of the difference between the VD+ and VD - signals; each measured with respect to Ground. FIGURE 1. LVDS Output Signal Levels reached with any input value. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. combination of full-scale error and reference voltage error. OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input. Offset Error = Actual Input causing average of 8k samples to result in an average code of 127.5. to recover and make a conversion with its rated accuracy.

16 Copyright © 1999-2012, Texas Instruments Incorporated

PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when that data is presented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the tOD. POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2 LSB below a differential +VIN/2. For the ADC07D1520 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error. POWER SUPPLY REJECTION RATIO (PSRR) can be one of two specifications. PSRR1 (D.C. PSRR) is the ratio of the change well an a.c. signal riding upon the power supply is rejected from the output and is measured with a 248 MHz, 50 mVP-P signal riding upon the power supply. It is the ratio of the output amplitude of that signal at the output to its amplitude on the power supply pin. PSRR is expressed in dB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the input clock frequency, including harmonics but excluding d.c. SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding d.c. TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. – Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in its 2nd harmonic level at the output. – Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic level at the output. ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 17

FIGURE 2. Input / Output Transfer Characteristic

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FIGURE 5. DDR Clocking in Non-Demultiplexed Non-DES Mode FIGURE 6. Serial Interface Timing FIGURE 7. Clock Reset Timing in DDR Mode

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Typical Performance Characteristics VA = VDR = 1.9V, fCLK = 1500 MHz, fIN = 748 MHz, TA= 25°C, I channel, 1:2 Demux Mode (1:1 Demux Mode has similar performance), unless otherwise stated. POWER CONSUMPTION vs. CLOCK FREQUENCY 0 500 1000 1500 1.0 1.5 2.0 2.5POWER (W) CLOCK FREQUENCY (MHz) 30194181 ENOB vs. TEMPERATURE -50 0 50 100 6.7 6.8 6.9 7.0ENOB TEMPERATURE (°C) 30194196 ENOB vs. SUPPLY VOLTAGE 6.7 6.8 6.9 7.0ENOB VA (V) I ChannelQ Channel 30194177 ENOB vs. CLOCK FREQUENCY 0 500 1000 1500 6.7 6.8 6.9 7.0ENOB CLOCK FREQUENCY (MHz) I-ChannelQ-Channel 30194178 ENOB vs. INPUT FREQUENCY 0 500 1000 15006.0 6.2 6.4 6.6 6.8 7.0ENOB INPUT FREQUENCY (MHz) I-ChannelQ-Channel 30194179 SNR vs. TEMPERATURE -50 0 50 100 45SNR (dB) TEMPERATURE (°C) 30194168 ADC07D1520

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SNR vs. SUPPLY VOLTAGE 45SNR (dB) VA (V) I-ChannelQ-Channel 30194169 SNR vs. CLOCK FREQUENCY 0 500 1000 1500 45SNR (dB) CLOCK FREQUENCY (MHz) I-ChannelQ-Channel 30194170 SNR vs. INPUT FREQUENCY 0 500 1000 1500 45SNR (dB) INPUT FREQUENCY (MHz) I-ChannelQ-Channel 30194171 THD vs. TEMPERATURE -50 0 50 100 -60 -55 -50 -45 -40THD (dB) TEMPERATURE (°C) 30194172 THD vs. SUPPLY VOLTAGE -60 -55 -50 -45 -40THD (dB) VA (V) I-ChannelQ-Channel 30194173 THD vs. CLOCK FREQUENCY 0 500 1000 1500 -60 -55 -50 -45 -40THD (dB) CLOCK FREQUENCY (MHz) I-ChannelQ-Channel 30194174 ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 23

THD vs. INPUT FREQUENCY 0 500 1000 1500 -60 -55 -50 -45 -40THD (dB) INPUT FREQUENCY (MHz) I-ChannelQ-Channel 30194175 SFDR vs. TEMPERATURE -50 0 50 100 65SFDR (dB) TEMPERATURE (°C) 30194185 SFDR vs. SUPPLY VOLTAGE 65SFDR (dB) VA (V) I-ChannelQ-Channel 30194184 SFDR vs. CLOCK FREQUENCY 0 500 1000 1500 65SFDR (dB) CLOCK FREQUENCY (MHz) I-ChannelQ-Channel 30194182 SFDR vs. INPUT FREQUENCY 0 500 1000 1500 65SFDR (dB) INPUT FREQUENCY (MHz) I-ChannelQ-Channel 30194183 Spectral Response at FIN = 373 MHz 0 250 500 750 -80 -70 -60 -50 -40 -30 -20 -10 MAGNITUDE (dBFS) FREQUENCY (MHz) 30194187 ADC07D1520

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Spectral Response at FIN = 748 MHz 0 250 500 750 -80 -70 -60 -50 -40 -30 -20 -10 MAGNITUDE (dBFS) FREQUENCY (MHz) 30194188 CROSSTALK vs. SOURCE FREQUENCY 30194163 FULL POWER BANDWIDTH (NON-DES MODE) 30194186 GAIN STABILITY vs. DIE TEMPERATURE 30194195 ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 25

1.0 Functional Description

The ADC07D1520 is a versatile A/D Converter with an innovative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions dis- cussed here and in the Applications Information Section. While it is generally poor practice to allow an active pin to float, pins 4, 14, 52 and 127 of the ADC07D1520 are designed to be left floating without jeopardy. In all discussions for pins 4, 14, and 127, whenever a function is called by allowing these control pins to float, connecting that pin to a potential of one half the VA supply voltage will have the same effect as allowing it to float.

1.1 OVERVIEW

The ADC07D1520 uses a calibrated folding and interpolating architecture that achieves 6.8 effective bits. The use of folding am- plifiers greatly reduces the number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. In addition to correcting other non- idealities, on-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely fast, high performance, low power converter. The analog input signal that is within the converter's input voltage range is digitized to seven bits at speeds of 200 MSPS to 1.5 GSPS. Differential input voltages below negative full-scale will cause the output word to consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of all ones. Either of these conditions at either the I- or Q- channel will cause the Out of Range (OR) output to be activated. This single OR output indicates when the output code from one or both of the channels is below negative full scale or above positive full scale. When PDQ is asserted, the OR indication applies to the I channel only. For Non-DES Modes, each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demux Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-demux Mode is selected, the output data rate on channels DI and DQ are at the same rate as the input sample clock. The output levels may be selected to be normal or reduced. Using reduced levels saves power but could result in erroneous data capture of some or all of the bits, especially at higher sample rates and in marginally designed systems.

1.1.1 Calibration

A calibration is performed upon power-up and can also be invoked by the user upon command. Calibration trims the 100Ω analog input differential termination resistor and minimizes full-scale error, offset error, DNL and INL, resulting in maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal bias currents are also set during the calibration process. All of this is true whether the calibration is performed upon power up or is performed upon command. Running the calibration is required for proper operation and to obtain the ADC's specified performance. In addition to the requirement to be run at power-up, an on-command calibration must be run whenever the sense of the FSR pin is changed. For best performance, it is recommend that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly, relative to the specific run while the device is in the power-down mode. See 1.1.7 Power Down for information on the interaction between Power Down and Calibration. In normal operation, calibration is performed just after application of power and whenever a valid calibration command is given, which may be accomplished one of two ways, via the CAL pin (30) or the Calibration register (Addr: 0h, Bit 15). The calibration command is achieved by holding the CAL pin low for at least t CAL_L clock cycles, and then holding it high for at least another tCAL_H clock cycles, as defined in the Converter Electrical Characteristics. The time taken by the calibration procedure is specified as tCALin Converter Electrical Characteristics. Holding the CAL pin high upon power up will prevent the calibration process from running until the CAL pin experiences the above-mentioned tCAL_L clock cycles followed by tCAL_H clock cycles. CalDly (pin 127) is used to select one of two delay times that take place from the application of power to the start of calibration. This calibration delay time is dependent on the setting of the CalDly pin and is specified as t CalDly in the Converter Electrical Characteristics. These delay values allow the power supply to come up and stabilize before calibration takes place. If the PD pin is high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the power supply.

1.1.2 Acquiring the Input

In 1:2 Demux Non-DES Mode, data is acquired at the falling edge of CLK+ (pin 18) and the digital equivalent of that data is available at the digital outputs 13 input clock cycles later for the DI and DQ output buses and 14 input clock cycles later for the DId and DQd output buses. See Pipeline Delay in the Converter Electrical Characteristics. There is an additional internal delay called tOD before the data is available at the outputs. See the Timing Diagrams. The ADC07D1520 will convert as long as the input clock signal is present. The fully differential comparator design and the innovative design of the sample-and-hold amplifier, together with self calibration, enables a very flat SINAD/ENOB response beyond 1.5 GHz. The ADC07D1520 output data signaling is LVDS and the output format is offset binary.

1.1.3 Control Modes

Much of the user control can be accomplished with several control pins that are provided. Examples include initiation of the cali- bration cycle, power down mode and full scale range setting. However, the ADC07D1520 also provides an Extended Control Mode whereby a serial interface is used to access register-based control of several advanced features. The Extended Control Mode is not intended to be enabled and disabled dynamically. Rather, the user is expected to employ either the Non-extended Control Mode or the Extended Control Mode at all times. When the device is in the Extended Control Mode, pin-based control of several ADC07D1520

26 Copyright © 1999-2012, Texas Instruments Incorporated

on the Extended Control Mode.

1.1.4 The Analog Inputs

and VIN- when d.c. coupling is used. VIN input level. The full-scale range setting operates on both ADCs. adjusted as described in 1.4 REGISTER DESCRIPTION and 2.2 THE ANALOG INPUT.

1.1.5 Clocking

The ADC07D1520 offers output clocking options: two of these options are Single Data Rate (SDR) and Double Data Rate (DDR). In SDR mode, the user has a choice of which Data Clock (DCLK) edge, rising or falling, the output data transitions on.

1.1.5.1 Dual-Edge Sampling

The Dual-Edge Sampling (DES) Mode allows either of the ADC07D1520's inputs (I- or Q-channel) to be sampled by both ADCs. frequency, or 3 GSPS with a 1.5 GHz input clock. with each edge of the clock in the following sampling order, from the earliest to the latest: DQ, DI. See Table 2. operation, the user can select which input is sampled. provides optimal DES Mode performance. TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode** ** Note that, in the Non-demux Mode (DES and Non-DES Mode), the DId and DQd outputs are disabled and are high impedance.

TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demux Mode

1.1.5.2 OutEdge and Demultiplex Control Setting

1.1.5.3 Double Data Rate and Single Data Rate

1.1.5.4 Clocking Summary

Demux Mode, the channel is not demultiplexed. Note that Non-Demux Mode is also sometimes referred to as 1:1 Demux Mode. but at half the rate of Non-Demux Mode.

1. Non-Demux Non-DES Mode: This mode is when the chip is in Non-Demux Mode and Non-DES Mode. The I- and Q- channels
2. Non-Demux DES Mode: This mode is when the chip is in Non-Demux Mode and DES Mode. The I- and Q- channels are

although the chip is in Non-Demux Mode, both I- and Q-channels are functioning and passing data.

1. 1:2 Demux Non-DES Mode: This mode is when the chip is in Demux Mode and Non-DES Mode. The I- and Q- channels

on DQ and DQd. This is because each channel (I-channel and Q-channel) is providing digital data in a demultiplexed manner.

1. 1:4 Demux DES Mode: This mode is when the chip is in Demux Mode and DES Mode. The I- and Q- channels are interleaved

1:4 because the analog input signal is provided on one channel and the digital output data is provided on four busses.

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DCLK runs at half the rate of the output data; the output data transitions on both rising and falling edges of the DCLK.

1.1.6 The LVDS Outputs

the ADC07D1520 is used is noisy, it may be necessary to tie the OutV pin high. common mode is required, this common mode voltage can be increased to 1175 mV by tying the VBG pin to VA . IMPORTANT NOTE: Tying the VBG pin to VA will also increase the differential LVDS output voltage by up to 40mV.

1.1.7 Power Down

power consumption is reduced to a minimal level. a calibration after PDQ is brought low.

1.2 NON-EXTENDED AND EXTENDED CONTROL MODE

simpler Non-extended Control Mode, the user affects available configuration and control of the device through several control pins. The Extended Control Mode provides additional configuration and control options through a serial interface and a set of 9 registers. not intended to be switched dynamically while the device is operational. Table 3 shows how several of the device features are affected by the control mode chosen. TABLE 3. Features and Modes low and longer delay selected when high. Short delay only. range selected for I- and Q-channels. (Addr-3h and Bh; bit-7 through 15).

(Addr-2h and Ah; bit-7 thru 15). TABLE 4. Extended Control Mode Operation

30 Copyright © 1999-2012, Texas Instruments Incorporated

1.3 THE SERIAL INTERFACE

values. Subsequent writes to single registers are allowed. to the SCLK must be observed. SCLK: Serial data input is accepted at the rising edge of this signal. There is no minimum frequency requirement for SCLK. and register value. The data is shifted in MSB first. Setup and hold times with respect to the SCLK must be observed. next 4 bits are the address of the register that is to be written to and the last 16 bits are the data written to the addressed register. The addresses of the various registers are indicated in Table 5. Refer to 1.4 REGISTER DESCRIPTION for information on the data to be written to the registers. SCS input permanently enabled (logic low) when using Extended Control Mode. Control register contents are retained when the device is put into power-down mode. duration of the register access time. TABLE 5. Register Addresses

1.4 REGISTER DESCRIPTION

Nine write-only registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset (POR) state of each control bit. Calibration Register Addr: 0h (0000b) Write only (0x7FFF) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CAL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 CAL: Calibration Enable. When this bit is set 1b, an on-command calibration cycle is initiated. This function is exactly the same as issuing an on-command calibration using the CAL pin. This bit is OR'd with the CAL pin (30). POR State: 0b Bits 14:0 Must be set to 1b Configuration Register Addr: 1h (0001b) Write only (0xB2FF) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 nSD DCS DCP nDE OV OED 1 1 1 1 1 1 1 1 Bit 15 Must be set to 1b Bit 14 Must be set to 0b Bit 13 nSD: Second DCLK Output. When this bit is 1b, the device only has one DCLK output and one OR output. When this output is 0b, the device has two identical DCLK outputs and no OR output. POR State: 1b Bit 12 DCS: Duty Cycle Stabilizer. When this bit is set to 1b, a duty cycle stabilization circuit is applied to the clock input. When this bit is set to 0b the stabilization circuit is disabled. POR State: 1b Bit 11 DCP: DDR Clock Phase. This bit only has an effect in the DDR mode. When this bit is set to 0b, the DCLK edges are time-aligned with the data bus edges ("0° Phase"). When this bit is set to 1b, the DCLK edges are placed in the middle of the data bit-cells ("90° Phase"), using the one-half speed DCLK shown in Figure 4 as the phase reference. POR State: 0b Bit 10 nDE: DDR Enable. When this bit is set to 0b, data bus clocking follows the DDR mode whereby a data word is output with each rising and falling edge of DCLK. When this bit is set to a 1b, data bus clocking follows the SDR mode whereby each data word is output with either the rising or falling edge of DCLK, as determined by the OutEdge bit. POR State: 0b Bit 9 OV: Output Voltage. This bit determines the LVDS outputs' voltage amplitude and has the same function as the OutV pin that is used in the Non-extended Control Mode. When this bit is set to 1b, the normal output amplitude is used. When this bit is set to 0b, the reduced output amplitude is used. See V OD in Converter Electrical Characteristics. POR State: 1b Bit 8 OED: Output Edge and Demultiplex Control. This bit has two functions. When the device is in SDR mode, this bit selects the DCLK edge with which the data words transition and has the same effect as the OutEdge pin in the Non-extended Control Mode. When this bit is set to 1b, the data outputs change with the rising edge of DCLK+. When this bit is set to 0b, the data output changes with the falling edge of DCLK+. When the device is in DDR mode, this bit selects the Non-demultiplexed Mode when set to 1b. When the bit set to 0b, the device is programmed into the Demultiplexed Mode. If the device is in DDR and Non- Demultiplexed Mode, then the DCLK has a 0° phase relationship with the data; it is not possible to select the 90° phase relationship. POR State: 0b Bits 7:0 Must be set to 1b IMPORTANT NOTE: It is recommended that this register should only be written upon power-up initialization as writing it may cause disturbance on the DCLK output as this signal's basic configuration is changed. ADC07D1520

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Addr: 2h (0010b) Write only (0x007F) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) Offset Value (LSB) Sign 1 1 1 1 1 1 1 Bits 15:8 Offset Value. The input offset of the I-channel ADC is adjusted linearly and monotonically by the value in this field. 00h provides a nominal value of zero offset, while FFh provides a nominal value of 45 mV of offset. Thus, each code step provides 0.176 mV of offset. POR State: 0000 0000 b Bit 7 Sign bit. 0b gives positive offset, 1b gives negative offset, resulting in total offset adjustment of ±45 mV. POR State: 0b Bit 6:0 Must be set to 1b I-Channel Full-Scale Voltage Adjust Addr: 3h (0011b) Write only (0x807F) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) Adjust Value (LSB) 1 1 1 1 1 1 1 Bit 15:7 Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I-channel is adjusted linearly and monotonically with a 9 bit data value. The adjustment range is ±20% of the nominal 700 mV P-P differential value. 0000 0000 0 560mVP-P 1000 0000 0 Default Value 700mVP-P 1111 1111 1 840mVP-P For best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to 1110 0000 0b, i.e., limit the amount of adjustment to ±15%. The remaining ±5% headroom allows for the ADC's own full scale variation. A gain adjustment does not require ADC re-calibration. POR State: 1000 0000 0b (no adjustment) Bits 6:0 Must be set to 1b ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 33

Extended Configuration Register Addr: 9h (1001b) Write only (0x03FF) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TPO RTD DEN IS 0 DLF 1 1 1 1 1 1 1 1 1 1 Bit 15 TPO: Test Pattern Output. When this bit is set 1b, the ADC is disengaged and a test pattern generator is connected to the outputs including OR. This test pattern will work with the device in the SDR, DDR and the Non-demux Modes (DES and Non-DES). POR State: 0b Bit 14 RTD: Resistor Trim Disable. When this bit is set to 1b, the input termination resistor is not trimmed during the calibration cycle and the DCLK output remains enabled. Note that the ADC is calibrated regardless of this setting. POR State: 0b Bit 13 DEN: DES Enable. Setting this bit to 1b enables the Dual Edge Sampling Mode. In this mode, the ADCs in this device are used to sample and convert the same analog input in a time-interleaved manner, accomplishing a sample rate of twice the input clock rate. When this bit is set to 0b, the device operates in the Non-DES Modes. POR State: 0b Bit 12 IS: Input Select. When this bit is set to 0b the I-channel is operated upon by both ADCs. When this bit is set to 1b the Q-channel is operated on by both ADCs. POR State: 0b Bit 11 Must be set to 0b Bit 10 DLF: DES Low Frequency. When this bit is set 1b, the dynamic performance of the device is improved when the input clock is less than 900 MHz. POR State: 0b Bits 9:0 Must be set to 1b ADC07D1520

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Addr: Ah (1010b) Write only (0x007F) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) Offset Value (LSB) Sign 1 1 1 1 1 1 1 Bit 15:8 Offset Value. The input offset of the Q-channel ADC is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero offset, while FFh provides a nominal 45 mV of offset. Thus, each code step provides about 0.176 mV of offset. POR State: 0000 0000 b Bit 7 Sign bit. 0b gives positive offset, 1b gives negative offset. POR State: 0b Bit 6:0 Must be set to 1b Q-Channel Full-Scale Voltage Adjust Addr: Bh (1011b) Write only (0x807F) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) Adjust Value (LSB) 1 1 1 1 1 1 1 Bit 15:7 Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the Q-channel ADC is adjusted linearly and monotonically with a 9 bit data value. The adjustment range is ±20% of the nominal 700 mVP-P differential value. 0000 0000 0 560 mVP-P 1000 0000 0 Default Value 700 mVP-P 1111 1111 1 840 mVP-P For best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to 1110 0000 0b, i.e., limit the amount of adjustment to ±15%. The remaining ±5% headroom allows for the ADC's own full scale variation. A gain adjustment does not require ADC re-calibration. POR State: 1000 0000 0b (no adjustment) Bits 6:0 Must be set to 1b ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 35

Sample Clock Phase Fine Adjust Addr: Eh (1110b) Write only (0x00FF) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) Fine Phase Adjust (LSB) 1 1 1 1 1 1 1 1 Bits 15:8 Fine Phase Adjust. The phase of the ADC sampling clock is adjusted linearly and monotonically by the value in this field. 00h provides a nominal zero phase adjustment, while FFh provides a nominal 50 ps of delay. Thus, each code step provides about 0.2 ps of delay. POR State: 0000 0000b Bits 7:0 Must be set to 1b Sample Clock Phase Intermediate/Coarse Adjust Addr: Fh (1111b) Write only (0x007F) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POL Coarse Phase Adjust Int Phase Adjust 1 1 1 1 1 1 1 Bit 15 Polarity Select. When this bit is selected, the polarity of the ADC sampling clock is inverted. POR State: 0b Bits 14:10 Coarse Phase Adjust. Each code value in this field delays the sample clock by approximately 65 ps. A value of 00000b in this field causes zero adjustment. POR State: 00000b Bits 9:7 Intermediate Phase Adjust. Each code value in this field delays the sample clock by approximately 11 ps. A value of 000b in this field causes zero adjustment. Maximum combined adjustment using Coarse Phase Adjust and Intermediate Phase adjust is approximately 2.1ns. POR State: 000b Bits 6:0 Must be set to 1b

1.4.1 Clock Phase Adjust

This is a feature intended to help the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used. However, enabling this feature will reduce the dynamic performance (ENOB, SNR, SFDR) some finite amount. The amount of degradation increases with the amount of adjustment applied. The user is strongly advised to (a) use the minimal amount of adjustment; and (b) verify the net benefit of this feature in his system before relying on it.

1.4.2 DCLK Output During Register Programming

When programming the Configuration register, the DCLK output may be disrupted and is invalid. The DCLK output is not valid until the register data has not been completely shifted and latched into the register and the register is in a known programmed state. To minimize disrupting the DCLK output, it is recommend that the Configuration Register only be programmed when necessary. For example, if a user wishes to enable the test pattern, only the Test Pattern register should be programmed. A user should avoid developing software routines which program all the registers when the data contents of only one register is being modified. ADC07D1520

36 Copyright © 1999-2012, Texas Instruments Incorporated

1.5 MULTIPLE ADC SYNCHRONIZATION

same time with respect to the shared CLK input that all the ADCs use for sampling. are three CLK cycles of delay. it is strongly recommended that DCLK only be used as a data capture clock and not as a system clock. cause a glitch in the digital circuitry, resulting in corruption and invalidation of the calibration.

1.6 ADC TEST PATTERN

as described in the Table 6 and Table 7. TABLE 6. Test Pattern by Output Port With the part programmed into the Non-demultiplex Mode, the test pattern’s order will be as described in Table 7.

TABLE 7. Test Pattern by Output Port in and Qd patterns may be behind by one DCLK. will work at speed and with the device in the SDR, DDR and the Non-demux Modes (DES and Non-DES).

38 Copyright © 1999-2012, Texas Instruments Incorporated

2.0 Applications Information

2.1 THE REFERENCE VOLTAGE

available at VBG (pin 31) for the user. This output has an output current capability of ±100 μA and should be buffered if more current than this is required. range. See 2.2.3 Out Of Range Indication. the typical value, the VBG pin can be connected directly to the supply rail.

2.2 THE ANALOG INPUT

guidelines on limiting the amount of adjustment. will be determined by the full scale range and offset settings in the Control Registers. TABLE 8. Differential Input To Output Relationship with adequate noise and distortion performance, and adequate gain at the frequencies used for the application. to be connected to the inputs through on-chip 50 kΩ resistors. pacitors to ground) when the inputs are a.c. coupled. Do not connect an unused analog input directly to ground. FIGURE 11. VCMO Drive for A.C. Coupled Differential Input

output of the driving device should track this change. inputs are d.c. coupled. Do not connect unused analog inputs to ground. result of using a very low supply voltage to minimize power. Keep the input common voltage within 50 mV of VCMO. both analog inputs remains within 50 mV of VCMO.

2.2.1 Single-Ended Input Signals

to differential signal conversion is with an appropriate balun-connected transformer, as shown in Figure 12. FIGURE 12. Single-Ended to Differential Signal Conversion Using a Balun manufacturer of the balun in order to aid in designing the best performing single-ended to differential conversion circuit. Characteristics as the specification RIN. output is within the specified input range of the ADC; see VIN in the Converter Electrical Characteristics. voltage operation and reasonable offset voltage. The output current from the ADC07D1520 VCMO pin should be limited to 100 μA.

40 Copyright © 1999-2012, Texas Instruments Incorporated

FIGURE 13. Example of Using LM6555 for D.C. Coupled Input TABLE 9. Resistor Values for Offset Adjustment

2.2.3 Out Of Range Indication

is programmed to provide a second DCLK output, the OR signals become DCLK2. Refer to 1.4 REGISTER DESCRIPTION.

2.2.4 Full-Scale Input Range

but better distortion and SFDR are obtained with the FSR pin low. The LMH6555 of Figure 13 is suitable for any Full Scale Range.

2.3 THE CLOCK INPUTS

FIGURE 14. Differential (LVDS) Input Clock Connection ADC07D1520 clock input is internally terminated with an untrimmed 100Ω resistor. range; see the Converter Electrical Characteristics. range of the ADC, "N" is the ADC resolution in bits and fIN is the maximum input frequency, in Hertz, at the ADC analog input. jitter added by the analog circuitry to the analog signal to a minimum. Input clock amplitudes above those specified in the Converter Electrical Characteristics may result in increased input offset voltage.

2.4 CONTROL PINS

chronization choice, LVDS Output Level choice and a Power Down feature.

2.4.1 Full-Scale Input Range Setting

scale range may be programmed using the Full-Scale Adjust Voltage register. See 2.2 THE ANALOG INPUT for more information.

2.4.2 Calibration

2.4.2.1 Power-On Calibration

42 Copyright © 1999-2012, Texas Instruments Incorporated

The internal power-on calibration circuitry comes up in an unknown logic state. If the input clock is not running at power up and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the power consumption will typically be less than 200 mW. The power consumption will be normal after the clock starts.

2.4.2.2 On-Command Calibration

To initiate an on-command calibration, either bring the CAL pin high for a minimum of t CAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles or perform the same operation via the CAL bit in the Calibration register. Holding the CAL pin high upon power up will prevent execution of power-on calibration until the CAL pin is low for a minimum of t CAL_L input clock cycles, then brought high for a minimum of another tCAL_H input clock cycles. The calibration cycle will begin tCAL_H input clock cycles after the CAL pin is thus brought high. The CalRun signal should be monitored to determine when the calibration cycle has completed. The minimum tCAL_L and tCAL_H input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. For best performance, a calibration should be performed 20 seconds or more after power up and repeated when the operating temperature changes significantly, relative to the specific system design performance requirements. By default, on-command calibration also includes calibrating the input termination resistance and the ADC. However, since the input termination resistance, once trimmed at power-up, changes marginally with temperature, the user has the option to disable the input termination resistor trim, which will guarantee that the DCLK is continuously present at the output during subsequent calibration. The Resistor Trim Disable (RTD) can be programmed in register 9h when in the Extended Control Mode. Refer to 1.4 REGISTER DESCRIPTION for register programming information.

2.4.2.3 Calibration Delay

The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of calibration, as described in 1.1.1 Calibration. The calibration delay values allow the power supply to come up and stabilize before calibration takes place. With no delay or insufficient delay, calibration would begin before the power supply is stabilized at its operating value and result in non-optimal calibration coefficients. If the PD pin is high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the power supply. Note that the calibration delay selection is not possible in the Extended Control Mode and the short delay time is used.

2.4.3 Output Edge Synchronization

DCLK signals are available to latch the converter output data into external circuitry. The output data can be synchronized with either edge of these DCLK signals. That is, the output data transition can be set to occur with either the rising edge or the falling edge of the DCLK signal, so that either edge of that DCLK signal can be used to latch the output data into the receiving circuit. When OutEdge (pin 4) is high, the output data is synchronized with the rising edge of the DCLK+ (pin 82). When OutEdge is low, the output data is synchronized with the falling edge of DCLK+. At the very high speeds, of which the ADC07D1520 is capable, slight differences in the lengths of the DCLK and data lines can mean the difference between successful and erroneous data capture. The OutEdge pin may be used to capture data on the DCLK edge that best suits the application circuit and layout.

2.4.4 LVDS Output Level Control

The output level can be set to one of two levels with OutV (pin 3). The strength of the output drivers is greater with OutV logic high. With OutV logic low, there is less power consumption in the output drivers, but the lower output level means decreased noise immunity. For short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low. If the LVDS lines are long and/or the system in which the ADC07D1520 is used is noisy, it may be necessary to tie the OutV pin high.

2.4.5 Dual Edge Sampling

The Dual Edge Sampling (DES) feature causes one of the two input pairs to be routed to both ADCs. The other input pair is deactivated. One of the ADCs samples the input signal on the rising input clock edge (duty cycle corrected); the other ADC samples the input signal on the falling input clock edge (duty cycle corrected). If the device is in the 1:4 Demux DES Mode, the result is an output data rate 1/4 that of the interleaved sample rate, which is twice the input clock frequency. Data is presented in parallel on all four output buses in the following order: DQd, DId, DQ, DI. If the device is the Non-demux DES Mode, the result is an output data rate 1/2 that of the interleaved sample rate. Data is presented in parallel on two output buses in the following order: DQ, DI. To use this feature in the Non-extended Control Mode, allow pin 127 to float and the signal at the I-channel input will be sampled by both converters. The Calibration Delay will then only be a short delay.

2.4.6 Power Down Feature

The Power Down pins (PD and PDQ) allow the ADC07D1520 to be entirely powered down (PD) or the Q-channel to be powered down and the I-channel to remain active (PDQ). See 1.1.7 Power Down for details on the power down feature. The digital data output pins are put into a high impedance state when the PD pin for the respective channel is high. Upon return to normal operation, the pipeline will contain meaningless information and must be flushed. If the PD input is brought high while a calibration is running, the device will not go into power down until the calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in the power down state. ADC07D1520 Copyright © 1999-2012, Texas Instruments Incorporated 43

2.5 THE DIGITAL OUTPUTS

C07D1520 input clock rate and the two buses must be multiplexed to obtain the entire 1.5 GSPS conversion result. clock, decimating the 200 MSPS data by two. falling edge of DCLK is determined by the sense of the OutEdge pin, as described in 2.4.3 Output Edge Synchronization. the DCLK frequency to 1/4 the input clock frequency. See the Timing Diagrams for details. The OutV pin is used to set the LVDS differential output levels. See 2.4.4 LVDS Output Level Control. those cases where the digital ASIC is capable of higher speed operation.

2.5.1 Terminating RSV Pins

FIGURE 15. Terminating RSV+/− Pins

2.6 POWER CONSIDERATIONS

to each VA pin, preferably within one-half centimeter. Leadless chip capacitors are preferred because they have low lead inductance. common source is used for them. power to the ADC07D1520. The ADC supplies should be the same supply used for other analog circuitry, if not a dedicated supply.

2.6.1 Supply Voltage

function with slightly higher supply voltages, these higher supply voltages may reduce product lifetime. driving any of the input pins, analog or digital, do not come up any faster than does the voltage at the ADC07D1520 power pins.

44 Copyright © 1999-2012, Texas Instruments Incorporated

output current during power-up to ensure there is no turn-on spiking. an LM1086 linear regulator is recommended. FIGURE 16. Non-Spiking Power Supply should not exceed the VA supply voltage. If the power is applied to the device without an input clock signal present, the current drawn by the device might be below 200 mA. the input clock is established.

2.6.2 Thermal Management

as well as to ensure best product parametric performance. of the package. The exposed pad of the device must be soldered down to ensure adequate heat conduction out of the package. FIGURE 17. Recommended Package Land Pattern

Since a large aperture opening may result in poor release, the aperture opening should be subdivided into an array of smaller openings, similar to the land pattern of Figure 17. To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done by including a copper area of about 2 square inches (6.5 square cm) on the opposite side of the PCB. This copper area may be plated or solder coated to prevent corrosion, but should not have a conformal coating, which could provide some thermal insulation. Thermal vias should be used to connect these top and bottom copper areas. These thermal vias act as "heat pipes" to carry the thermal energy from the device side of the board to the opposite side of the board where it can be more effectively dissipated. The use of 9 to 16 thermal vias is recommended. The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this wicking could cause voids in the solder between the package exposed pad and the thermal land on the PCB. Such voids could increase the thermal resistance between the device and the thermal land on the board, which would cause the device to run hotter. If it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the board near the thermal vias. Allow for a thermal gradient between the temperature sensor and the ADC07D1520 die of θJ-PAD times typical power con- sumption = 2.8°C/W x 1.8W = 5°C. Allowing for 6°C, including some margin for temperature drop from the pad to the temperature sensor, would mean that maintaining a maximum pad temperature reading of 124°C will ensure that the die temperature does not exceed 130°C. This calculation assumes that the exposed pad of the ADC07D1520 is properly soldered down and the thermal vias are adequate. (The inaccuracy of the temperature sensor is in addition to the above calculation).

2.7 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A single ground plane should be used, instead of splitting the ground plane into analog and digital areas. Since digital switching transients are composed largely of high frequency components, the skin effect implies that the total ground plane copper weight will have little effect upon the logic-generated noise. Total surface area is more important than is total ground plane volume. Coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High power digital components should not be located on or near any linear component or power supply trace or plane that services analog or mixed signal components, as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC, causing excessive noise in the conversion result. Generally, it is assumed that analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The input clock lines should be isolated from ALL other lines, analog AND digital. The generally accepted 90° crossing should be avoided, as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. This is especially important with the low level drive required of the ADC07D1520. Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be connected to a very clean point in the analog ground plane. All analog circuitry (input amplifiers, filters, etc.) should be separated from any digital components.

2.8 DYNAMIC PERFORMANCE

The ADC07D1520 is a.c. tested and its dynamic performance is guaranteed. To meet the published specifications and avoid jitter- induced noise, the clock source driving the CLK input must exhibit low rms jitter. The allowable jitter is a function of the input frequency and the input signal level, as described in 2.3 THE CLOCK INPUTS. It is good practice to keep the ADC input clock line as short as possible, to keep it well away from any other signals and to treat it as a transmission line. Other signals can introduce jitter into the input clock signal. The clock signal can also introduce noise into the analog path if not isolated from that path. Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection to ground. This is because this path from the die to ground is a lower impedance than offered by the package pins.

2.9 USING THE SERIAL INTERFACE

The ADC07D1520 may be operated in the Non-extended Control Mode or in the Extended Control Mode. Table 10 and Table 11 describe the functions of pins 3, 4, 14 and 127 in the Non-extended Control Mode and the Extended Control Mode, respectively.

2.9.1 Non-Extended Control Mode Operation

Non-extended Control Mode operation means that the Serial Interface is not active and all controllable functions are controlled with various pin settings. Pin 41 is the primary control of the Extended Control Mode enable function. When pin 41 is logic high, the device is in the Non-extended Control Mode. If pin 41 is floating and pin 52 is floating or logic high, the Extended Control Enable function is controlled by pin 14. The device has functions which are pin programmable when in the Non-extended Control Mode. An example is the full-scale range; it is controlled in the Non-extended Control Mode by setting pin 14 logic high or low. Table 10 indicates the pin functions of the ADC07D1520 in the Non-extended Control Mode. ADC07D1520

46 Copyright © 1999-2012, Texas Instruments Incorporated

TABLE 10. Non-Extended Control Mode Operation

3 Reduced VOD Normal VOD N/A

4 OutEdge = Neg OutEdge = Pos DDR

127 CalDly Short CalDly Long DES

14 Reduced VIN Normal VIN Extended Control Mode

1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for more information. Data Rate) and the output edge synchronization is irrelevant since data is clocked out on both DCLK edges. delay is short and the converter performs in DES Mode. TABLE 11. Extended Control Mode Operation

3 SCLK (Serial Clock)

4 SDATA (Serial Data)

127 SCS (Serial Interface Chip Select)

2.10 COMMON APPLICATION PITFALLS

locations must be written at least once with the default or desired values before calibration and subsequent use of the ADC. acteristic impedance should control overshoot. value, but can be used to change the LVDS common mode voltage from 0.8V to 1.2V by tying the VBG pin to VA. in the Operating Ratings Table or the input offset could change. mance. Excessive input clock levels could result in the introduction of an input offset. reduction in SNR performance. board. The backside pad should be grounded for best performance.

Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead Exposed Pad LQFP Order Number ADC07D1520CIYB ADC07D1520

48 Copyright © 1999-2012, Texas Instruments Incorporated

Copyright © 1999-2012, Texas Instruments Incorporated 49

Copyright © 1999-2012, Texas Instruments Incorporated

www.ti.com 12-Nov-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) ADC07D1520CIYB/NOPB ACTIVE HLQFP NNB 128 60 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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