ADC-305

ADC-305 MURATA-PS | Alldatasheet

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Technical content

Ḥ Figure 1. Functional Block Diagram Both the ADC-305-1 and the ADC-305-3 have the same pin assignment.

24 DGNDOUTPUT ENABLE 1

23 VRB

21 AGND

20 AGND

19 VIN

17 VRT

22 VRBS

16 VRTS

FEATURES

■ 8-bit resolution, 20MHz min. sampling rate ■ ±½LSB max. differential nonlinearity error ■ 18MHz input signal bandwidth ■ Subranging, S&H enclosed ■ +5V single power, low 85mW max. dissipation ■ CMOS compatible logic input ■ 3-State TTL compatible output PRODUCT OVERVIEW DATEL's ADC-305 is an 8-bit, 20MHz sam- pling, CMOS, subranging (two-pass) A/D converter. It processes signals at speeds comparable to a full fl ash converter by using a sub-ranging conversion technique with multiple comparator blocks, each containing a sample and hold amplifi er. The ADC-305 features CMOS low power dis- sipation (60mW typical) and a wide 18MHz (–1dB) input signal bandwidth. The ADC-305-1 is packaged in 400 mil 24-pin DIP and the ADC-305-3 in 300 mil 24-pin SOP . Other features are CMOS compatible input logic, 3-state TTL compatible output logic, +5V single power operation, self bias mode and low cost. INPUT/OUTPUT CONNECTIONS Pin FUNCTION Pin FUNCTION

1 OUTPUT ENABLE (OE) 24 DGND

2 DGND 23 REF . BOTTOM (VRB)

3 BIT 8 (LSB) 22 SELF BIAS 1 (VRBS)

4 BIT 7 21 AGND

5 BIT 6 20 AGND

6 BIT 5 19 ANALOG INPUT (VIN)

7 BIT 4 18 +AVS (+5V)

8 BIT 3 17 REFERENCE TOP (VRT)

9 BIT 2 16 SELF BIAS 2 (VRTS)

10 BIT 1 (MSB) 15 +AVS (+5V)

11 +DVS (+5V) 14 +AVS (+5V)

12 CLOCK INPUT (A/D CLK) 13 +DVS (+5V)

8-Bit, 20MHz CMOS A/D Converters MDA_ADC-305.B01 Page 1 of 6 For full details go to www.murata-ps.com/rohs www.murata-ps.com www.murata-ps.com Technical enquiries email: data.acquisition@murata-ps.com, tel: +1 508 339 3000

1. The ADC-305 has separate +AVS and +DVS pins. It is recommended that both +AVS and +DVS be powered from a single supply since a time lag between start up of separate supplies could induce latch up. Other external logic circuits must be powered from a separate digital supply. +DVS (pins 11 and 13) and +AVs (pins 14, 15 and 18) should be tied together externally. DGND (pins 2 and 24) and AGND (pins 20 and 21) should also be tied together externally. Power supply grounds must be connected at one point to the ground plane directly beneath the device. Digital returns should not fl ow through analog grounds. 2. Bypass all power lines to ground with a 0.1µF ceramic chip capacitor in parallel with a 47µF electrolytic capacitor. Locate the bypass capacitor as close to the unit as possible. 3. Even though the analog input capacitance is a low 15pF , it is recommended that high frequency input be provided via a high speed buffer amplifi er. A parasitic oscillation may be generated when a high speed amplifi er is used. A 75 ohm resister inserted between the output of an amplifi er and the analog input of the ADC-305 will improve the situation. A resistor larger than 100 ohms may degrade linearity. 4. The input voltage range is determined by voltages applied to VRB (Reference Bottom) and VRT (Reference Top). Keep to the following equations: 0V≤VRB≤VRT≤2.8V 1.8V≤VRT–VRB≤2.8V The analog input range is normally 2Vp-p. Self Bias Mode a. Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog input range in this case is +0.64V to +2.73V nominal. b. Tie VRB to AGND, and tie VRT to VRTS respectively. The analog input voltage range is 0 to +2.39V in this case. These values may differ from one device to another. Voltage changes on the +5V supply have a direct infl uence on the performance of the device. The use of external references is recommended for applications sensitive to gain error. External Reference Mode Tie VRB to AGND, and apply +2V to VRT to use at 0 to +2V input voltage range. The reference resistance between VRB and VRT is about 300 ohms. It is important to make the output impedance of the reference source small enough while, at the same time, keeping suffi cient drive capacity. Insert a 0.1µF bypass ceramic chip capacitor between VRT and GND to minimize the effect of the 20MHz clock running nearby. See Figure 5. 5. Logic inputs are CMOS compatible. Normally a series 74HC is used as a driver. It is recommended to pull up to +5V if the device is driven with TTL. 6. The start convert (A/D CLK) pulse can be a 50% duty cycle clock. Both TPW1 and TPW0 are 25ns minimum. A slightly longer TPW1 will improve linearity of the system for higher frequency input signals. 7. The digital data outputs are 3-state and TTL compatible. To enable the 3-state outputs, connect the OUTPUT ENABLE (pin 1) to GND. To disable, connect it to +5V. It is recommended that the data outputs be latched and buffered through output registers. 8. Maximum 30ns (18ns typical) after the rising edge of the Nth conversion pulse, the result of the (N-3) conversion can be obtained. Data is stored fi rmly in an output register, such as an 74LS574, using the rising edge of a start convert pulse as a trigger. The (N–4) data is stored in this case. See the timing diagrams, Figure 2 and 4. 9. The 20MHz sampling rate is guaranteed. It is not recommended to use this device at sampling rates slower than 500kHz because the droop characteristics of the internal sample and holds will then exceed the limit required to maintain the specifi ed accuracy of the device. Functional Specifi cations (Specifi cation are typical at TA = +25°C, +VRT = +2.5V, VRB = +0.5V, +AVS = +DVS = +5v, fS = 20MHz sampling unless otherwise specifi ed.) Analog Inputs Min. Typ. Max. Units Input Voltage Range (VIN) ➀ — +0.5 to +2.5 — Volts Input Capacitance — 11 — pF (V IN = 1.5Vdc+0.07VRMS) Input Impedance — 12.5 — k Ω Input Signal Bandwidth — 18 — MHz (VIN-2Vp-p, –1dB) REFERENCE INPUTS Ref. Resitance V RT to VRB 230 300 450 Ω Ref. Current 4.5 6.6 8.7 mA Ref. Voltage ➀ V RT +1.8 — +2.8 Volts V RB 0 — V RT Volts Offset Voltage V RT –10 –35 –60 mV V RB 0 +15 +45 mV Self Bias I ➀ ➁ V RBS +0.6 +0.64 +0.68 Volts V RTS-VRBS +1.96 +2.09 +2.21 Volts Self Bias II ➀ ➂ V RTS +2.25 +2.39 +2.53 Volts DIGITAL INPUTS Input Voltage (CMOS) Logic Levels (VIH) "1" +4 — — Volts Logic Level (V IL) "0" — — +1 Volts Input Current (@VIH=+DVS)"1" — — 5 µA Clock Pulse Width TPW1 25 — — ns (A/D CLK) T PW0 25 — — ns DIGITAL Outputs Output Data 8-bit Binary Parallel Output Voltage 3-State TTL compatible Output Current ➃ Logic Level "1" –1.1 — — mA Logic Level "0" +3.7 — — mA Output Current ➄ Logic Level "1" — — 16 µA Logic Level "0" — — 16 µA Output Data Delay, Td — 18 30 ns PERFORMANCE Resolution 8 — — Bit Maximum Sampling Rate 20 — — MHz Minimum Sampling Rate — — 0.5 MHz Aperature Delay, TA — 4 — ns Aperature Jitter — 30 — ps Differential Linearity Error — ±0.3 ±0.5 LSB Integral Linearity Error — +0.5 +1.3 LSB Differential Gain Error ➅ — 1 — % Differential Phase Error ➅ — 0.5 — deg POWER REQUIREMENTS Min. Typ. Max. Units Power Supply (+AVS, +DVS) +4.75 +5.0 +5.25 Volts I A GND - D GND I — — 100 mV Power Supply Current — 12 17 mA Power Dissipation — 60 85 mW Physical/Environmental Operating Temp. Range –40 to +85°C Storage Temp. Range –55 to +150°C Package Type ADC-305-1 24-pin Plastic DIP ADC-305-3 24-pin Plastic SOP Weight ADC-305-1 2.0 grams ADC-305-3 0.3 grams Footnotes: ➀ See Technical Note 4 ➁ Short VRB (pin 23) to VRBS (pin 22). Short V RT (pin 17) to VRTS (pin 16). ➂ Short VRB (pin 23) to A GND. Short V RT (pin 17) to VRTS (pin 16). ➃ OE=OV, VOH=+DVS–0.5V, V OL=+0.4V ➄ OE=+DVS, VOH=+DVS, VOL=0V ➅ NTSC 40IRE mode ramp, 14.3MHz sampling PARAMETERS MIN MAX UNITS Power Supply Voltage (+AVS, +DVS) –0.5 +7 Volts Analog Input Voltage (VIN) –0.5 +AVS +0.5 Volts Reference Input Voltage (VRT, VRB) –0.5 +AVS +0.5 Volts Digital Input Voltage (VIH, VIL) –0.5 +DVS +0.5 Volts Digital Output Voltage (VOH, VOL) –0.5 +DVS +0.5 Volts ADC-305 8-Bit, 20MHz CMOS A/D Converters MDA_ADC-305.B01 Page 2 of 6 Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000www.murata-ps.com

Figure 4. Timing Chart

Figure 5. Typical Connection Diagram Figure 6. Typical Performance Curves

10 Supply Current

Differential Linearity Error vs.

ORDERING INFORMATION

ADC-305-1 24-Pin Plastic DIP 400 mil ADC-305-3 24-Pin Plastic SOP 300 mil ADC-305-1 24-Pin DIP (Plastic) 400mil 2.0g ADC-305-1 1.195 ±0.010 (30.35 .±0.25) 0.020 ±0.004 (0.50 ±0.10) 0.100 TYP. (2.54) 0.047 ±0.006 (1.20 ±0.15) 0.152 ±0.010 (3.85 ±0.25) 0.118 MIN. (3.00 MIN.) 0° to 15° 0.011 ±0.003 (0.28 ±0.08) 0.339 ±0.008 (8.60 ±0.20) 0.400 (10.16) SEATING PLANE 0.020 MIN. (0.50 MIN.) ADC-305-3 24-Pin SOP (Plastic) 300mil 0.3g ADC-305-3 0.018 ± 0.004 (0.45 ± 0.10) 0.078 ±0.011 (1.97 ±0.28) 0.213 ±0.008 (5.40 ±0.20) 0.272 (6.90) 0.009 ±0.003 (0.23 ±0.08) 0.050 TYP. (1.27) 0.020 ±0.008 (0.50 ±0.20) 0.596 ±0.010 (15.15 ±0.25) 0.007 ±0.005 (0.18 ±0.13) 0.307 ±0.012 (7.80 ±0.30) ADC-305 8-Bit, 20MHz CMOS A/D Converters MDA_ADC-305.B01 Page 6 of 6 Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. © 2009 Murata Power Solutions, Inc. USA: Mansfi eld (MA), Tel: (508) 339-3000, email: sales@murata-ps.com Canada: Toronto, Tel: (866) 740-1232, email: toronto@murata-ps.com UK: Milton Keynes, Tel: +44 (0)1908 615232, email: mk@murata-ps.com France: Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: france@murata-ps.com Germany: München, Tel: +49 (0)89-544334-0, email: munich@murata-ps.com Japan: Tokyo, Tel: 3-3779-1031, email: sales_tokyo@murata-ps.com Osaka, Tel: 6-6354-2025, email: sales_osaka@murata-ps.com China: Shanghai, Tel: +86 215 027 3678, email: shanghai@murata-ps.com Guangzhou, Tel: +86 208 221 8066, email: guangzhou@murata-ps.com Singapore: Parkway Centre, Tel: +65 6348 9096, email: singapore@murata-ps.com Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 www.murata-ps.com email: sales@murata-ps.com ISO 9001 and 14001 REGISTERED Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000www.murata-ps.com 12/30/08