ADBT1001

ADBT1001 (Rev.0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 49

Technical content

4-Channel AFE, Digital Controller, and PWM for Battery Formation and Testing Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Precise measurement of the voltage and current ►4 PWM control channels up to 16 bits (effective) resolution ►Selectable synchronous and asynchronous rectifier operation ►Programmable dead time compensation ►Programmable switching frequency from 62.5 kHz to 500 kHz in powers of 2 steps ►Multiphase operation ►Interchip digital current sharing ►Interchip frequency synchronization ►Digital control loop ►Programmable PID loop filters ►Fast dc bus voltage feedforward ►Integrated spectrum analysis per channel ►Measure load impedance ►SPI port control and status interface ►Host interrupt on programmable status changes ►CC, CV, CP, and CR operating modes ►15-bit setpoint resolution ►Input and output inrush current protection ►External NTC thermistor temperature sensing ►Internal die temperature measurement ►User calibration of input voltages and currents ►0°C to 85°C operation

APPLICATIONS

►Battery formation and testing ►High efficiency battery test systems with recycle capability ►Battery conditioning (charging and discharging) systems GENERAL DESCRIPTION The ADBT1001 is a flexible, feature rich digital controller that tar- gets high volume battery testing and formation manufacturing and precision battery test instrumentation applications. The ADBT1001 is optimized for minimal component count, maximum flexibility, and minimum design time. Features include differential remote voltage sense, current sense, pulse-width modulation (PWM) generation, frequency synchronization, overvoltage protection (OVP), and cur- rent sharing. Programmable protection features include overcurrent protection (OCP), OVP limiting, and external overtemperature pro- tection (OTP). Parameters can be programmed over the serial peripheral interface (SPI), providing extensive programming of the integrated loop filter, PWM signal timing, and soft start timing. The SPI provides access to the many monitoring and system test functions. Reliability is improved through a built-in checksum and programmable protection circuits. A comprehensive graphical user interface (GUI) is provided for simple system and channel configuration and programming of the safety features. The ADBT1001 is available in a 100-lead LQFP_EP. TYPICAL APPLICATION DIAGRAM Figure 1.

analog.com Rev. 0 | 2 of 49 Analog Front End and Controller Supports Coulombic Efficiency Measurement..20

REVISION HISTORY

6/2021—Revision 0: Initial Version

analog.com Rev. 0 | 3 of 49 AHVDD = 15 V, AHVSS = −15 V, VDDIO = AVDD = DVDD = 3.3 V, and TA = 0°C to 85°C, unless otherwise noted. ANALOG FRONT END AND CONTROLLER SPECIFICATIONS Table 1. Parameter Test Conditions/CommentsMin Typ Max Unit CURRENT SENSE CHANNEL Gain 40 V/V Gain Error Output voltage (VOUT) =±2 V 0.2 % Gain Drift 7 ppm/°C System Input Offset Voltage1 −10 +10 LSB System Input Offset Voltage Drift RTI 0.235 LSB/°C Input Bias Current VICM = reference voltage (VREF)/2 30 500 nA Input Differential Voltage Range −62.5 +62.5 mV Input Common-Mode Voltage Range AHVSS + 5 AHVDD − 5 V Differential Input Impedance By design 24 kΩ Common-Mode Input Impedance By design 246 kΩ Input Resistance Both input pins 492 kΩ Common-Mode Rejection Ratio (CMRR) 100 110 dB CMRR Drift 0.05 ppm/°C Small Signal −3 dB Bandwidth (Gain = 40)2 TA = 25°C, VOUT = 100 mV p-p 600 kHz Power Supply Rejection Ratio (PSRR) Supply voltage (Vs) = ±5 V to ±18 V120 dB Slew Rate VOUT = ±2 V 0.6 V/μs Readout Data Signal-to-Noise Ratio (SNR)MAF3 = 16, FIR4 on Update Rate5 31.25 kHz (OSR = 32) 78 dB 15.625 kHz (OSR = 64) 81 dB 7.8125 kHz (OSR = 128) 84 dB 3.90625 kHz (OSR = 256) 87 dB Full-Scale Input Range −60 +60 mV VOLTAGE SENSE AND CAPACITOR VOLTAGE SENSE CHANNEL Gain 0.5 V/V Gain Error VOUT = ±2 V 0.2 % Gain Drift 10 ppm/°C System Input Offset Voltage1 −10 +10 LSB Offset Voltage Drift 0.235 LSB/°C Input Common-Mode Voltage Range AHVSS + 5 AHVDD − 5 V Differential Input Impedance By design 0.85 1 MΩ Common-Mode Input Impedance By design 375 kΩ Input Resistance Noninverting pin 750 kΩ Inverting pin 375 kΩ Small Signal −3 dB Bandwidth (G = 0.5)6 TA = 25°C, VOUT = 100 mV p-p 200 kHz CMRR BVx_x 80 90 dB CVS_x 78 90 dB

analog.com Rev. 0 | 4 of 49 Table 1. Parameter Test Conditions/CommentsMin Typ Max Unit CMRR Drift BVx_x 0.235 ppm/°C CVS_x 3 ppm/°C PSRR 100 120 dB Slew Rate 0.15 V/μs Power Dissipation 30 mW Readout Data SNR MAF = 16, FIR on Update Rate 31.25 kHz (OSR = 32) 91 dB 15.625 kHz (OSR = 64) 92 dB 7.8125 kHz (OSR = 128) 93 dB 3.90625 kHz (OSR = 256) 93 dB Full-Scale Input Range −4.8 +4.8 V BATTERY CURRENT AND VOLTAGE ADCSVREF = 2.5 V SNR 1 kHz sine wave at 80% full scale 82 dB Signal-to-Noise-and-Distortion (SINAD) Ratio 82 dB Resolution 16 Bits Differential Nonlinearity (DNL)7, 8 −1 +1 LSB Integral Nonlinearity (INL) Internal voltage reference −6 +6 LSB Sampling Rate 1 MHz/Channel VOLTAGE REFERENCE (INTERNAL) Voltage Range 2.495 2.500 2.505 V Temperature Coefficient 7 11 ppm/°C RMS Noise REFCAP = 1 μF 7 μV rms PULSE-WIDTH MODULATION (PWM) External CLK = 16 MHz Resolution 16 Bits Switching Frequency fSW 62.5 500 kHz Programmable Dead Time Minimum 0 ns Maximum 992.2 ns Dead Time Resolution9 7.8125 ns Delay from External SYNC (Programmable)Minimum10 0 µs Maximum at fSW = 62.5 kHz11 16 µs Delay Resolution 7.8125 ns Effective Phase Shift Resolution fSW = 62.5 kHz 0.176 Degrees fSW = 125 kHz 0.352 Degrees fSW = 250 kHz 0.703 Degrees fSW = 500 kHz 1.406 Degrees CHANNEL AC PERFORMANCE Loop Bandwidth (Cross over Frequency) 10 50 kHz Constant Current (CC) to Constant Voltage (CV) Transition Time fSW = 500 kHz 2 μs fSW = 62.5 kHz 16 μs Channel to Channel Isolation 96 dB Intrachannel Isolation 90 dB Current and Voltage Readout Rate12 Minimum OSR13 31,250 Samples/sec Maximum OSR 15.26 Samples/sec Output Data Resolution 18 Bits

analog.com Rev. 0 | 5 of 49 Table 1. Parameter Test Conditions/CommentsMin Typ Max Unit AUXILIARY ADC Resolution (Effective) 12 Bits Sampling Rate DC bus monitor disabled 100,000 Samples/sec DC bus monitor enabled 50,000 Samples/sec Input Voltage Range14 0.1 2.4 V Unity-Gain Offset −1 +1 LSB Unity-Gain Offset Drift 0.02 LSB/°C Current Excitation (4-Bit Programmable) Minimum 0 μA Maximum 750 μA Resolution 50 μA LOGIC INPUTS (SPI_CS, SPI_SCK, SPI_SDIO, SPI_SDO, FAULT_x, GPIOx, AND HW_IRQ) Hysteresis = 600 mV Input Voltage High (VIH) VDDIO × 0.8 V Input Voltage Low (VIL) VDDIO × 0.2 V Input Current High (IIH) VIN = VDDIO −1 μA Input Current Low (IIL) VIN = DVSS 1 μA Input Pull-Down Current (HW_IRQ Only) 15 115 μA Input Capacitance 4 pF LOGIC OPEN-DRAIN OUTPUTS (SPI_SDIO, SPI_SDO, AND HW_IRQ) 1 mA load Output Low Voltage (VOL) 0.4 V Output High Leakage Current (IOH) ±0.1 ±1.0 μA LOGIC OUTPUTS (GPIO) 1 mA load Output Low Voltage (VOL) 0.4 V Output High Leakage Current (IOH) ±0.1 ±1.0 μA Output High Voltage (VOH) VDDIO = 3.0 V 3 V VDDIO = 3.3 V 3.3 V VDDIO = 3.6 V 3.6 V Slew Rate15 Default settings Falling Edge 5.2 ns Rising Edge 4 ns Internal Oscillator Frequency 16 MHz External Oscillator Frequency 16 MHz Power Supplies AHVDD 4.5 30.7 V Quiescent Current Active and standby 3 4.2 mA AHVSS −26 −4.5 V Active and standby 4 6 mA High Voltage Supply Range (AHVDD to AHVSS) 10.6 36 V AVDD 3 3.3 3.6 V Active 40 47 mA Standby 3.6 4.5 mA AVSS 0 V VDDIO 3.3 V Active and standby 2 6 μA VDDDRV 3.3 V Active 4.6 4.8 mA Standby 26 30 μA

analog.com Rev. 0 | 6 of 49 Table 1. Parameter Test Conditions/CommentsMin Typ Max Unit DVDD 3.3 V Active 21 22 mA Standby 4.8 5.2 mA Power Dissipation AHVDD AHVDD = 12 V, active and standby 50.4 mW AHVSS AHVSS = −12 V, active and standby 63.6 mW VDDIO Active and standby 19.8 μW AVDD Active 155 mW Standby 14.9 mW DVDD Active 72.6 mW Standby 17.2 mW VDDDRV Active 15.8 mW Standby 99 μW PWM DRIVE LOGIC DLx and DHx Drive Voltage16 PWM_DRV = 0 VOH 0 mA load 3 3.29 3.3 V 15 mA load 2.6 2.8 2.9 V VOL 0 mA load 17 25 mV 15 mA load 0.6 0.8 1 V DL_x and DH_x Sink Resistance PWM_DRV = 0 10 23 40 Ω PWM_DRV = 15 1.8 2.6 5 Ω DL_x and DH_x Source Resistance PWM_DRV = 0 30 41 55 Ω PWM_DRV = 15 2.2 3.2 5.1 Ω Internal Pull-Down Resistance 1 MΩ Drive Capacitive Load 10 100 pF 1 Factory calibration after ADC. 2 Bandwidth is analog only. The readout data bandwidth is limited by the selected over sampling rate (OSR). 3 The moving average filter (MAF) is a 3-bit field in the MAF_CFG register (one per channel). The default value is 8. 4 The finite impulse response (FIR) filter in the readout filter is not bypassed (default). 5 The readout filter update rate is selected in a 5-bit field in the DSP_READOUT_FILT_CFG register. 6 The bandwidth is analog only. The readout data bandwidth is limited by the selected OSR. 7 Guaranteed by design. 8 No missing codes. 9 For sync mode only. 10 CHANNEL_A_PHASE = 0x000 in the PMU_CHANNEL CFG1 register. 11 The 11-bit CHANNEL_A_PHASE in the PMU_CHANNEL_CFG1 register = 0x07FF and is the same for other channels. 12 The readout update rate is set in a 5-bit field in the DSP_READOUT_FILT_CFG register. There is one per channel. 13 Minimum OSR is based on the maximum readout rate of the current and voltage data for all four channels. 14 Based on 2.5 V nominal VREF. 15 The output pins (SPI_SDIO, SPI_SDO, GPIOx, EXTCLKIO, and HW_IRQ) have xxx_PAD_CFG registers with a 3-bit xxx_SLEW bitfield. The default is 0x7, which is the fastest slew rate. 16 PWM_DRV is a 4-bit field in the PWM_CFG1 channel register.

Table 2. SPI Bus Timing Figure 2. 3-Wire SPI Bus Timing Diagram

ing conditions for extended periods may affect product reliability. Table 4. Thermal Resistance the EE-352 Engineer-to-Engineer Note. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 5. ADBT1001, 100-Lead LQFP_EP

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions 3 CVS_A Channel A Capacitor Voltage Sense Input. 4 BVN_A Channel A Voltage Sense Negative Input. 5 BVP_A Channel A Voltage Sense Positive Input. 6 ISN_A Channel A Current Sense Negative Input. 7 ISP_A Channel A Current Sense Positive Input. 8 ISP_B Channel B Current Sense Positive Input. 9 ISN_B Channel B Current Sense Negative Input. 10 BVP_B Channel B Voltage Sense Positive Input. 11 BVN_B Channel B Voltage Sense Negative Input. 12 CVS_B Channel B Capacitor Voltage Sense Input. 13 AHVDD AFE Positive Supply. 14 AHVSS AFE Negative Supply. Ensure AVDD is applied before applying AHVSS. 15 CVS_C Channel C Capacitor Voltage Sense Input. 16 BVN_C Channel C Voltage Sense Negative Input. 17 BVP_C Channel C Voltage Sense Positive Input. 18 ISN_C Channel C Current Sense Negative Input. 19 ISP_C Channel C Current Sense Positive Input. 20 ISP_D Channel D Current Sense Positive Input. 21 ISN_D Channel D Current Sense Negative Input. 22 BVP_D Channel D Voltage Sense Positive Input. 23 BVN_D Channel D Voltage Sense Negative Input. 24 CVS_D Channel D Capacitor Voltage Sense Input. 29 DH_D PWM Drive High, Channel D. 30 DL_D PWM Drive Low, Channel D. 31 VDDDRV PWM Driver Supply.

32 DH_C PWM Drive High, Channel C

33 DL_C PWM Drive Low, Channel C. 34 DH_B PWM Drive High, Channel B. 35 DL_B PWM Drive Low, Channel B. 36 VDDDRV PWM Driver Supply. 37 DH_A PWM Drive High, Channel A. 38 DL_A PWM Drive Low, Channel A. 39 DVDD_CAP Digital Supply Source Capacitor. Connect a 10 μF decoupling capacitor from DVDD_CAP to DVSS. 40 DVDD Digital Supply Source, 3.3 V Typical. 42 AVDD Analog Supply Source, 3.3 V Typical. Ensure AVDD is applied before applying AHVSS. 43 AVSS Analog Supply Return. 44 EXTCLKIO External Oscillator Input and Clock Output. 45 DVDD_CAP Digital Supply Source Capacitor. Connect a 10 μF decoupling capacitor from DVDD_CAP to DVSS. 46 DVSS Digital Supply Return. 48 XTALP External Crystal High-Side Excitation Pin. 49 XTALN External Crystal Low-Side Excitation Pin.

50 AVSS Analog Supply Return. 52 AIN_COM Analog Input, ADC Common. 53 AIN0 Analog Input, ADC Channel 0. 54 AIN1 Analog Input, ADC Channel 1. 55 AIN2 Analog Input, ADC Channel 2. 56 AIN3 Analog Input, ADC Channel 3. 57 AIN4 Analog Input, ADC Channel 4. 58 AIN5 Analog Input, ADC Channel 5. 59 AIN6 Analog Input, ADC Channel 6. 60 AIN7 Analog Input, ADC Channel 7. 61 AVSS Analog Power Return. 62 REFCAP Internal Reference Capacitor. 63 REFGND Internal Reference Ground. 64 REFIOGND Ground for Reference Input and Output. 65 REFIO Reference Input and Output. Connect a 10 μF from REFIO to AVSS. 66 AVDD Analog Power Supply. Ensure AVDD is applied before applying AHVSS. 67 AVSS Analog Power Return. 68 FAULT_D Fault Detect Input, PWM Channel D Shutdown. Active low. 69 FAULT_C Fault Detect Input, PWM Channel C Shutdown. Active low. 70 FAULT_B Fault Detect Input, PWM Channel B Shutdown. Active low. 71 FAULT_A Fault Detect Input, PWM Channel A Shutdown. Active low. 72 RESET Chip Reset. Active low. 73 GPIO0 General-Purpose Digital Input and Output 0. 74 GPIO1 General-Purpose Digital Input and Output 1. 75 VDDIO Input and Output Supply. 76 VDDIO Input and Output Supply. 77 GPIO2 General-Purpose Digital Input and Output 2. 78 GPIO3 General-Purpose Digital Input and Output 3. 79 GPIO4 General-Purpose Digital Input and Output 4. 80 GPIO5 General-Purpose Digital Input and Output 5. 81 GPIO6 General-Purpose Digital Input and Output 6. 82 GPIO7 General-Purpose Digital Input and Output 7. 83 GPIO8 General-Purpose Digital Input and Output 8. 84 GPIO9 General-Purpose Digital Input and Output 9. 85 GPIO10 General-Purpose Digital Input and Output 10. 86 AVDD_CAP Analog Power Return Capacitor. Connect a 10 μF decoupling capacitor from AVDD_CAP to AVSS. 87 AVSS Analog Power Return. 88 AVDD Analog Power Supply. Ensure AVDD is applied before applying AHVSS. 89 VDDIO Digital Input and Output Supply. 90 GPIO11 General-Purpose Digital Input and Output 11. 91 GPIO12 General-Purpose Digital Input and Output 12. 92 GPIO13 General-Purpose Digital Input and Output 13. 93 GPIO14 General-Purpose Digital Input and Output 14. 94 GPIO15 General-Purpose Digital Input and Output 15. 95 HW_IRQ Host Interrupt Request. Active low. 96 SPI_SDO Host SPI Master Input, Slave Output (MISO). 97 SPI_SDIO Host SPI Master Output, Slave Input (MOSI) or Bidirectional.

99 SPI_CS Host SPI Select. Active low. 100 VDDIO Input and Output Supply. EPAD DVSS Exposed Pad. DVSS for DVDD, VDDIO, and VDDDRV.

8 auxiliary ADC channels and 16 GPIOx pins. Figure 34. Functional Block Diagram

analog.com Rev. 0 | 19 of 49 ANALOG FRONT END Each channel has a precision current sense differential amplifier with a fixed gain of 40 and a precision voltage sense differential amplifier with a fixed gain of 0.5. A pair of simultaneous sampling ADCs converts the conditioned current and voltage signals to 12-bit digital representations before transferring the signals to the digital controller. DIGITAL CONTROLLER A finite state machine (FSM)-based proportional integral derivative (PID) controller provides digital loop control. The controller has user-programmable filter coefficients for control loop compensation. Current and voltage setpoints are register based and are configured by the user over a host SPI. Power and resistance setpoints are al- so available. Separate current and voltage control loops support CC and CV, as well as constant power (CP) and constant resistance (CR) operating modes. The controller output is used to command the duty cycle of an 16-bit digital PWM. Operation of the controller is discussed in the Sequencer Operation Example section. HOST SPI Control is provided by an external host through a 3-wire or a 4-wire SPI. Use the SPI_CS, SPI_SCK, and SPI_SDIO pins for the 3-wire SPI and use the SPI_CS, SPI_SCK, SPI_SDIO, and SPI_SDO pins for the 4-wire SPI. This interface is used to configure the controller through the memory mapped registers. These registers are introduced in Table 11. HOST INTERRUPT REQUEST Use the HW_IRQ signal, HW_IRQ, to provide interrupt requests to the host. Use the SPI port accessible set of registers to select which internal events generate host interrupt requests. Event op- tions include system errors, channel data ready, channel voltage and current over limit detection, channel operation complete, and auxiliary ADC high and low threshold detection. CLOCKING The ADBT1001 derives all internal clocking from either an internal oscillator, an external 16 MHz crystal, or an external 16 MHz oscillator. Phase interleaving can be configured to help minimize input ripple as well as output ripple when channels are paralleled for greater current capacity. Additionally, multiple devices can be synchronized together, which enables parallel channel operation in multiples of four. The master device provides a 16 MHz clock on the EXTCLKIO pin, and this clock signal is an input at the EXTCLKIO pin on the slave device. GPIOX PINS There are 16 GPIOx pins on the ADBT1001. Typical GPIOx pin usage includes controlling the dc bus and battery isolation switches or getting the digital inputs from the digital sources. The GPIOx pins are user-programmable through the following set of memory mapped registers. The GPIOx pins used for the battery isolation switches can be assigned in the global registers for sequencer control. This assigning facilitates the precharge operation at start- up that prevents reverse current when connecting to the battery. Additionally, the GPIOx pins can be configured to provide interde- vice digital current sharing communications when using multiple ADBT1001 devices in parallel. The GPIO_PAD_CFG register is used to configure the GPIOx pin parameters including slew rate, hysteresis, and drive strength. The default bitfields, GPIO_SLEW, GPIO_HYST, and GPIO_DRV, have default settings of 5 ns, 600 mV, and 10 Ω, respectively. These default values are typically acceptable for most applications. The GPIOx pins can be individually configured as inputs or outputs by using the 16-bit GPIO_IEN_CFG and GPIO_OEN_CFG regis- ters, respectively. Bits[15:0] in each register corresponds to GPIO0 through GPIO15. When configured as standard GPIOx pins, there are five 16-bit registers that can interact with these pins. In each case, Bit 0 corresponds to GPIO0, and Bit 15 corresponds to GPIO15. The GPIO_READ register can be read to see the state of each GPIOx pin, and the GPIO_WRITE register can be written to set the output pins as 1 or 0. The GPIO_SET, GPIO_CLEAR, and GPIO_TOG- GLE registers set, clear, or toggle, respectively, the GPIOx pins that are set as standard GPIOx pin outputs. In addition to basic user-controlled GPIO operations, the GPIOx pins can be configured for specific operation modes. This configura- tion is done through the GPIO_MODE_CFG0 (for GPIO0 through GPIO7 pins) and the GPIO_MODE_CFG1 (for GPIO8 through GPIO15 pins) registers. All GPIOx pins can be configured as either standard GPIO input and output functions or can be controlled by the sequencer. The latter is used to control a battery isolation switch that is used as part of the precharge operation. Additional options for GPIO0 through GPIO7 are unique functions used for interdevice communications when multiple devices are used in parallel. When a GPIOx pin is controlled by the sequencer in a particular channel, there is also a channel GPIO_CFG register where the

4 LSBs are used to select which GPIOx pin is controlled by the

sequencer of the channel. AUXILIARY ADC An 8-channel, 12-bit ADC is available for dedicated (for example, internal temperature) or general-purpose external measurements. Note that four of the channels have optional current sources for use with the external thermistors for temperature measurement. The dc bus voltage can also be sensed on an ADC channel and used in a feedforward control mechanism to reduce the effect of dc bus transients. All auxiliary ADC operations are user configurable.

analog.com Rev. 0 | 20 of 49 SUPPORTS COULOMBIC EFFICIENCY MEASUREMENT Coulombic efficiency is a ratio of the capacity during discharge to the capacity during charge. The device supports this efficiency through the integration of current over time. The integration results are accessible through a set of registers. SUPPORTS PRECHARGE OPERATION When connecting to a cell before a new formation or test cycle, there is a possibility of having a large inrush current from the battery to the discharged output stage. The device allows a user to precharge the output stage before connecting to the cell, which is described in additional detail in the Precharge Operation section.

from a user point of view: manual, semiautomatic, and automatic. instruction until the host CPU services the interrupt. required fields for the instruction to execute as expected. Figure 35. Manual Sequencing Mode

NEXT_INSTR_READY bit in the register map. the register map for debug purposes. payloads using 16-bit words. A fixed header is a one word length. GUI is available to help users code instruction memory. Figure 36. Automatic Sequencing Mode

analog.com Rev. 0 | 23 of 49 CHARGE AND DISCHARGE INSTRUCTION MODES The device provides two PID control loops per channel, the current loop and the voltage loop. Only one PID control loop is in control at any given time. The PID control loop in control is the one with the smallest error between the filtered ADC sample and the target setpoint. Note that, VMEAS is the measurement on the V channel. There are four independent bits to configure how the control loop behaves: ►CC, where the I channel is in control, and the loop target is set to the current setpoint (ISET). ►CV, where the V channel is in control, and the loop target is set to the voltage setpoint (VSET). ►CP, where the I channel is in control, and the loop target is set to the power setpoint (PSET/VMEAS). ►CR, where the I channel is in control, and the loop target is set to the resistance setpoint (VMEAS × GSET). There are 16 possible mode combinations or 32 including whether the loop is charging or discharging the battery. The VSET bits (15 LSBs in Register SEQ_NEXT_VSET) can refer to either the absolute value or a delta value based on VMEAS, as determined by the VSET_DELTA bit (MSB in Register SEQ_NEXT_VSET). The main purpose of the delta is to allow the programming of a VSET value at some offset from the last VMEAS value. The start-up (that is, precharge) procedure uses the VSET_DELTA bit with zero offset to get to the current battery voltage value. The precharge operation is discussed in the Precharge Operation section. CHARGE AND DISCHARGE INSTRUCTION LIMITS There are three 16-bit programmable fields that represent instruc- tion limits. VLIMIT is associated with the CC mode of operation and can be used to signal the end point of a CC charge or discharge. ILIMIT is associated with the CV mode of operation and is typically used to signal the end point for a CV charge or discharge operation. TLIMIT can be used to either set the duration of an instruction or to set an error overlimit when an instruction should have completed earlier. VLIMIT The following details the operation of the VLIMIT bits (Register SEQ_VLIMIT): ►The VLIMIT threshold flags the instruction end on a charge or discharge instruction with CC mode. ►In an instruction with both the CV and CC modes, VLIMIT avoids early instruction termination by not letting any crossing through ILIMIT (Bits[14:0], Register SEQ_ILIMIT) to end the instruction before VLIMIT is crossed. In addition, the V channel PID is not allowed to take control until this threshold is reached. ►If the VLIMIT_DELTA (MSB) bit is cleared, the VLIMIT bits, Bits[14:0], represent an absolute positive voltage. ►If the VLIMIT_DELTA bit is set, the limit is understood as an increment (charge) or a decrement (discharge) from the first VMEAS value read during the execution of an instruction. The main purpose of this bit is to set this limit dynamically without having to read the ADC value before programming this instruction. This bit is related to the VSET_DELTA bit (Register SEQ_VSET). ►The VLIMIT is reached when the measured voltage is higher or equal to the VLIMIT threshold with a charge instruction. ►The VLIMIT is reached when the measured voltage is lower or equal to the VLIMIT threshold with a discharge instruction. ILIMIT The following details the operation of the ILIMIT bits (Register SEQ_ILIMIT): ►The ILIMIT threshold flags the instruction end on a charge or discharge instruction with the CV mode active. ►The ILIMIT bits, Bits[14:0], always represent the absolute current magnitude. ►The ILIMIT is reached when the measured current is lower or equal to the ILIMIT threshold with a charge instruction. A reverse current while charging triggers the limit. ►The ILIMIT is reached when the measured current is higher or equal to the negative value of the ILIMIT threshold with a battery discharge instruction. A reverse current while discharging triggers the limit. TLIMIT The following details the usage of the NEXT_TLIMIT_SCALE and NEXT_TLIMIT_VAL bitfields (Register SEQ_NEXT_TLIMIT): ►TLIMIT is the target for a timeout trigger event. The trigger is asserted when the elapsed time is equal or greater than TLIMIT. ►A timeout trigger event can be used for either an error, if an instruction must terminate through another limit, or for a timed execution of an instruction (no error). ►The SEQ_NEXT_TLIMIT, Bits[15:0], are encoded as the following: ►NEXT_TLIMIT_SCALE, Bits[15:14] are the time units, 3 = minutes, 2 = minutes, 1 = milliseconds, and 0 = microseconds. ►NEXT_TLIMIT_VAL, Bits[13:0] are the integer value. ►The time units set the resolution and the maximum time value. On a scale of minutes, the resolution is minutes, and the maximum time is 11.3 days. On a scale of microseconds, the resolution is microseconds, and the maximum time is approx- imately 16.5 ms.

►VLIMIT = 0 causes a CC operation to terminate immediately. transformed into a ramp waveform. within the PID and PWM update rate. charge and discharge instruction for CV ramps VSET. Case section and the Four Channels in Parallel Use Case section. Groups of channels working in parallel can span multiple devices. this flag separate from the SEQ_DONE flag for debug purposes. and the start bit resets the SEQ_DONE flag. the flag was not another limit termination or the HALT instruction. overlimit samples for detection. include malformed instruction and division by zero. transition, such as a CC to CV transition. Table 7. Sequencer Flags

NEXT_USER_IRQ bit was executed. CV mode in a CC to CV operation. ►Configuration of channels for parallel operation. ►Interrupt controller settings. ►Auxiliary ADC configuration and readout. controllable per instruction. describing the lower 8 bits first and the higher 8 bits second. Manual sequencing mode provides a limited set of instructions. not care. It is recommended to write 0s in these bits. Bits[1:0] of the header define the instruction, INST_TYPE. Instructions include rest, stop, charge, or discharge. of operation for the charge or the discharge of the battery. ging any voltage or current measurement overlimits. where either ISET or VSET targets are ramped. GPIOx that this GPIO_VAL bit controls. value is not 0, the program jumps to the first instruction of the loop. ment is taken across the BVP_x and BVN_x pins. ment is taken across the CVS_x and BVN_x pins. the charge or discharge instructions.

Table 8. Instruction Header

Halt is coded with INST_TYPE = 2’b00. There is no payload associated with the halt instruction. Rest is coded with INST_TYPE = 2’b01. the end of the list of instructions that get repeated in the loop. Table 9. Rest Instruction Payload

controls the charge or discharge of the battery. The payload depends on which bitfields are enabled in the header. VSET are based on the last V channel measurement. Table 10. Charge and Discharge Instruction Payload 1 See the Instruction Set Architecture section and Table 8 for additional information on this row. determines the end of the list of instructions that get repeated in the loop.

Table 11. Register Block Summary ters used to configure the SPI port and communications protocol. external temperature measurement. Table 12. SPI_SLV_CTRL (SPI_SLV_CTRL) Register Summary Table 13. SYSTEM_CTRL (MISC_CTRL_DIG) Register Summary

Table 14. ADC_CTRL (ADC_COMMON_SETTINGS) Register Summary

Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary

1 MSBs Register

1 LSBs Register

2 MSBs Register

2 LSBs Register

3 MSBs Register

3 LSBs Register

4 MSBs Register

4 LSBs Register

5 MSBs Register

5 LSBs Register

0 Register

1 Register

2 Register

3 Register

maximum clock rate is 16 MHz. MSB first is the default mode, but LSB first can also be configured. range of consecutive register addresses. The instruction phase is performed in the first 16-bit word transfer. word 16-bit transfers through the total number requested. Figure 38. Basic 4-Wire Read Operation

sequential register addresses. Figure 39. Basic 4-Wire Write Operation

analog.com Rev. 0 | 44 of 49 CALIBRATION Facilitate System Calibration The device supports a means to facilitate a system calibration, which includes registers for each ADC channel to include offset and gain scaling calibration data. The user can provide external stimulus, measure the results, and calculate the requisite offset and gain scaling values over several temperature points. These values can then be user programmed into the ADC calibration registers. These values can then be used to compensate for system errors over a specific temperature range. DIAGNOSTICS Support DC Internal Resistance (DCIR) Measurement DCIR measurement is supported indirectly via accurate measure- ment of the battery voltage. The external controller must store data samples, monitor current step changes, determine when the RC time constant is complete, and estimate the voltage difference. DC I R = Δ V / Δ I (1) During this measurement, the output data rate can be increased to capture the transient response. OPERATING USE CASES 4-Channel Independent Use Case For the 4-channel independent use case, each channel conducts a separate and independent measurement of the battery voltage and current, and has independent control of the same. In addition, each channel has independently programmable voltage and current setpoints.

Figure 40. 4-Channel Independent Use Case

Figure 41. Two Parallel—Two Independent Channels Use Case

master channel current setpoint with ¼ of the total desired current. Figure 42. Four Channels in Parallel Use Case

available via the SPI port and a set of memory mapped registers. Use the VSET bit to control of the output capacitor voltage. Figure 43. Precharge Function Diagram

registered trademarks are the property of their respective owners. Figure 44. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP]