ADBMS6822

ADBMS6821_V01 AD | Alldatasheet

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Technical content

Single/Dual isoSPI Transceiver Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Up to 2 Mbps isolated bidirectional serial data communications ►Drop in compatible: single (ADBMS6821) and dual (ADBMS6822) ►Fully independent dual transceivers (ADBMS6822) ►Simple galvanic isolation using capacitors or transformers ►Bidirectional interface over a single twisted pair ►Supports cable lengths up to 100 meters ►Very low EMI susceptibility and emissions ►LPCM support for ADBMS battery monitors ►Interrupt output for LPCM system wake-up ►4 Mbps unidirectional mode ►Requires no software changes in most SPI systems ►Ultra-low idle current ►Automatic interface wake-up detection ►Operating temperature range: −40°C to +125°C ►3.0 V to 5.5 V isoSPI driver power supply ►1.7 V to 5.5 V interface to microcontrollers ►3.0 V to 30 V input for powering wake-up and monitoring func- tions (12 V battery compatible) ►Available in 32-lead, side solderable LFCSP package ►AEC-Q100 qualified for automotive applications

APPLICATIONS

►Electric and hybrid electric vehicles ►Backup battery systems ►Industrial networking ►Remote sensors TYPICAL APPLICATION CIRCUIT A typical application of the ADBMS6822 in a system with the ADBMS6815 battery monitor is shown in Figure 1. Figure 1. Typical Application Circuit to achieve hundreds of volts of isolation. receiver detect the differential signals. received in the programmed time period. 1 Protected by U.S. patents, including 8,908,779.

Data Sheet ADBMS6821/ADBMS6822 TABLE OF CONTENTS analog.com Rev. B | 2 of 28

REVISION HISTORY

7/2024—Rev. A to Rev. B 1/2024—Revision A: Initial Version

Figure 2. ADBMS6821/ADBMS6822 Functional Block Diagram

Operating junction temperature (TJ) = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 1. Power-Supply Specifications TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 2. LPCM Timeout Specifications

TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 3. XCVRMD and PHAPOL Pin Specifications

4 Mbps unidirectional mode 65 120 kΩ

TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 4. INTR and WAKE Pin Specifications TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 5. Digital Pins DC Specifications

TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 6. isoSPI DC Specifications TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 7. isoSPI Idle/Wake-Up Specifications TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 8. isoSPI Pulse Timing Specifications

TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 9. SPI/isoSPI Timing Specifications (Controller) TJ = −40°C to +125°C, VDDS = 3 V, VDD = VP = 5 V, unless otherwise noted. Table 10. SPI/isoSPI Timing Specifications (Peripheral)

2 Mbps with 1-bit latency transceiver mode145 195 240 ns

(for example, CS2 relative to VDDS2). Table 11. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. Table 12. Thermal Resistance

1 The exposed pad must be connected to the GND plane for proper thermal

2 Board layout impacts thermal characteristics such as θJA. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 13. ADBMS6821, 32-Lead LFCSP_SS Table 14. ADBMS6822, 32-Lead LFCSP_SS damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 3. ADBMS6821 Pin Configuration Table 15. ADBMS6821 Pin Function Descriptions 1 MSTR SPI Mode Select. MSTR selects SPI controller mode (connected to VDDS) or peripheral mode (connected to GND). 2 PICO SPI Controller Output (Controller Mode) or Peripheral Input (Peripheral Mode). 3 POCI SPI Controller Input (Controller Mode) or Peripheral Output (Peripheral Mode). 4 SCK SPI Clock Input (Controller) or Output (Peripheral). 5 CS Active Low SPI Chip-Select Input (Controller Mode) or Output (Peripheral Mode). 6 VDDS SPI Power-Supply Input (1.7 V to 5.5 V). 7 INTR LPCM Interrupt Current-Limited Output. 8 WAKE Device Wake-Up State Current-Limited Output or Input. 9 GND Ground. The GND pins must be shorted together external to the IC. 10 IM Isolated Interface Minus Input/Output. 11 IP Isolated Interface Plus Input/Output. 12 VDD isoSPI Power-Supply Input (3.0 V to 5.5 V). 13 VP High Voltage Power-Supply Input (3.0 V to 30 V). 14 PHAPOL Multilevel, Resistor Set SPI PHA/POL Selection Input. 15 RTO Multilevel, Resistor Set LPCM Timeout Selection Input. 16 XCVRMD Multilevel, Resistor Set Transceiver Mode Selection Input. 17 to 32 NIC Not Internally Connected. 33 EP Exposed Pad. Must be connected to GND.

Figure 4. ADBMS6822 Pin Configuration Table 16. ADBMS6822 Pin Function Descriptions or peripheral mode (MSTR and MSTR2 connected to GND). 2, 26 PICO, PICO2 SPI Controller Outputs (Controller Mode) or Peripheral Inputs (Peripheral Mode). 3, 27 POCI, POCI2 SPI Controller Inputs (Controller Mode) or Peripheral Outputs (Peripheral Mode). 4, 28 SCK, SCK2 SPI Clock Inputs (Controller) or Outputs (Peripheral). 5, 29 CS, CS2 Active Low SPI Chip-Select Inputs (Controller Mode) or Outputs (Peripheral Mode). 6, 30 VDDS, VDDS2 SPI Power-Supply Inputs (1.7 V to 5.5 V). 7, 31 INTR, INTR2 LPCM Interrupt Current-Limited Outputs. 8, 32 WAKE, WAKE2 Device Wake-Up State Current-Limited Outputs or Inputs. 9, 17 GND Ground. The GND pins must be shorted together external to the IC. 10, 18 IM, IM2 Isolated Interface Minus Inputs/Outputs. 11, 19 IP, IP2 Isolated Interface Plus Inputs/Outputs. 12, 20 VDD, VDD2 isoSPI Power-Supply Inputs (3.0 V to 5.5 V). 13, 21 VP, VP2 High Voltage Power-Supply Inputs (3.0 V to 30 V). 14, 22 PHAPOL, PHAPOL2 Multilevel, Resistor Set SPI PHA/POL Selection Inputs. 15, 23 RTO, RTO2 Multilevel, Resistor Set LPCM Timeout Selection Inputs. 16, 24 XCVRMD, XCVRMD2 Multilevel, Resistor Set Transceiver Mode Selection Inputs. 33 EP Exposed Pad. Must be connected to GND.

back and forth on twisted pair cables. the first BMS monitor in a daisy chain. one or more peripheral devices. VIP − VIM is between the positive and negative thresholds. criminate between short and long pulses. pulse pair is −VA followed by +VA. Table 17. isoSPI Pulse Types Table 18. Controller Communication Events Table 19. In addition, the peripheral device can transmit a return information, see the isoSPI Interaction and Timing section. Table 19. Peripheral SPI Port Output collisions (for additional information, see the Multidrop section).

transceivers to be paralleled without affecting signal amplitude. Figure 37. Receiver Common-Mode Bias The VDDS power supply pin is used for SPI input or output. SPI port of the connected devices. internally when switching between controller and peripheral mode. modes, configured by the PHAPOL pin. pin state does not occur while the transceiver is in the idle state. The four configuration settings for PHAPOL are shown in Table 20. Table 20. PHAPOL SPI Modes ADBMS battery monitors use SPI Mode 3. to allow enhanced capabilities with different system configurations. (connected to GND or 20 kΩ resistor to GND).

to the ready state to cause the XCVRMD pin state to be detected. Table 21. XCVRMD Pin Transceiver Modes

4 Mbps Unidirectional 100 kΩ resistor to GND

2 Mbps with 1-Bit Latency VDDS

in either controller or peripheral mode. it behaves the same as the standard bidirectional isoSPI mode.

4 Mbps Unidirectional

transmit isoSPI data when configured in peripheral mode.

2 Mbps with 1-Bit Latency

shut down most of the circuitry. receive, but there is no active data transmission on IP and IM. condition is referred to as the active state. Figure 38. isoSPI State Diagram configurations are maintained from the last VDDS power-up. reliable isoSPI communication. down, VP must be >6 V to function in LPCM timeout monitor mode. If high voltage LPCM power is not required, connect VP to VDD. Table 22 provides equations for estimating IVDD/VP in each state. is less than a transceiver configured as a controller.

addressed peripheral device returns data to the controller. Figure 40. Multiple Peripherals on a Single Cable

diagram of an LPCM BMS system is shown in Figure 41. Figure 41. Simplified LPCM BMS heartbeat sequence quickly after initially enabling LPCM operation. has begun and the cell stack is not in an unexpected condition. After the INTR pin is deasserted low, the internal timer is reset to 0. to turn on a power supply to power up the BMS controller. are not active. Therefore, the VDD pin supply is not required. monitors and confirming that the INTR pin indicates the failure. communication with the battery monitors. LPCM measurement periods are shown in Table 23. Table 23. RTO Resistor Selection

1.5 GND or 100 1

the INTR operation, see the LPCM Timeout Monitor section. clamp or a level shifter may be required.

Data Sheet ADBMS6821/ADBMS6822 THEORY OF OPERATION analog.com Rev. B | 25 of 28 Average LPCM Supply Current = I V P L STN + I VD D / V P RD Y _ L PCM × 1 ms / Heartbeat Period (1) Thus, for instance, when VP = 12 V, VDD = 0 V, and heartbeat period = 1 sec, the average LPCM supply current is approximately 12 µA. SPI PINS DURING LPCM When the MSTR pin transitions low to begin LPCM operation, the CS, SCK, and PICO pins of the transceiver cease to operate as input pins and begin to operate as low impedance output pins. The POCI pin ceases to operate as a low impedance output pin and begins to operate as an input pin, which can cause contention if the VDDS supply remains powered and the attached microcontrol- ler continues to drive the CS, SCK, and PICO pins. To prevent contention on these pins, disable the VDDS supply or stop the microcontroller from driving these pins before driving the MSTR pin low.

Data Sheet ADBMS6821/ADBMS6822 APPLICATIONS INFORMATION analog.com Rev. B | 26 of 28 SOFTWARE LAYER The isoSPI physical layer has high immunity to EMI and is not par- ticularly susceptible to bit errors induced by noise. But for optimal results in a high noise environment, implement a software layer that uses an error detection code, for example, a cyclic redundancy check (CRC) or checksum. Error detection codes allow software detection of any bit errors and notify the system to retry the last erroneous serial communication.

Figure 43. 32-Lead Lead Frame Chip-Scale Package [LFCSP_SS]

Data Sheet ADBMS6821/ADBMS6822 OUTLINE DIMENSIONS ©2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. B | 28 of 28 Updated: September 02, 2021 ORDERING GUIDE Model 1, 2, 3, 4, 5 Temperature Range Package Description Packing Quantity Package Option ADBMS6821WCCSZ −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Tray, 490 05-08-7057 ADBMS6821WCCSZ-RL −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Reel, 5000 05-08-7057 ADBMS6822WCCSZ −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Tray, 490 05-08-7057 ADBMS6822WCCSZ-RL −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Reel, 5000 05-08-7057 ADBMS6821CCSZ −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Tray, 490 05-08-7057 ADBMS6821CCSZ-RL −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Reel, 5000 05-08-7057 ADBMS6822CCSZ −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Tray, 490 05-08-7057 ADBMS6822CCSZ-RL −40°C to +125°C 32-Lead Plastic Side Solderable QFN (5 mm × 5 mm)Reel, 5000 05-08-7057 1 W = Qualified for Automotive Applications. 2 C = Temperature Range = −40°C to +125°C. 3 CS = LFCSP-SS 64 Package. 4 Z = RoHS-Compliant Part. 5 RL = Tape and Reel. EVALUATION BOARDS Model1 Description EVAL-ADBMS6822 Evaluation Board 1 Evaluation Board is a RoHS-Compliant Part. AUTOMOTIVE PRODUCTS The ADBMS6821W and ADBMS6822W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models, therefore, designers must review the Specifications section of this data sheet carefully. Only the automotive-grade products shown are available for use in automotive applications. For specific product ordering information and to obtain the specific Automotive Reliability reports for these models, contact the local Analog Devices, Inc., account representative.