ADBMS2950B

Battery Pack Monitor

Document overview

• PDF pages: 97

Technical content

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887- 2356, U.S.A. Tel: 781.935.5565 ©2024 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Battery pack current measurement Buffered analog inputs Continuous operation option Lossless measurement for coulomb counting 1 ms update rate ±0.1% maximum gain error ±1 µV maximum offset Redundant implementation Battery pack voltage measurement Buffered analog inputs Synchronous with current measurement Differential and single-ended mode Redundant implementation 10 additional voltage measurement channels Buffered analog inputs On-demand operation Differential and single-ended mode Redundant implementation Overcurrent detection Triple redundancy with majority voting PWM output options Built-in isoSPI™ interface

2 Mbps isolated serial communications

Capacitor or transformer coupled Daisy-chaining option 4-wire SPI option General-purpose digital IO Six general-purpose outputs (GPOs) Dual threshold read-back of GPOs Four GPIOs configurable as an I2C or SPI controller 48-Lead side-solderable QFN package

APPLICATIONS

The ADBMS2950B is a battery pack monitor for current or voltage sense applications. It measures the current flowing in and out of a battery pack by sensing the voltage drop over a shunt resistor with a very low offset. The ADBMS2950B also detects overcurrent conditions using fast overcurrent analog-to-digital converters (ADCs) with digital threshold comparators and communicate their results through dedicated overcurrent alert lines with minimum delay. It features a total of 12 internally buffered high impedance inputs for measuring voltages from external sensors or resistor- dividers, enabling measurement of pack voltages, temperatures, HV-Link voltages, chassis isolation, and the supervision of the state of contactors and fuses. Six digital outputs (GPOs) supporting open-drain or push-pull can be used to control high voltage transistors to disconnect external resistor-dividers. Four digital general-purpose inputs/outputs (GPIOs) also allow operation as an I 2C or SPI controller interface to address an external electronically erasable programmable read‐only memory (EEPROM) or other serial peripherals. The built-in serial interface of the ADBMS2950B can be configured for SPI or isolated isoSPI communication to the host. An additional isoSPI port allows to connect a daisy-chain of the ADBMS2950B devices, which is optionally extended with the ADBMS6830B cell monitor. Table 1. ADBMS2950B Features Overview

Figure 1. Functional Block Diagram

Rev. 0 | Page 3 of 97 TABLE OF CONTENTS

REVISION HISTORY

Revision 0 | 8/2024 Initial Version

Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V , VREG = 5.0V , ISOMD pin is connected low, unless otherwise noted. Table 2. I1ADC and I2ADC Current ADCs 1 The TME specifications include the ADC's offset, nonlinearity, drift over temperature (gain error), reflow soldering, lifetime, and thermal hysteresis. Table 3. VB1ADC and VB2ADC Battery Voltage ADCs

1 The TME specifications include the ADC's offset, nonlinearity, drift over temperature (gain error), reflow soldering, lifetime, and thermal hysteresis. Table 4. OC1ADC to OC3ADC Overcurrent ADCs 1 The signal transitions arrive by this amount of time earlier on the OCA pin compared to the OCB pin. 2 The TME specifications include the ADC's offset, nonlinearity, drift over temperature (gain error), reflow soldering, lifetime, and thermal hysteresis. Table 5. V1ADC and V2ADC General Purpose Voltage ADCs

1 The TME specifications include the ADC's offset, nonlinearity, drift over temperature (gain error), reflow soldering, lifetime, and thermal hysteresis. Table 6. AUX ADC 1 The TME specifications include the ADC's offset, nonlinearity, drift over temperature (gain error), reflow soldering, lifetime, and thermal hysteresis.

Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V , VREG = 5.0V , ISOMD pin is connected low, unless otherwise noted. Table 7. VREF1, VREF2, and VREF1P25 Specifications in the TME and gain error specifications of the OCxADCs. 3 The VREF2 long-term drift includes variation of VREF2 due to, for example, reflow soldering, lifetime, and thermal hysteresis. 4 This specification covers all variation in VREF2 over temperature and lifetime.

Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V , VREG = 5.0V , ISOMD pin is connected low, unless otherwise noted. Table 8. General Timing Specifications Table 9. General-Purpose Outputs Table 10. General-Purpose Input/Open Drain Outputs Table 11. OC Outputs Table 12. General DC Specifications

calculated from DC measurements. Slower clock rates reduce the supply current. Table 13. Supply Monitors 1 The Min value defines the minimum negative-going reset threshold, and the Max value defines the maximum positive-going reset threshold.

Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V , VREG = 5.0V . ISOMD pin is connected low, unless otherwise noted. Table 14. SPI Interface Specifications meets the setup time requirements of the BMS controller. Figure 2. Timing Diagram of 4-Wire SPI

Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V , VREG = 5.0V . Table 15. isoSPI DC Specifications Table 16. isoSPI Pulse Timing Specifications Figure 3. isoSPI Pulse Timings

Table 17. isoSPI Timing Specifications Figure 4. isoSPI Read Command Timing

Voltages relative to GND, unless otherwise noted. SPI mode (CSB and SCK) or isoSPI mode (IPA and IMA). 2 Positive currents flow into pins, negative currents flow out of pins. enclosure. θJC is the junction-to-case thermal resistance. Table 19. Thermal Resistance

3 Those pins are clamped to VREG through internal diodes, this maximum sum

see the Protection Features section.

Table 20. Pin Function Descriptions 40 VDD S GPO and DRIVE Power-Supply Voltage Input. Bypass this pin to PCB ground plane with a 0.1 μF (or greater) capacitor. Connect to VREG for 5V only supply option. emitter to VREG. Leave floating if unused. For recommended external circuitry, see the Providing DC Power section. 44 GND S Power-Supply Ground. Connect to PCB ground plane. from power ground paths by placement of components and optional slots in the ground plane. and optional slots in the ground plane.

Rev. 0 | Page 15 of 97 Pin No. Mnemonic Type Description 45, 43 VREF1, VREF2 REF Primary (VREF1 = 3.2V typ) and Secondary (VREF2 = 3.0V typ) Reference Voltage Outputs. Bypass each pin with a 1 μF (or greater) capacitor to the PCB ground plane. Avoid common power ground paths between this capacitor's ground connection and the SGND and RGND pin connections by placement of components and optional slots in the ground plane. No DC loads are allowed on those pins. 15 VREF1P25 REF B uffered Reference Voltage Output of 1.25V for driving 10 kΩ T hermistors and Resistor-Dividers. Bypass with a 1 μF capacitor to the PCB ground plane. Avoid common power ground paths between this capacitor's ground connection and the SGND pin connection by placement of components and optional slots in the ground plane. 5, 9 S1A, S2A I For more details, see the Current Sense Inputs section. Connect to PCB ground plane if current sense functionality is unused. 3, 4, 7, 8 I1A, I1B, I2A, I2B I Current and Overcurrent Sense Channel 1/2 Differential Signal Inputs (A: positive, B: negative). For more details, see the Current Sense Inputs section. Connect to the PCB ground plane if current sense functionality is unused. 1, 11 I3A, I3B I Overcurrent Sense Channel 3 Differential Signal Inputs (A: positive, B: negative). For more details, see the Current Sense Inputs section. Connect to the PCB ground plane if current sense functionality is unused. 48, 2, 10, 18, 6, 16 V1, V2, V3, V4, V5, V6 I Voltage Sense Inputs. Pins are internally buffered before being applied to V1ADC and V2ADC to ensure high input impedance and low leakage. Leave floating or connected to the PCB ground plane (preferred) if unused. 12, 14 VBAT1, VBAT2 I Battery Voltage Sense Inputs. VBAT1 and VBAT2 are internally buffered before being applied to VB1ADC and VB2ADC to ensure high input impedance and low leakage. The VBxADC's inputs are configurable between either both differentially VBAT1 to VBAT2 or individual single ended VBAT1 vs. SGND through VB1ADC and VBAT2 vs. SGND through VB2ADC. Leave floating or connected to the PCB ground plane (preferred) if unused. 17, 13 V7, V8 I Voltage Sense Inputs. Pins are internally buffered before being applied to V1ADC to ensure high input impedance and low leakage. Input pins V7, V9 and V8, V10 each can form one redundant input pin -pair. Leave floating or connected to the PCB ground plane (preferred) if unused. 19, 20 V9, V10 I Voltage Sense Inputs. Pins are internally buffered before being applied to V2ADC to ensure high input impedance and low leakage. Input pins V7, V9 and V8, V10 each can form one redundant input pin -pair. Leave floating or connected to the PCB ground plane (preferred) if unused. 28, 29, 30, 31 GPIO1, GPIO2, GPIO3, GPIO4 IO General-Purpose Inputs and Outputs (GPIOs). Pins can be used as digital inputs or digital outputs (open drain). Pins are high impedance during power down and by default after power up/reset. GPIO3 (SDA) and GPIO4 (SCL) can be used as an I 2C controller port. GPIO1 (SDIM), GPIO2 (CSBM), GPIO3 (SDOM), and GPIO4 (SCKM) can be used as an SPI controller port. Shared data-in/-out (SDIOM) through GPIO3 only (3-wire SPI, see bit SPI3W in CFGA) is also possible, allowing GPIO1 to be used for other functions, for example, as a fault Output. Leave floating or connected to the PCB ground plane (preferred) if unused. 32, 33, 34, 35, 37, 39 GPO1, GPO2, GPO3, GPO4, GPO5, GPO6 IO General-Purpose Outputs (GPOs). It can be configured individually for open -drain and push-pull mode. In push-pull mode, the pin can be switched to GND or VDD. It can be used as an input when configured in open- drain mode with output disabled. Dual threshold confirms whether the pin is at high or at low level. Pins are high impedance during power down, and as default after power up/reset. GPO6 can be configured to a push -pull clock output with frequency 0.1 × OSC1. Leave the pins floating if unused. 36, 38 OCA, OCB IO Overcurrent Alert Push-Pull or Open Drain Outputs A/B with Programmable Polarity and PWM or Static Operation Mode. State of the pins can be readback (OCAP, OCBP). In push -pull the pins can switch to VREG. Leave floating if unused. 25 ISOMD I isoSPI Mode Enable Input. Serial interface mode digital input. Connecting ISOMD to logic high level (VREG) configures pins SDO, SCK/IPA, CSB/IMA, and SDI for 2 -wire isolated SPI (isoSPI) mode. Connecting ISOMD to logic low level (GND) configures the pins for 4-wire SPI mode. 21 SDO O 4-Wire SPI Serial-Data Open-Drain Output (SDO) when ISOMD is Connected Low (GND). Pull -up resistor must be connected externally (see VOL,SDO specification on SDO pin, which limits the minimum pull -up resistance). Connect to the PCB ground plane when 2-wire isolated SPI mode is configured through ISOMD connected high. 24 SDI I 4-Wire SPI Serial-Data Input (SDI) when ISOMD is Connected Low (GND). Connect to the PCB ground plane when 2 -wire isolated SPI mode is configured through ISOMD connected high. 26 SCK/IPA IO 4-Wire SPI Serial-Clock Input (SCK) or Differential Positive Input/Output Port A (IPA). The function of this pin depends on the connection of ISOMD. When ISOMD is connected low, the SCK function is active. When ISOMD is connected high, the IPA function is active. 27 CSB/IMA IO 4-Wire SPI Active Low Chip-Select input (CSB) or Differential Negative Input/Output Port A (IMA). The function of this pin depends on the connection of ISOMD. When ISOMD is connected low, the CSB function is active. When ISOMD is connected high, the IMA function is active. 22, 23 IPB, IMB IO Differential (IPB: Plus, IMB: Minus) Input/Output Pins of the Isolated 2-wire SPI Port B. When ISOMD is connected to logic low level (GND), the Port B operates in the controller mode only, and communication can only be initiated on the A -port and never on the B-port. Termination resistor must be connected externally, or the pins can be connected to the PCB ground plane if unused. 49 EPAD N/A Exposed Pad. Connect exposed pad to GND. The exposed pad is internally connected to GND. It must be connected to the PCB ground plane through several vias. For more details, see the Current Sense Layout Recommendation and Footprint Recommendation sections.

Figure 18. TMP2 Error vs. Temperature

B is not used to lower the VREG supply current consumption. Table 21. isoSPI Pulse Types and short pulses transmit data. Table 22. Port B (Controller) isoSPI Port Function Table 23. Port A (Peripheral) isoSPI Port Function Long +1 Drive CSB high None. Short +1 Set SDI = 1 Short −1 pulse if reading 0 bit. Pulse SCK Short +1 pulse if reading 1 bit. No return pulse if not in read mode. Short −1 Set SDI = 0 Short -1 pulse if reading 0 bit. Pulse SCK Short +1 pulse if reading a 1 bit. No return pulse if not in read mode.

(Port A) or isoSPI (Port A or Port B) peripheral interface. Table 24. Protocol Keys CMD0 Command Byte 0 (see Table 29). CMD1 Command Byte 1 (see Table 29). PEC0 Packet Error Code Byte 0 (see Table 30). PEC1 Packet Error Code Byte 1 (see Table 30). DPEC0 Data Packet Error Code Byte 0 (see Table 31 and Table 32). DPEC1 Data Packet Error Code Byte 1 (see Table 31 and Table 32). ... Continuation of Protocol. S<m>:B<n> Byte n send to (WRITE) or read from (READ) device m. N Total number of devices in daisy-chain. Table 25. WRITE Command. Data and DPEC Bytes are Sent from Serial Controller to Peripheral Table 26. Read Command. Data and DPEC Bytes are Sent from Serial Peripheral to Controller Table 27. Read-All Command Table 28. Poll or 4-Byte-Only Commands. The Optional Poll Data is Sent from Peripheral to Controller CMD0 CMD1 PEC0 PEC1 Optional Poll Data ... Table 29. Command Format byte for a total of 54 data bits followed by the PEC10 bits. or WR48 command type throughout this data sheet. PEC10 bits as shown in Table 27. ADBMS2950B shown in Figure 20, Figure 21, or Figure 22. indicated in Table 27 by showing S1:... bytes only. counter and PEC10 when reading data.

format for the DPEC when reading data. being accessed does not increment.

1. Initialize the Command PEC to 0b000000000010000
2. Update the 15-bit Command PEC as follows:
3. Go back to step 2 until all 16 command bits are

Table 30. Command PEC Format

1. Initialize the data PEC to 0b0000010000 (10-bit
2. Update the 10-bit data PEC as follows:
3. Go back to step 2 until all the data, including six

two polling methods can be used. stack complete the operations. data pulses are sent to the device to update the operation status. devices completed conversions. Figure 25. SDO Polling After an ADC Conversion Command (Daisy-Chain Configuration) Figure 26. SDO Polling Using PLADC Command (Daisy-Chain Configuration) Table 33 lists all available commands of the ADBMS2950B. ADBMS6830B compatible commands are listed in Table 87. Table 33. Command Codes Overview

10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Description

Rev. 0 | Page 26 of 97 Name Type BIT ADX CMD 1 0 1 0 0 1 1 0 x x x Start AUX ADC. CLRI CMD 1 1 1 0 0 0 1 0 0 0 1 Clear IxADC and VBxADC results (ADBMS6830B: CLRCELL). CLRA CMD 1 1 1 0 0 0 1 0 1 0 0 Clear IxADC and VBxADC accumulators (ADBMS6830B: CLRFC). CLRVX CMD 1 1 1 0 0 0 1 0 0 1 0 Clears all VxADC and AUX ADC results (ADBMS6830B: CLRAUX). CLRO CMD 1 1 1 0 0 0 1 0 0 1 1 Clears all OCxADC results. CLRFLAG WR48 1 1 1 0 0 0 1 0 1 1 1 Write 1 to Clear Flag Register Latches (ADBMS6830B: CLRFLAG). RDFLAG RD48 0 0 0 0 ERR 1 1 0 0 1 0 Read FLAG register (ADBMS6830B: RDSTATC). RDSTAT RD48 0 0 0 0 0 1 1 0 1 0 0 Read STAT register (ADBMS6830B: RDSTATE). RDI RD48 0 0 0 0 0 0 0 0 1 0 0 Read I1ADC and I2ADC results (ADBMS6830B: RDCVA). 0 0 0 0 0 0 1 0 0 1 0 ADBMS6830B compatible code RDFCA. RDVB RD48 0 0 0 0 0 0 0 0 1 1 0 Read VB1ADC and VB2ADC results (ADBMS6830B: RDCVB). 0 0 0 0 0 0 1 0 0 1 1 ADBMS6830B compatible code RDFCB. RDIACC RD48 0 0 0 0 1 0 0 0 1 0 0 Read I1ADC and I2ADC accumulators (ADBMS6830B: RDACA). RDVBACC RD48 0 0 0 0 1 0 0 0 1 1 0 Read VB1ADC and VB2ADC accumulators (ADBMS6830B: RDACB). RDIVB1 RD48 0 0 0 0 0 0 0 1 0 0 0 Read I1ADC and VB1ADC results (ADBMS6830B: RDCVC). 0 0 0 0 0 0 1 0 1 0 0 ADBMS6830B compatible code RDFCC. RDIVB1ACC RD48 0 0 0 0 1 0 0 1 0 0 0 Read I1ADC and VB1ADC accumulators (ADBMS6830B: RDACC). RDV1A RD48 0 0 0 0 0 0 0 1 0 1 0 Reads V1ADC results (ADBMS6830B: RDCVD). 0 0 0 0 0 0 1 0 1 0 1 ADBMS6830B compatible code RDFCD. 0 0 0 0 1 0 0 1 0 1 0 ADBMS6830B compatible code RDACD. 0 0 0 0 0 0 1 1 0 0 1 ADBMS6830B compatible code RDAUXA. RDV1B RD48 0 0 0 0 0 0 0 1 0 0 1 Reads V1ADC results (ADBMS6830B: RDCVE). 0 0 0 0 0 0 1 0 1 1 0 ADBMS6830B compatible code RDFCE. 0 0 0 0 1 0 0 1 0 0 1 ADBMS6830B compatible code RDACE. 0 0 0 0 0 0 1 1 0 1 0 ADBMS6830B compatible code RDAUXB. RDV1C RD48 0 0 0 0 0 0 0 0 0 1 1 Reads V1ADC results (ADBMS6830B: RDSVA). RDV1D RD48 0 0 0 0 0 0 1 1 0 1 1 Reads V1ADC/V2ADC results (ADBMS6830B: RDAUXC). RDV2A RD48 0 0 0 0 0 0 0 0 1 1 1 Reads V2ADC results (ADBMS6830B: RDSVC). 0 0 0 0 0 0 1 1 1 0 0 ADBMS6830B compatible code RDRAXA. RDV2B RD48 0 0 0 0 0 0 0 1 1 0 1 Reads V2ADC results (ADBMS6830B: RDSVD). 0 0 0 0 0 0 1 1 1 0 1 ADBMS6830B compatible code RDRAXB. RDV2C RD48 0 0 0 0 0 0 0 0 1 0 1 Reads V2ADC results (ADBMS6830B: RDSVB).

Rev. 0 | Page 27 of 97 Name Type BIT RDV2D RD48 0 0 0 0 0 0 1 1 1 1 1 Reads V1ADC/V2ADC results (ADBMS6830B: RDAUXD). RDV2E RD48 0 0 0 0 0 1 0 0 1 0 1 Reads V2ADC results (ADBMS6830B: RDRAXD). RDXA RD48 0 0 0 0 0 1 1 0 0 0 0 Reads AUX ADC results (ADBMS6830B: RDSTATA). RDXB RD48 0 0 0 0 0 1 1 0 0 0 1 Reads AUX ADC results (ADBMS6830B: RDSTATB). RDXC RD48 0 0 0 0 0 1 1 0 0 1 1 Reads AUX ADC results (ADBMS6830B: RDSTATD). RDOC RD48 0 0 0 0 0 0 0 1 0 1 1 Read OCxADC results (ADBMS6830B: RDCVF). 0 0 0 0 0 0 1 0 1 1 1 ADBMS6830B compatible code RDFCF. RDSID RD48 0 0 0 0 0 1 0 1 1 0 0 Read SID register (ADBMS6830B: RDSID). RDCFGA RD48 0 0 0 0 0 0 0 0 0 1 0 Read CFGA register (ADBMS6830B: RDCFGA). RDCFGB RD48 0 0 0 0 0 1 0 0 1 1 0 Read CFGB register (ADBMS6830B: RDCFGB). RDCOMM RD48 1 1 1 0 0 1 0 0 0 1 0 Read COMM register (ADBMS6830B: RDCOMM). WRCFGA WR48 0 0 0 0 0 0 0 0 0 0 1 Write CFGA register (ADBMS6830B: WRCFGA). WRCFGB WR48 0 0 0 0 0 1 0 0 1 0 0 Write CFGB register (ADBMS6830B: WRCFGB). WRCOMM WR48 1 1 1 0 0 1 0 0 0 0 1 Write COMM register (ADBMS6830B: WRCOMM). STCOMM CMD 1 1 1 0 0 1 0 0 0 1 1 Send COMM register (ADBMS6830B: STCOMM). PLADC CMD 1 1 1 0 0 0 1 1 0 0 0 Poll IxADC, VBxADC, VxADC, and AUX ADC conversion completion (ADBMS6830B: PLADC). PLI1 CMD 1 1 1 0 0 0 1 1 1 0 0 Poll I1ADC and VB1ADC conversion completion (ADBMS6830B: PLCADC). PLI2 CMD 1 1 1 0 0 0 1 1 1 0 1 Poll I2ADC and VB2ADC conversion completion (ADBMS6830B: PLSADC). PLV CMD 1 1 1 0 0 0 1 1 1 1 0 Poll V1ADC and V2ADC conversion completion (ADBMS6830B: PLAUX1). PLX CMD 1 1 1 0 0 0 1 1 1 1 1 Poll AUX ADC conversion completion (ADBMS6830B: PLAUX2). RDALLI RD160 0 0 0 0 0 0 0 1 1 0 0 Read IxADC and VBxADC results. RDALLA RD160 0 0 0 0 1 0 0 1 1 0 0 Read IxADC and VBxADC accumulators. RDALLV RD160 0 0 0 0 0 1 1 0 1 0 1 Reads all external input V1ADC results and V9, V10 results measured by V2ADC only. RDALLR RD160 0 0 0 0 0 0 1 0 0 0 1 Reads all external input V2ADC results and V7, V8 results measured by V1ADC only. RDALLX RD160 0 0 0 0 1 0 1 0 0 0 1 Reads all AUX ADC results. RDALLC RD160 0 0 0 0 0 0 1 0 0 0 0 Read All configuration, flag and status registers. Timing Considerations This section shows how to calculate the length of SPI transactions when operating with a single device (Figure 19 or any of the subsequent figures with one device only) or when operating in a daisy-chain of pack and link monitor devices ADBMS2950B and optional cell monitor devices ADBMS6830B (see Figure 20, Figure 21, and Figure 22). Table 34 describes the parameters used for the calculation and the resulting timings. For the single device scenario NP = 1, NQ = 0 resulting in N = 1 is assumed.

with NP = 2, NQ = 5 is assumed. required for the pack monitors. depends on the SPI controller driver and OS. Table 34. SPI Sequence Timing Parameters t Absolute SPI transaction time stamp. Bc Number of command (and PEC) bytes is always 4. Bd Number of bytes depends on command type. B Number of command bytes plus data bytes. T Serial transaction time equals B × Tb + Ts. NP 2 Number of pack monitors within daisy-chain. NQ 5 Number of cell monitors within daisy-chain. N 7 Total number of devices in daisy-chain. Fspi 2 MHz SPI frequency, ADBMS devices support up to 2 MHz. Tb 4 μs Transaction time per byte is equal to 8 ÷ Fspi + Tdb. propagation delays specified as tDSY(D) in Table 17. the transaction at a device boundary. conversions (for example, ADV). Table 35. Single Device Command Types A 4 0 4 Action command, no data bytes. all conversions to be completed before reading the results. Table 36. Single Device Vx and Diagnostic Measure Sequence

1 WRCFGA W 12 50

2 ADV A 4 18

3 ADX A 4 18

4 RDALLV RALL 24 98

5 RDALLR RALL 24 98

6 RDALLX RALL 24 98

commands allow to read from the first device in the chain only. making a total of seven devices in the daisy-chain. Table 37. Daisy Chain Command Types A 4 0 4 Action command, no data bytes. R1 4 8 12 Read from 1st device in daisy-chain (Bd = 8). W1 4 8 12 Write to 1st device in daisy-chain (Bd = 8). RALL 4 20 24 Read All from 1st device in daisy-chain (Bd = 20). R 4 56 60 Read from all devices in daisy-chain (Bd = N × 8). W 4 56 60 Write to all devices in daisy-chain (Bd = N × 8). currents from all pack monitors. Note that the ADI1 and ADCV are compatible commands. periodically and can be read by the host controller any time. Table 38. Daisy-Chain Pack and Cell Monitor Sequence

1 ADCV,

2 ADV A 4 18 μs Trigger VxADCs.

3 RDACA R 60 242

4 RDACB R 60 242

5 RDACC R 60 242

6 RDACD R 60 242

7 RDACE R 60 242

8 RDACF R 60 242

9 RDV1A RP 20 82 μs Read V1ADC results V1A to

10 RDV1B RP 20 82 μs Read V1ADC results V4A to

11 RDV1C RP 20 82 μs Read V1ADC results V7A, V8A,

12 RDIACC RP 20 82 μs Read battery pack current. 13 RDVBACC RP 20 82 μs Read battery pack voltage. Figure 27. Core State Diagram VREG can charge VDD through another internal protection diode. externally more than 0.3V below VREG (see Table 18). the bit REFUP in CFGA register (see Table 69) can be read. maximum tREFUP or for the REFUP bit set to 1.

details, see the Overcurrent Configuration Update section. initialization procedure (see Initialization Cycle section). removed or the SRST command is sent. of STAT register (see Table 75) being set to 1. communication: Port A and Port B. receiving data, the isoSPI interface moves to the ACTIVE state. that are not generated for write commands. Figure 28. isoSPI Interface State Diagram IREG(VREF1P25) is the VREF1P25 pin sourcing current. IREG(OCx) is the sum of the OCA and OCB pin sourcing currents. DisoSPI is the isoSPI communication duty cycle. of read commands is (1 − RWR). IREG(isoSPI,RDY) is the isoSPI ready current.

before reading the result registers. commands, as indicated in the Continuous column of Table 39. triggered on demand through ADV or ADX. Table 39. Overview of ADCs and Related Trigger Commands OCxADC I1A, I1B, I2A, I2B, I3A, I3B, VREF1-VREF2 WRCFGA (OCEN = 1) Yes Overcurrent ADCs. I1ADC, VB1ADC I1A, I1B, VBATx, SGND ADI1 Yes (OPT) Battery current and voltage ADCs channel 1. I2ADC, VB2ADC I2A, I2B, VBATx, SGND ADI2 Yes (OPT) Battery current and voltage ADCs channel 2. V1ADC, V2ADC V1 to V10, VREF2, VREF1P25, SGND ADV No Voltage ADCs. AUX ADC See Table 48 ADX No Auxiliary ADC. to redundantly measure the voltage drop across a shunt resistor. after 1 ms or ACCN times 1 ms) has elapsed. every I1ADC/VB1ADC conversion.

Rev. 0 | Page 32 of 97 The IxCAL bits are low until the initialization process has completed, after 136 conversions. The total time required for initialization = tIxADC_STARTUP + tIxADC_INIT. When initialization is started by an ADV or ADX command, no IxADC results are available, and IxCNT remains zero. For this reason, it is recommended to start the initialization through a continuous ADIx command and wait for 136 conversion cycles (when IxCNT reports 136 the first time) before reading the IxADC results for the first time. From power-up or SRST, it takes t WA K E + tREFUP + tIxADC_STARTUP + tIxADC_INIT for the IxADCs to meet the accuracy specification. The VBxADC results are available during the initialization process. All other ADCs are unaffected by the initialization process. IxADC Open-Wire Current Sources As shown in Figure 1, the ADBMS2950B features current sources at the inputs of both current measurement channels. Activating these current sources allows the detection of a broken connection to a shunt resistor. The Open-wire current sources are configured by the DIAGSEL configuration register and activated by issuing a diagnostic ADI1 or ADI2 measurement through the OPT command bits. The current sources have a value of about 0.5 μA. As the open-wire current sources are connected after a 3.8 kΩ ESD protection resistor, activating them changes the reading of the corresponding IxADC by about 1.9 mV , while it does not affect the reading of the other IxADC. It also does not affect any of the OCxADC readings. Redundant I2ADC and VB2ADC diagnostic measurements (synchronous to I1ADC and VB1ADC for redundancy) must be terminated through one of the two ADI2 single-shot measurement (non-diagnostic) or any other ADI2 single-shot diagnostic (DIAGSEL) measurement command after DIAGSEL has been set to 0b000. Battery Voltage Measurements The ADBMS2950B features two dedicated battery-stack voltage measurement paths that connect to one or two external resistor- dividers through the VBAT1 and VBAT2 pins. The voltage at these pins is first buffered to provide a high input resistance and then applied to two 16-bit ADCs. VB1ADC operates simultaneously and synchronously to I1ADC whenever an ADI1 command is issued. Diagnostic measurements selected through DIAGSEL and activated through OPT command bits are also performed on both ADCs simultaneously. The same is valid for VB2ADC, which operates simultaneously and synchronously to I2ADC. If ADI1 is issued with the RD command bit set, all four ADCs operate synchronously, irrespective of whether the OPT bits are set to single-shot or continuous mode. Redundant I2ADC and VB2ADC diagnostic measurements (synchronous to I1ADC and VB1ADC for redundancy) must be terminated through one of the two ADI2 single-shot measurement (non-diagnostic) or any other ADI2 single-shot diagnostic (DIAGSEL) measurement command after DIAGSEL has been set to 0b000. VBxADC Open-Wire Current Sources Similar to the IxADCs, the VBxADCs feature current sources connected to their inputs. The open-wire current source has a value of 10 μA and is preceded by a 2.3 kΩ ESD protection resistor, leading to a typical change in ADC output of about 23 m V. Continuous or Single-Shot Measurements The IxADC and VBxADC can be configured to perform a single measurement or continuous measurements, which are controlled by the OPT command bits. In continuous mode, the result registers of the corresponding ADCs are updated at their conversion rate (nominally 1 ms for the Ix, VBx registers, and 1 ms times ACCN for the accumulated result registers IxACC, VBxACC) for non-diagnostic measurements. For diagnostic measurements, the content of the accumulated IxADC result registers is not valid and must be ignored and only the 1 ms conversion results must be used. The accumulated VBxADC result registers can be used for diagnostic and non-diagnostic measurements. To end the continuous measurement mode of the respective ADCs, a single-shot ADI1 or ADI2 command must be sent. The addressed ADCs then perform the last single-shot measurement and stop. Conversion Results Accumulation In the continuous diagnostic measurement mode, the VBxADC conversions are summed up to the accumulation results VBxACC. The current measurement accumulation results IxACC are not valid during diagnostic operation. In continuous non-diagnostic measurement mode, the IxADC and VBxADC results are summed up to the accumulation results IxACC and VBxACC. The ACCI (and the resulting ACCN) register configures the number of IxADC and VBxADC conversions (ACCN) that are accumulated internally before being stored to the IxACC and VBxACC registers. The ACCI configuration becomes active only with the next ADI1 or ADI2 command. The internal accumulators are cleared to start a new cycle after the accumulation result registers have been updated. The update rate of those registers thus depends on ACCN, which can be set to be slower than the host controller update rate, allowing to read back-to-back conversion results. The conversion counters I1CNT and I2CNT allow to identify new conversions and discard those that are already read.

any time to get fast measurement snapshots if required. see the Continuous Sampling and Coulomb Counting section. Figure 29. Relation of I1CNT, I2PHA, Ix, VBx, and Accumulated Result Registers IxACC, VBxACC Update for Two Settings of ACCN 4 and 8 (ACCI 0 and 1) triggered to provide redundant, synchronous measurements. conversion immediately and then stop. and the I1PHA value is zero. Table 40. I1ADC, VB1ADC, I2ADC, VB2ADC Command Codes

8 BIT 7

5 BIT 4

2 BIT 1 BIT 0 Description

ADI1 CMD 0 1 RD OPT[3] 1 1 OPT[2] 0 x OPT[1] OPT[0] Start I1ADC and VB1ADC (ADBMS6830B: ADCV). ADI2 CMD 0 0 1 OPT[3] 1 1 OPT[2] 1 0 OPT[1] OPT[0] Start I2ADC and VB2ADC (ADBMS6830B: ADSV). 0 0 0 0 0 0 1 0 0 1 0 ADBMS6830B compatible code RDFCA. 0 0 0 0 0 0 1 0 0 1 1 ADBMS6830B compatible code RDFCB. 0 0 0 0 0 0 1 0 1 0 0 ADBMS6830B compatible code RDFCC. RDALLI RD160 0 0 0 0 0 0 0 1 1 0 0 Read IxADC and VBxADC results. RDALLA RD160 0 0 0 0 1 0 0 1 1 0 0 Read IxADC and VBxADC accumulators.

way if the command PEC matches the command bytes. see the Communication Protocol section. the CFGB configuration register (see Table 72). Table 41. ADI1 and ADI2 Parameter Bits 0 Start I1ADC/VB1ADC only. Start CADC only. 1 Start I1ADC/VB1ADC and I2ADC/VB2ADC synchronously. Start CADC and SADC synchronously. 1010 Continuous diagnostic (DIAGSEL) measurement. Continuous odd channel OWD, no PWM discharge. 1001 Continuous diagnostic (DIAGSEL) measurement. Continuous even channel OWD, no PWM discharge. 1011 Continuous diagnostic (DIAGSEL) measurement. Continuous all channel OWD, no PWM discharge. 1100 Continuous measurement. Invalid command (CONT = DCP = 1). 1000 Continuous measurement. Continuous measurement, no PWM discharge. 0010 Invalid command. Single-shot odd channel OWD, no PWM discharge. 0001 Invalid command. Single-shot even channel OWD, no PWM discharge. 0011 Invalid command. Single-shot all channel OWD, no PWM discharge. 1110 Single-shot diagnostic (DIAGSEL) measurement. Invalid command (CONT = DCP = 1). 1101 Single-shot diagnostic (DIAGSEL) measurement. Invalid command (CONT = DCP = 1). 1111 Single-shot diagnostic (DIAGSEL) measurement. Invalid command (CONT = DCP = 1). 0110 Single-shot diagnostic (DIAGSEL) measurement. Single-shot odd channel OWD, PWM discharge permitted. 0101 Single-shot diagnostic (DIAGSEL) measurement. Single-shot even channel OWD, PWM discharge permitted. 0111 Single-shot diagnostic (DIAGSEL) measurement. Single-shot all channel OWD, PWM discharge permitted. 0000 Single-shot measurement. Single-shot measurement, no PWM discharge. 0100 Single-shot measurement. Single-shot measurement, PWM discharge permitted. additional commands with OPT = 0b1100.

Table 42. ADI2 Command Result while I1ADC in Continuous Operation 0b000 No No No Non-diagnostic, Immediate single shot, Asynchronous to I1ADC, VB1ADC. Yes No No Diagnostic, Immediate single shot, Asynchronous to I1ADC, VB1ADC. Single Shot 0bxxx No No No Non-diagnostic, Immediate single shot, Asynchronous to I1ADC, VB1ADC. Table 43. I1ADC, VB1ADC, I2ADC, VB2ADC Result Registers I1 RO, FRZ 0x03FFFF 0xFC0000 Signed 24-bit I1ADC result register, VSHUNT = I1 × 1 µV = I1A − I1B. I2 RO, FRZ 0x03FFFF 0xFC0000 Signed 24-bit I2ADC result register, VSHUNT = −(I2 × 1 µV) = I2B − I2A; inverted gain compared to I1. VB1 RO, FRZ 0x7FFF 0x8000 Signed 16-bit VB1ADC result register, VBAT = VB1 × 100 µV. VB2 RO, FRZ 0x7FFF 0x8000 Signed 16-bit VB2ADC result register, VBAT = −(VB2 × 85 µV); inverted gain compared to VB1. Table 44 lists the accumulated measurement result registers. up to the accumulation results IxACC. Table 44. I1ADC, VB1ADC, I2ADC, VB2ADC Accumulation Registers VB1ACC RO, FRZ 0x7FFFFF 0x800000 Signed 24-bit VB1ADC accumulation register, VBAT_AVERAGED = VB1ACC × 100 µV ÷ ACCN. VB2ACC RO, FRZ 0x7FFFFF 0x800000 Signed 24-bit VB2ADC accumulation register, VBAT_AVERAGED = VB2ACC × (−85 µV) ÷ ACCN. I1ACC RO, FRZ 0x7FFFFF 0x800000 Signed 24-bit I1ADC accumulation register, VSHUNT_AVERAGED = I1ACC × 1 µV ÷ ACCN. I2ACC RO, FRZ 0x7FFFFF 0x800000 Signed 24-bit I2ADC accumulation register, VSHUNT_AVERAGED = I2ACC × (−1 µV) ÷ ACCN. on operation of the SNAP , UNSNAP commands. Table 45. I1ADC, VB1ADC, I2ADC, VB2ADC Return Values Table 46. RDALLI Return Values

0 I1[7:0]

1 I1[15:8]

2 I1[23:16]

3 I2[7:0]

4 I2[15:8]

5 I2[23:16]

6 VB1[7:0]

7 VB1[15:8]

8 VB2[7:0]

9 VB2[15:8]

10 OC1R

11 OC2R

12 OC3R

13 GPO6H GPO5H GPO4H GPO3H GPO2H GPO1H GPO6L GPO5L

14 RESERVED VDRUV OCMM OC3L OCAGD OCAL OC1L

15 RESERVED VDDUV NOCLK REFFLT OCBGD OCBL OC2L

16 I2CNT[2:0] I1CNT[10:6]

17 I1CNT[5:0] I1PHA[1:0]

18 VREGOV VREGUV VDIGOV VDIGUV SED1 MED1 SED2 MED2

19 VDEL VDE 0 SPIFLT RESET THSD1 TMODE OSCFLT

1 The thermal shutdown indicator bit THSD is not cleared by

Table 47. RDALLA Return Values

0 I1ACC[7:0]

1 I1ACC[15:8]

2 I1ACC[23:16]

3 I2ACC[7:0]

4 I2ACC[15:8]

5 I2ACC[23:16]

6 VB1ACC[7:0]

7 VB1ACC[15:8]

8 VB1ACC[23:16]

9 VB2ACC[7:0]

10 VB2ACC[15:8]

11 VB2ACC[23:16]

12 GPO6H GPO5H GPO4H GPO3H GPO2H GPO1H GPO6L GPO5L

13 GPO4L GPO3L GPO2L GPO1L GPIO4L GPIO3L GPIO2L GPIO1L

chassis-ground isolation resistance measurement. an ongoing conversion, the V ADCs are stopped and restarted. the order of the channels in the table given above.

1.25V yields a −0.75V differential ADC measurement. VBxADC and VxADC Transfer Function section). VREF1P25, and the internal temperature sensors. 2.1 ms to measure all the eight channels. Table 48. AUX ADC Measurement Sequence 1 VDIV GND 0.27 ms Divided VREF1 reference voltage. 2 EPAD GND 0.53 ms Exposed pad. 3 VREF1P25 RGND 0.80 ms VREF1P25 reference pin voltage. 4 VDIG GND 1.06 ms Internal digital 3V supply. 5 VDD GND 1.33 ms VDD power supply pin. 7 VREG GND 1.86 ms VREG power supply pin. Table 49. V1ADC, V2ADC, AUX ADC Command Codes ADV CMD 1 0 0 OW[1:0] 1 1 VCH[3:0] Start V1ADC and V2ADC. ADX CMD 1 0 1 0 0 1 1 0 x x x Start AUX ADC. RDV1A RD48 0 0 0 0 0 0 0 1 0 1 0 Reads V1ADC results (ADBMS6830B: RDCVD). 0 0 0 0 0 0 1 0 1 0 1 ADBMS6830B compatible code RDFCD. 0 0 0 0 1 0 0 1 0 1 0 ADBMS6830B compatible code RDACD. 0 0 0 0 0 0 1 1 0 0 1 ADBMS6830B compatible code RDAUXA. RDV1B RD48 0 0 0 0 0 0 0 1 0 0 1 Reads V1ADC results (ADBMS6830B: RDCVE). 0 0 0 0 0 0 1 0 1 1 0 ADBMS6830B compatible code RDFCE. 0 0 0 0 1 0 0 1 0 0 1 ADBMS6830B compatible code RDACE. 0 0 0 0 0 0 1 1 0 1 0 ADBMS6830B compatible code RDAUXB. RDV1C RD48 0 0 0 0 0 0 0 0 0 1 1 Reads V1ADC results (ADBMS6830B: RDSVA). RDV2A RD48 0 0 0 0 0 0 0 0 1 1 1 Reads V2ADC results (ADBMS6830B: RDSVC). 0 0 0 0 0 0 1 1 1 0 0 ADBMS6830B compatible code RDRAXA. RDV2B RD48 0 0 0 0 0 0 0 1 1 0 1 Reads V2ADC results (ADBMS6830B: RDSVD). 0 0 0 0 0 0 1 1 1 0 1 ADBMS6830B compatible code RDRAXB. RDV2C RD48 0 0 0 0 0 0 0 0 1 0 1 Reads V2ADC results (ADBMS6830B: RDSVB). RDV2E RD48 0 0 0 0 0 1 0 0 1 0 1 Reads V2ADC results (ADBMS6830B: RDRAXD). V10 results measured by V2ADC only. V8 results measured by V1ADC only. RDALLX RD160 0 0 0 0 1 0 1 0 0 0 1 Reads all AUX ADC results.

way if the command PEC matches the command bytes. RDALL commands are not available on the isoSPI daisy-chains. For more details, see the Communication Protocol section. Table 50. ADV Parameter Bits OW PAR V1ADC and V2ADC open-wire test current injection enable. 00 V1ADC and V2ADC open-wire source off. 01 Current injected into V1ADC MUXP for measurements V1 to V8. Current injected into V2ADC MUXP for measurements V9 to V10. Do not use OW=0b01 in combination with VCH=9, see note below. 10 Current injected into V1ADC MUXN (Pins selected by VS1 to VS8 configuration) for measurements V1 to V8. Current injected into V2ADC MUXN (Pins selected by VS9 to VS10 configuration) for measurements V9 to V10. VCH PAR V1ADC and V2ADC channel select. ≤8 Single Measurement, see Table 57. ≥9 Multi Measurement, see Table 58. false trigger of the VDDUV flag. (OW=0b01) with VCH=10 to VCH=15. issued with any OW and VCH setting. Table 51. V1ADC, V2ADC, AUX ADC Result Registers V1A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V1 result register, voltage = V1A × 100 µV. V1B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V1 result register, voltage = V1B × −85 µV. V2A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V2 result register, voltage = V2A × 100 µV. V2B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V2 result register, voltage = V2B × −85 µV. V3A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V3 result register, voltage = V3A × 100 µV. V3B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V3 result register, voltage = V3B × −85 µV. V4A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V4 result register, voltage = V4A × 100 µV. V4B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V4 result register, voltage = V4B × −85 µV. V5A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V5 result register, voltage = V5A × 100 µV. V5B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V5 result register, voltage = V5B × −85 µV. V6A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V6 result register, voltage = V6A × 100 µV. V6B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V6 result register, voltage = V6B × −85 µV. V7A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V7 result register, voltage = V7A × 100 µV. V8A RO 0x7FFF 0x8000 Signed 16-bit V1ADC V8 result register, voltage = V8A × 100 µV. V9B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V9 result register, voltage = V9B × −85 µV. V10B RO 0x7FFF 0x8000 Signed 16-bit V2ADC V10 result register, voltage = V10B × −85 µV. VREF2A RO 0x7FFF 0x8000 Signed 16-bit V1ADC VREF2 result register, voltage = VREF2A × (100 µV × 3 ÷ 1.25) = VREF2A × 240 µV. VREF2B RO 0x7FFF 0x8000 Signed 16-bit V2ADC VREF2 result register, voltage = VREF2B × (−85 µV × 3 ÷ 1.25) = VREF2B × −204 µV. VREF1P25 RO 0x7FFF 0x8000 Signed 16-bit AUX ADC VREF1P25 result register, voltage = VREF1P25 × 100 µV. VDIV RO 0x7FFF 0x8000 Signed 16-bit AUX ADC VDIV result register, voltage = VDIV × 100 µV. VREG RO 0x7FFF 0x8000 Signed 16-bit AUX ADC VREG result register, voltage = VREG × 240 µV. VDD RO 0x7FFF 0x8000 Signed 16-bit AUX ADC VDD result register, voltage = VDD × 1 mV. VDIG RO 0x7FFF 0x8000 Signed 16-bit AUX ADC VDIG result register, voltage = VDIG × 240 µV. EPAD RO 0x7FFF 0x8000 Signed 16-bit AUX ADC EPAD result register, voltage = EPAD × 100 µV. TMP1 RO 0x7FFF 0x8000 Signed 16-bit AUX ADC temperature 1 result register, temperature in °C = (TMP1 ÷ 61.8) − 250°C. TMP2 RO 0x7FFF 0x8000 Signed 16-bit AUX ADC temperature 2 result register, temperature in °C = (TMP2 ÷ 20.5) − 267°C. Table 52. V1ADC, V2ADC, AUX ADC Return Values

Table 53. Clock Frequency Monitor Result Description latched until OSCFLT gets cleared. Expected valid range, no fault. Others First latched counter value in the invalid range leading to OSCFLT flag assertion. Table 54. RDALLV Return Values

0 V1A[7:0]

1 V1A[15:8]

2 V2A[7:0]

3 V2A[15:8]

4 V3A[7:0]

5 V3A[15:8]

6 V4A[7:0]

7 V4A[15:8]

8 V5A[7:0]

9 V5A[15:8]

10 V6A[7:0]

11 V6A[15:8]

12 V7A[7:0]

13 V7A[15:8]

14 V8A[7:0]

15 V8A[15:8]

16 V9B[7:0]

17 V9B[15:8]

18 V10B[7:0]

19 V10B[15:8]

Table 55. RDALLR Return Values

0 V1B[7:0]

1 V1B[15:8]

2 V2B[7:0]

3 V2B[15:8]

4 V3B[7:0]

5 V3B[15:8]

6 V4B[7:0]

7 V4B[15:8]

8 V5B[7:0]

9 V5B[15:8]

10 V6B[7:0]

11 V6B[15:8]

Table 56. RDALLX Return Values

0 VREF2A[7:0]

1 VREF2A[15:8]

2 VREF2B[7:0]

3 VREF2B[15:8]

4 VREF1P25[7:0]

5 VREF1P25[15:8]

6 TMP1[7:0]

7 TMP1[15:8]

8 VREG[7:0]

9 VREG[15:8]

10 VDD[7:0]

11 VDD[15:8]

12 VDIG[7:0]

13 VDIG[15:8]

14 EPAD[7:0]

15 EPAD[15:8]

16 VDIV[7:0]

17 VDIV[15:8]

18 TMP2[7:0]

19 TMP2[15:8]

input and MUXN indicates the negative multiplexer input. the comparison can be done in the host controller. each to be measured against either SGND or VREF1P25. VS10) in the CFGA Configuration Register (see Table 70). Table 57. V1ADC and V2ADC Single-Channel Options multiplexer setting and a conversion time which is 0.265 ms.

multiple channels, one after the other. Table 58. V1ADC and V2ADC Multichannel Options The SOAK time is applied to every individual measurement. single conversions, where n is the number of specified channels. measurement time is 9 × (0.265 ms + 150 ms) = 1.35 seconds. or negative (OW = 10) direction. active when measuring VREF2. impact on the digital output codes that can be reached. is lower than the guaranteed minimum value of VREF1. Therefore, these ADCs do not have any unreachable codes. V2ADC is equivalent to VB2ADC.

Figure 30. VxADC and VBxADC Transfer Function Figure 31. VxADC and VBxADC Transfer Function Detail completion of ADCs triggered for single-shot measurements.

• PLI1 for I1ADC/VB1ADC
• PLI2 for I2ADC/VB2ADC
• PLV for V1ADC/V2ADC
• PLX for AUX ADC Additionally, the global Poll command PLADC allows to poll for completion of all ADCs in case none of them operate in continuous mode.

Table 59. PLI1, PLI2, PLV, PLX Command Codes

0 Description

PLX CMD 1 1 1 0 0 0 1 1 1 1 1 Poll AUX ADC conversion completion (ADBMS6830B: PLAUX2). the precision improves by a factor √2. error, and nonlinearity. At zero-input, only the offset is relevant.

function of the input signal. Figure 36. VBxADC TME vs. Input Voltage common deglitch filter setting (OCDGT) are programmable. per overcurrent channel (OC1GC to OC3GC). conversion rate of 16 kHz through registers OC1R to OC3R. such a power rail to the VREG rail must be placed. OCEN = 0, regardless of the OCMODE or OCOD settings. impedance. In both the cases, the deglitchers reset as well.

headroom for such variations. Figure 37. PWM1 and PWM2 Coding neither a fault nor a diagnostic cycle is pending in the device. can trigger an external timeout detector. 25% and 0% is changed to 100%. from the no-clock detection. Table 60. PWM1 Overcurrent Output Mode Duty-Cycle Coding for OCAX = 0, OCBX = 0 0% - High-Z OCx pins in high impedance state after reset and whenever OCEN = 0. 0% - Active-low OCx pins actively driven low. Detection of any SPF which is a DFI for OC1 -2-3 or when executing diagnostic for OC. 25% OC threshold is not violated by more than one OCxADC (no overcurrent). 75% OC threshold is violated by more than one OCxADC.

Rev. 0 | Page 47 of 97 overcurrent detection is activated and changes to the respective bit fields in the CFGB register do not affect the overcurrent engine. New configurations in CFGB are activated only with the next 0-to-1 transition on the OCEN bit. When deactivating the overcurrent functionality through changing OCEN from 1 to 0, the overcurrent engine does not disable immediately. Instead, the deactivation only takes effect once the ongoing OCxADC conversions finish and the dependent registers (OCxR) and flags (OC1 to OC3L, OCAL, and OCBL) are updated. This leads to a minimum wait time requirement between the WRCFGA clearing the OCEN and any subsequent command that reads (RDFLAG), freezes (SNAP) or clears (CLRFLAG) the overcurrent alert flags or reactivates the overcurrent engine (WRCFGA with OCEN = 1). The required wait time between WRCFGA with OCEN = 0 and WRCFGA with OCEN = 1 or CLRFLAG can be expressed as follows: t OCEN,DLY1 > max(tOCxADC) − t5 − (32 + N × 64) × tCLK Where max(tOCxADC) is the maximum OCxADC conversion time, t5 is the minimum CS idle time, N is the number of devices written in the daisy-chain, and tCLK is the clock period of the (iso)SPI interface. If positive, the host must wait this time. If negative, no wait time is required as the length of the second WRCFGA or the CLRFLAG command ensures already a minimum time after OCEN clears. The required wait time between WRCFGA with OCEN = 0 and RDFLAG or SNAP can be expressed as follows: t OCEN,DLY2 > max(tOCxADC) − t5 − 16 × tCLK The wait time tOCEN,DLY2 is easily respected by proper command sequencing that avoids RDFLAG or SNAP directly after the WRCFGA. The wait time tOCEN,DLY1 is typically required in the sequences for the Overcurrent Configuration Update and the Crash Signal Management. Overcurrent Configuration Update The overcurrent detection is activated while the OCEN bit is set. To dynamically update the configuration from this state, at least three write commands are required: 1. Send WRCFGB command with new configuration. 2. Send WRCFGA command with OCEN = 0. 3. Wait for t OCEN,DLY1 (no wait if tOCEN,DLY1 ≤ 0). 4. Send WRCFGA command with OCEN = 1. Note:

• While it is recommended to minimize the time in which the overcurrent detection is inactive, the OCEN must be disabled for at least one OCxADC conversion time (t OCxADC), which is ensured by the wait time tOCEN,DLY1.
• It is recommended to set the bit OCDP in step 1 for the reduced interval of 3 OCxADC conversion cycles during which the OCx pins have high impedance.
• The deglitchers are reset at step 4. In case an overcurrent condition is present already before the reconfiguration but not yet long enough to ignite the pyrofuse, this leads to an increased latency equal to one deglitching time window. The successful update of the new settings can be verified by issuing a RDFLAG command after the three-write-sequence, validate the command counter (CC) incremented by 3. Crash Signal Management In case of a vehicle crash, it is typically required to do an emergency disconnect of the HV battery from the vehicle's HV network through firing the pyrofuse(s). The BMS controller can command the ADBMS2950B devices to activate the OCA and OCB outputs by setting the thresholds of all three overcurrent ADCs to zero, or by inverting the OCA and OCB outputs through OCAX, OCBX, and setting the thresholds of all three overcurrent ADCs to the maximum. The deglitch setting OCDGT must be set to the minimum value and the OCDP must be activated for minimum latency (reduced interval) between the rising edge of OCEN and the assertion of the OCA, OCB output pins. As described in the section Overcurrent Configuration Update, three write commands are required to trigger the ignition from the overcurrent function active state (OCEN = 1): 1. Send WRCFGB command to modify the OCxTH, OCAX, OCBX, OCDGT, and OCDP bits as required. 2. Send WRCFGA command to clear OCEN bit. This disables the overcurrent function and OCA, OCB pin output drivers shortly. 3. Wait for t OCEN,DLY1 (no wait if tOCEN,DLY1 ≤ 0). 4. Send WRCFGA command to set the OCEN bit again. When the ADSBM2950 derivative is configured in isoSPI mode and the isoSPI is implemented in a redundant ring topology, the device responds to commands irrespective of whether they are received through isoSPI Port A or Port B. This allows the BMS controller to send the above sequence redundantly to Port A and Port B, thereby reducing he potential risk of command loss. Successful OCx assertion can be confirmed through reading back the OCAL and OCBL latch bits. Most applications can also measure the voltage at the pyrofuse output directly to verify the successful ignition. Note that whenever OCEN is cleared, the OCx pins have a high impedance state, which allows the pin state to be defined through external pull-up or pull-down resistors. Figure 40 shows the expected timing of the OCx assertion for the PWM1 mode with OCAX = 0, OCBX = 0, COD = 0, OCDGT = 0, OCDP = 1.

unsnap commands, see the Snapshot Commands section. commands are listed in Table 66. cleared (0) do not affect the related flags. Table 66. Configuration and Status Command Codes WRCFGA WR48 0 0 0 0 0 0 0 0 0 0 1 Write CFGA register (ADBMS6830B: WRCFGA). RDCFGA RD48 0 0 0 0 0 0 0 0 0 1 0 Read CFGA register (ADBMS6830B: RDCFGA). WRCFGB WR48 0 0 0 0 0 1 0 0 1 0 0 Write CFGB register (ADBMS6830B: WRCFGB). RDCFGB RD48 0 0 0 0 0 1 0 0 1 1 0 Read CFGB register (ADBMS6830B: RDCFGB). RDFLAG RD48 0 0 0 0 ERR 1 1 0 0 1 0 Read FLAG register (ADBMS6830B: RDSTATC). RDSTAT RD48 0 0 0 0 0 1 1 0 1 0 0 Read STAT register (ADBMS6830B: RDSTATE). RDALLC RD160 0 0 0 0 0 0 1 0 0 0 0 Read All configuration, flag and status registers. RDSID RD48 0 0 0 0 0 1 0 1 1 0 0 Read SID register (ADBMS6830B: RDSID). RDALL commands are not available on the isoSPI daisy-chains. For more details, see the Communication Protocol section. Table 67. RDFLAG Parameter Bits ERR PAR SPIFLT Diagnostic Enable. 0 RDFLAG readout without artificial error injection. 1 RDFLAG readout with error injection. see the Snapshot Commands section). Table 68. Other Control Command Codes RSTCC CMD 0 0 0 0 0 1 0 1 1 1 0 Reset command counter (ADBMS6830B: RSTCC). SNAP CMD 0 0 0 0 0 1 0 1 1 0 1 Freeze result registers (ADBMS6830B: SNAP). UNSNAP CMD 0 0 0 0 0 1 0 1 1 1 1 Unfreeze result registers (ADBMS6830B: UNSNAP). groups increment the command counter. Table 69. CFGA Register Map

0 OCEN VS5 VS4 VS3 VS2[1:0] VS1[1:0]

1 INJTM INJECC 0 INJTS INJMON[1:0] INJOSC[1:0]

2 SOAK VS10 VS9 VS8 VS7 VS6

4 SPI3W GPIO1FE GPO6OD GPO5OD GPO4OD GPO3OD GPO2OD GPO1OD

5 VB2MUX VB1MUX SNAPST REFUP COMMBK ACCI[2:0]

Table 70. CFGA Bit Description 0 OC1ADC, OC2ADC, OC3ADC disabled. 1 OC1ADC, OC2ADC, OC3ADC enabled. must be followed by a new ADI1 command for the ADC behavior to update. 0 VB1ADC measures VBAT1 vs. SGND. 1 VB1ADC measures VBAT1 vs. VBAT2. change to this bit must be followed by a new command for the ADC behavior to update. 0 VB2ADC measures VBAT2 vs. SGND. 1 VB2ADC measures VBAT2 vs. VBAT1. Double polarity inversion due to negative LSB of VB2ADC. with the next ADI1 or ADI2 command. 000 IxACC, VBxACC accumulate 4 samples. 001 IxACC, VBxACC accumulate 8 samples. 010 IxACC, VBxACC accumulate 12 samples. 011 IxACC, VBxACC accumulate 16 samples. 100 IxACC, VBxACC accumulate 20 samples. 101 IxACC, VBxACC accumulate 24 samples. 110 IxACC, VBxACC accumulate 28 samples. 111 IxACC, VBxACC accumulate 32 samples. VS1 RW 00 Reference voltage for V1 measurement. 00 V1ADC and V2ADC measure V1 vs. SGND. 01 V1ADC and V2ADC measure V1 vs. VREF1P25. 10 V1ADC and V2ADC measure V1 vs. V3. 11 V1ADC and V2ADC measure V1 vs. V4. VS2 RW 00 Reference voltage for V2 measurement. 00 V1ADC and V2ADC measure V2 vs. SGND. 01 V1ADC and V2ADC measure V2 vs. VREF1P25. 10 V1ADC and V2ADC measure V2 vs. V3. 11 V1ADC and V2ADC measure V2 vs. V4. VS3 RW 0 Reference voltage for V3 measurement. 0 V1ADC and V2ADC measure V3 vs. SGND. 1 V1ADC and V2ADC measure V3 vs. VREF1P25. VS4 RW 0 Reference voltage for V4 measurement. 0 V1ADC and V2ADC measure V4 vs. SGND. 1 V1ADC and V2ADC measure V4 vs. VREF1P25. VS5 RW 0 Reference voltage for V5 measurement. 0 V1ADC and V2ADC measure V5 vs. SGND. 1 V1ADC and V2ADC measure V5 vs. VREF1P25. VS6 RW 0 Reference voltage for V6 measurement. 0 V1ADC and V2ADC measure V6 vs. SGND. 1 V1ADC and V2ADC measure V6 vs. VREF1P25. VS7 RW 0 Reference voltage for V7 measurement. 0 V1ADC measures V7 vs. SGND. 1 V1ADC measures V7 vs. VREF1P25. VS8 RW 0 Reference voltage for V8 measurement. 0 V1ADC measures V8 vs. SGND. 1 V1ADC measures V8 vs. VREF1P25. VS9 RW 0 Reference voltage for V9 measurement. 0 V2ADC measures V9 vs. SGND. 1 V2ADC measures V9 vs. VREF1P25. VS10 RW 0 Reference voltage for V10 measurement. 0 V2ADC measures V10 vs. SGND. 1 V2ADC measures V10 vs. VREF1P25. SOAK RW 000 Delays response of V1ADC and V2ADC to ADV command and further multi -measurements.

Rev. 0 | Page 51 of 97 Name Type Reset Value Description 010 500 µs of soak time. 011 1 ms of soak time. 100 2 ms of soak time. 101 10 ms of soak time. 110 20 ms of soak time. 111 150 ms of soak time. GPO1OD RW 1 GPO1 Open-Drain Mode Enable. 0 GPO1 pushed to VDD (GPO1C = 1) or pulled to GND (GPO1C = 0). 1 GPO1 high-impedance (GPO1C = 1) or pulled to GND (GPO1C = 0). GPO2OD RW 1 GPO2 Open-Drain Mode Enable. 0 GPO2 pushed to VDD (GPO2C = 1) or pulled to GND (GPO2C = 0). 1 GPO2 high-impedance (GPO2C = 1) or pulled to GND (GPO2C = 0). GPO3OD RW 1 GPO3 Open-Drain Mode Enable. 0 GPO3 pushed to VDD (GPO3C = 1) or pulled to GND (GPO3C = 0). 1 GPO3 high-impedance (GPO3C = 1) or pulled to GND (GPO3C = 0). GPO4OD RW 1 GPO4 Open-Drain Mode Enable. 0 GPO4 pushed to VDD (GPO4C = 1) or pulled to GND (GPO4C = 0). 1 GPO4 high-impedance (GPO4C = 1) or pulled to GND (GPO4C = 0). GPO5OD RW 1 GPO5 Open-Drain Mode Enable. 0 GPO5 pushed to VDD (GPO5C = 1) or pulled to GND (GPO5C = 0). 1 GPO5 high-impedance (GPO5C = 1) or pulled to GND (GPO5C = 0). GPO6OD RW 1 GPO6 Open-Drain Mode Enable. 0 GPO6 pushed to VDD (GPO6C = 0b01) or pulled to GND (GPO6C = 0b00). 1 GPO6 high-impedance (GPO6C = 0b01) or pulled to GND (GPO6C = 0b00). GPO1C RW 1 GPO1 Output State Control. 0 GPO1 pulled low to GND. 1 GPO1 pushed to VDD (GPO1OD = 0) or put to high-impedance state (GPO1OD = 1). GPO2C RW 1 GPO2 Output State Control. 0 GPO2 pulled low to GND. 1 GPO2 pushed to VDD (GPO2OD = 0) or put to high-impedance state (GPO2OD = 1). GPO3C RW 1 GPO3 Output State Control. 0 GPO3 pulled low to GND. 1 GPO3 pushed to VDD (GPO3OD = 0) or put to high-impedance state (GPO3OD = 1). GPO4C RW 1 GPO4 Output State Control. 0 GPO4 pulled low to GND. 1 GPO4 pushed to VDD (GPO4OD = 0) or put to high-impedance state (GPO4OD = 1). GPO5C RW 1 GPO5 Output State Control. 0 GPO5 pulled low to GND. 1 GPO5 pushed to VDD (GPO5OD = 0) or put to high-impedance state (GPO5OD = 1). GPO6C RW 01 GPO6 Output State Control. 00 GPO6 pulled low to GND. 01 GPO6 pushed to VDD (GPO6OD = 0) or put to high-impedance state (GPO6OD = 1). 10 GPO6 outputs 200 kHz (push-pull for GPO6OD = 0 and open-drain for GPO6OD = 1); readback disabled. 11 Reserved. GPIO1FE RW 0 GPIO1 Fault Output Enable. 0 GPIO1 controlled by GPIO1C or COMM register in case SPI controller usage. 1 GPIO1 outputs fault status. SPI3W RW 0 SPI Controller Mode Select. 0 4-wire: SDIM and SDOM on separate pins. 1 3-wire: SDIM and SDOM on the same pin. COMMBK RW 0 isoSPI Communication Break. 0 Communication propagates from the peripheral to the controller port (from Port A to Port B and vice versa depending on where communication is initiated). 1 No transmission from the peripheral to the controller port. REFUP RO 0 Indicates Powered Voltage References. 0 VREF1 and VREF2 are not (yet) powered. 1 VREF1 and VREF2 are powered. SNAPST RO 0 SNAP Status Indicator. 0 SNAP inactive. Result registers progress to SPI. 1 SNAP active. Result registers frozen until next UNSNAP command. INJTS RW 01 Thermal Shutdown Diagnostic Enable. 0 Normal operation. 1 Forces THSD flag, see note1. INJTM RW 0 Test mode Indicator Diagnostic Enable. 0 Normal operation.

INJECC RW 0 ECC Diagnostic Enable. 1 Inject bit error and trigger ECC logic to set SED1, SED2, MED1, and MED2. INJOSC RW 00 Clock Monitor Diagnostic Enable. 00 Regular clock applied to clock monitor. No-clock detector in regular mode. 01 Faster clock applied to clock monitor. No-clock detector in regular mode. 10 Slower clock applied to clock monitor. No-clock detector checks for clock stuck high. 11 Regular clock applied to clock monitor. No-clock detector checks for clock stuck low. INJMON RW 00 Supply Monitor and Deglitcher Diagnostic Enable. 00 Supply monitors operate normally. Deglitcher operates normally. 01 Supply monitors operate normally. Deglitcher mismatched forced to set OCMM flag. 10 Force undervoltage to trigger VDDUV, VREGUV, and VDIGUV checks. 11 Force overvoltage to trigger VREGOV, VDIGOV, VDE, and VDEL checks.

1 The host controller must keep log when setting the INJTS bit

to be asserted, but by itself does not trigger an internal reset. Table 71. CFGB Register Map

4 OCBX OCAX OCMODE[1:0] OC3GC OC2GC OC1GC OCOD

5 GPIO4C GPIO3C GPIO2C GPIO1C GPIO2EOC DIAGSEL[2:0]

Table 72. CFGB Bit Description OC1GC RW 0 OC1ADC Analog Input Gain Control. 0 OC1ADC Gain = 1 (OC1LSB = 5 mV). OC2GC RW 0 OC2ADC Analog Input Gain Control. 0 OC2ADC Gain = 1 (OC2LSB = 5 mV). OC3GC RW 0 OC3ADC Analog Input Gain Control. 0 OC3ADC Gain = 1 (OC3LSB = 5 mV). OC1TH RW 0000000 OC1ADC Overcurrent Threshold. Magnitude of signed 7 -bit result depends on gain setting. 0000000 OC1 output asserted irrespective of measured value. 0000001 OC1 output asserted when |OC1R| ≥ 1. 0000010 OC1 output asserted when |OC1R| ≥ 2. 0000011 OC1 output asserted when |OC1R| ≥ 3. 0111111 OC1 output asserted when |OC1R| ≥ 63. 1xxxxxx OC1 output is deasserted. CLRO command clears the OC1R result register to 10000000. OC2TH RW 0000000 OC2ADC Overcurrent Threshold. Magnitude of signed 7 -bit result depends on gain setting. 0000000 OC2 output asserted irrespective of measured value. 0000001 OC2 output asserted when |OC2R| ≥ 1. 0000010 OC2 output asserted when |OC2R| ≥ 2. 0000011 OC2 output asserted when |OC2R| ≥ 3. 0111111 OC2 output asserted when |OC2R| ≥ 63. 1xxxxxx OC2 output is deasserted. CLRO command clears the OC2R result register to 10000000. OC3TH RW 0000000 OC3ADC Overcurrent Threshold. Magnitude of signed 7 -bit result depends on gain setting.

Rev. 0 | Page 53 of 97 Name Type Reset Value Description 0000000 OC3 output asserted irrespective of measured value. 0000001 OC3 output asserted when |OC3R| ≥ 1. 0000010 OC3 output asserted when |OC3R| ≥ 2. 0000011 OC3 output asserted when |OC3R| ≥ 3. 0111111 OC3 output asserted when |OC3R| ≥ 63. 1xxxxxx OC3 output is deasserted. CLRO command clears the OC3R result register to 10000000. OCDGT RW 00 OC1ADC, OC2ADC, OC3ADC Overcurrent Deglitch Time Threshold. 00 1oo1. Deglitching disabled. OC event progresses directly to the output. No extra latency. 01 2oo3. OC event progresses when two out of three subsequent samples are above threshold. 10 4oo8. OC event progresses when four out of eight subsequent samples are above threshold. 11 7oo8. OC event progresses when seven out of eight subsequent samples are above threshold. OCMODE RW 00 OCA and OCB Output Mode Control. 00 OCA and OCB outputs are disabled and in high-impedance state. 01 OCA and OCB outputs are enabled in PWM1 mode. 10 OCA and OCB outputs are enabled in PWM2 mode. 11 OCA and OCB outputs are enabled in static mode. OCAX RW 0 OCA Output XOR Inverter. 0 OCA Output is not inverted. Active high. PWM period starts with high pulse. 1 OCA Output is inverted. Active low. PWM period starts with low pulse. OCBX RW 0 OCB Output XOR Inverter. 0 OCB Output is not inverted. Active high. PWM period starts with high pulse. 1 OCB Output is inverted. Active low. PWM period starts with low pulse. OCOD RW 1 OCA and OCB Output Open drain Enable. OCOD is ignored when OCMODE is set to 0b00. 0 OCA and OCB operate in push-pull mode and are pushed to VREG for logic level 1 or pulled to GND for logic level 0. 1 OCA and OCB operate in open-drain mode and are high-impedance for logic level 1 or pulled to GND for logic level 0. External pull-up resistor required in this mode. OCDP RW 0 OCA and OCB Output Pin reduced safety interval from OCEN rising edge to OCA and OCB output drivers activation. 0 Normal safety interval of 10 OCxADC conversion cycles. 1 Reduced safety interval of 3 OCxADC conversion cycles. DIAGSEL RW 000 IxADC and VBxADC Diagnostic Select for ADI1 and ADI2 diagnostic measurement commands. 000 No current injection. IxADC convert regular inputs (IxA vs. IxB). VBxADC convert regular inputs (VBATx pins depending on VBxMUX setting). 001 Current injected into IxA, VBATx pins. IxADC convert regular inputs. VBxADC convert regular inputs. 010 Current injected into IxB, SGND pins. IxADC convert regular inputs. VBxADC convert regular inputs. 011 Current injected into SxA pins. IxADC convert SxA vs. IxA. VBxADC convert regular inputs. 100 No current injection. IxADC convert SxA vs. IxA. VBxADC convert SGND vs. SGND (offset measurement). 101 No current injection. IxADC and VBxADC convert VDIV. 110 No current injection. IxADC convert scaled VREF2 version (nominal −0.125V). VBxADC convert scaled VREF2 version (nominal 2.375V). 111 Current injected into IxB pins. IxADC convert SxA vs. IxA. VBxADC convert regular inputs. GPIO1C RW 1 GPIO1 Output Control. 0 GPIO1 pulls down to GND. 1 GPIO1 output driver disabled, unless overruled by COMM register. GPIO2C RW 1 GPIO2 Output Control. 0 GPIO2 pulls down to GND. 1 GPIO2 output driver disabled, unless overruled by COMM register. GPIO3C RW 1 GPIO3 Output Control. 0 GPIO3 pulls down to GND. 1 GPIO3 output driver disabled, unless overruled by COMM register. GPIO4C RW 1 GPIO4 Output Control. 0 GPIO4 pulls down to GND. 1 GPIO4 output driver disabled, unless overruled by COMM register. GPIO2EOC RW 0 GPIO2 Toggle on OC1ADC End of Conversion Enable.

0 GPIO2 controlled by GPIO2C or COMM register. 1 GPIO2 toggles on end of conversion of OC1ADC. VREF1 to VDIV ratio listed in the Table 7. (1) and the bits that are not altered (0). Table 73. FLAG Register Map

0 RESERVED VDRUV OCMM2 OC3L OCAGD/CLRM2 OCAL OC1L

1 RESERVED VDDUV2 NOCLK2 REFFLT2 OCBGD2 OCBL OC2L

2 I2CNT[2:0]1 I1CNT[10:6]1

3 I1CNT[5:0]1 I1PHA[1:0]1

4 VREGOV2 VREGUV2 VDIGOV2 VDIGUV2 SED1 MED12 SED2 MED22

5 VDEL VDE2 0 SPIFLT RESET3 THSD3, 4 TMODE2 OSCFLT2

1 Bits are read-only and are not controlled by the CLRFLAG

2 Bits contribute to FAULT output on OCA, OCB and, if

output pins are set to the fault state.

3 Related events cause OCA, OCB, GPIOx, and GPOx to enter

Table 74. FLAG Bit Description 0 No OC1 threshold event passed deglitching. 1 OC1 threshold event detected and passed deglitching. 0 No OC2 threshold event passed deglitching. 1 OC2 threshold event detected and passed deglitching. 0 No OC3 threshold event passed deglitching. 1 OC3 threshold event detected and passed deglitching. 1 Majority Voter A Overcurrent Latch. 0 No OC event passed majority Voter A. 1 OC event detected that passed majority Voter A. 1 Majority Voter B Overcurrent Latch. 0 No OC event passed majority Voter B. 1 OC event detected that passed majority Voter B. 1 OCA Gate/Drain Mismatch Latch. Clear OC3 Min/Max. 0 OCA output reads back as expected. 1 Detected unexpected readback from OCA output while OCEN = 1. Clear operation also clears OC3MIN and OC3MAX registers. 1 OCB Gate/Drain Mismatch Latch. 0 OCB output reads back as expected.

Rev. 0 | Page 55 of 97 Name Type Reset Value Description 1 Detected unexpected readback from OCB output while OCEN = 1. OCMM RW1C 1 OC Configuration Mismatch Latch. 0 No internal mismatch detected. 1 Mismatch in redundant shadow copies of OCEN, OCTSEL, or OCDGT detected. I1PHA RO, FRZ 00 2-bit I1ADC/VB1ADC Phase Counter with four increments per sample. Resets with ADI1 commands. Rolls over. I1CNT RO, FRZ 0x000 11-bit I1ADC/VB1ADC Conversion Counter, when in continuous mode. Resets with ADI1 commands. Rolls over. I1CNT and I1PHA can be treated as a single counter I1CNTPHA[12:0] = [I1CNT, I1PHA]. I2CNT RO, FRZ 000 3-bit I2ADC/VB2ADC Conversion Counter, when in continuous mode. Resets with ADI1 while RD = 1 and ADI2 commands. Rolls over. SED1 RW1C 1 NVM1 1-bit ECC Latch. 0 No error detected in NVM1 and shadow registers. 1 Single bit error detected and autocorrected in NVM1 shadow registers. SED2 RW1C 1 NVM2 1-bit ECC Latch. 0 No error detected in NVM2 and shadow registers. 1 Single bit error detected and autocorrected in NVM2 shadow registers. MED1 RW1C 1 NVM1 multi-bit ECC Latch. 0 No uncorrectable error detected in NVM1 and shadow registers. 1 Uncorrectable multi-bit error detected in NVM1 or shadow registers. MED2 RW1C 1 NVM2 multi-bit ECC Latch. 0 No uncorrectable error detected in NVM2 and shadow registers. 1 Uncorrectable multi-bit error detected in NVM2 or shadow registers. VREGUV RW1C 1 VREG Undervoltage Latch. 0 No undervoltage detected on VREG supply. 1 Undervoltage event on VREG supply detected. VREGOV RW1C 1 VREG Overvoltage Latch. 0 No overvoltage detected on internal VREG supply. 1 Overvoltage event on internal VREG supply detected. VDDUV RW1C 1 VDD Undervoltage Latch. 0 No undervoltage detected on VDD supply. 1 Undervoltage event on VDD supply detected. VDRUV RW1C 1 Drive Undervoltage Latch (VDD supply for DRIVE output). 0 No DRIVE undervoltage detected on VDD supply. 1 DRIVE undervoltage event on VDD supply detected. VDIGUV RW1C 1 VDIG Undervoltage Latch. 0 No undervoltage detected on internal VDIG supply. 1 Undervoltage event on internal VDIG supply detected. VDIGOV RW1C 1 VDIG Overvoltage Latch. 0 No overvoltage detected on internal VDIG supply. 1 Overvoltage event on internal VDIG supply detected. VDE RW1C 1 Voltage Domain Event Latch. 0 No mismatch on internal supply domains detected. 1 Mismatch on internal VREG or GND domains detected. VDEL RW1C 1 Voltage Domain Diagnostic Latch. See INJMON bit field. 0 Not all domain comparators report mismatch. 1 All VREG and GND domain comparators report mismatch. OSCFLT RW1C 1 Oscillator Frequency Fault Latch. 0 No OSC1 vs. OSC2 frequency comparison fault detected. 1 OSC1 vs. OSC2 frequency comparison fault detected. NOCLK RW1C 1 No Clock Fault Latch. 0 No OSC1 stuck event detected. 1 OSC1 stuck event detected. SPIFLT RW1C 1 SPI Read Fault Latch. 0 No SPI SDO mismatch detected. 1 SPI SDO mismatch detected. TMODE RW1C 1 Test mode Indicator Latch. 0 No activation of factory test mode detected. 1 Activation of factory test mode detected. RESET RW1C 1 Reset Indicator Latch. 0 No reset event detected since last clear. 1 Reset event detected since last clear. THSD RW1C 0 1 Thermal Shutdown Indicator Latch. 0 No thermal shutdown detected. 1 Thermal shutdown detected, not cleared by SRST, see note 1.

that are implemented redundantly. be read with the RDSTAT command. Table 75. STAT Register Map

1 I2CAL I1CAL 0000 DER[1:0]

3 GPO6H GPO5H GPO4H GPO3H GPO2H GPO1H GPO6L GPO5L

4 GPO4L GPO3L GPO2L GPO1L GPIO4L GPIO3L GPIO2L GPIO1L

5 REVID[3:0] 0000

The RDSID command is used to read the SID register. Table 76. SID Register Map

0 SID[7:0]

1 SID[15:8]

2 SID[23:16]

3 SID[31:24]

4 SID[39:32]

5 SID[47] DEVID[5:0]/SID[46:41] SID[40]

Table 77. SID and STAT Bit Description SID RO As per part 48-bit Unique Serial Identifier. The DEVID uses 6 bits of the SID. DEVID RO As per derivative Device Derivative Identifier is part of the serial identifier SDI[46:41]. REVID RO As per revision Device Revision Identifier. DER RO As per derivative Derivative Code. OCAP RO x OCA Pin State, when OCMODE = 11 or for Diagnostics. 0 OCA pin reads back as low. 1 OCA pin reads back as high. OCBP RO x OCB Pin State, when OCMODE = 11 or for Diagnostics. 0 OCB pin reads back as low. 1 OCB pin reads back as high. I1CAL RO 0 I1ADC Initialization Status. 0 I1ADC has not yet completed initialization. 1 I1ADC has completed initialization. I2CAL RO 0 I2ADC Initialization Status. 0 I2ADC has not yet completed initialization. 1 I2ADC has completed initialization. GPIO1L RO 1 GPIO1 Read Back.

1 GPIO1 reads back as high, when pulled up externally. GPIO2L RO 1 GPIO2 Read Back. 1 GPIO2 reads back as high, when pulled up externally. GPIO3L RO 1 GPIO3 Read Back. 1 GPIO3 reads back as high, when pulled up externally. GPIO4L RO 1 GPIO4 Read Back. GPO1L RO 1 GPO1 Low-Level Read Back. 0 GPO1 reads back below low-level threshold vs. GND. 1 GPO1 reads back above low-level threshold vs. GND. GPO1H RO 1 GPO1 High-Level Read Back. 0 GPO1 reads back below high-level threshold vs. VDD. 1 GPO1 reads back above high-level threshold vs. VDD. GPO2L RO 1 GPO2 Low-Level Read Back. 0 GPO2 reads back below low-level threshold vs. GND. 1 GPO2 reads back above low-level threshold vs. GND. GPO2H RO 1 GPO2 High-Level Read Back. 0 GPO2 reads back below high-level threshold vs. VDD. 1 GPO2 reads back above high-level threshold vs. VDD. GPO3L RO 1 GPO1 Low-Level Read Back. 0 GPO1 reads back below low-level threshold vs. GND. 1 GPO1 reads back above low-level threshold vs. GND. GPO3H RO 1 GPO3 High-Level Read Back. 0 GPO3 reads back below high-level threshold vs. VDD. 1 GPO3 reads back above high-level threshold vs. VDD. GPO4L RO 1 GPO4 Low-Level Read Back. 0 GPO4 reads back below low-level threshold vs. GND. 1 GPO4 reads back above low-level threshold vs. GND. GPO4H RO 1 GPO4 High-Level Read Back. 0 GPO4 reads back below high-level threshold vs. VDD. 1 GPO4 reads back above high-level threshold vs. VDD. GPO5L RO 1 GPO5 Low-Level Read Back. 0 GPO5 reads back below low-level threshold vs. GND. 1 GPO5 reads back above low-level threshold vs. GND. GPO5H RO 1 GPO5 High-Level Read Back. 0 GPO5 reads back below high-level threshold vs. VDD. 1 GPO5 reads back above high-level threshold vs. VDD. GPO6L RO 1 GPO6 Low-Level Read Back. 0 GPO6 reads back below low-level threshold vs. GND. 1 GPO6 reads back above low-level threshold vs. GND. GPO6H RO 1 GPO6 High-Level Read Back. 0 GPO6 reads back below high-level threshold vs. VDD. 1 GPO6 reads back above high-level threshold vs. VDD. flag bits, and most status bits by one single read command. RDALL commands are not available on the isoSPI daisy-chains. For more details, see the Communication Protocol section. Table 78. RDALLC Return Values

0 OCEN VS5 VS4 VS3 VS2 VS1

1 INJTM INJECC 0 INJTS INJMON INJOSC

5 VB2MUX VB1MUX RESERVED COMMBK ACCI

Rev. 0 | Page 58 of 97 BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

9 OCTSEL 0 0 OCDP 0 OCDGT

10 OCBX OCAX OCMODE OC3GC OC2GC OC1GC OCOD

11 GPIO4C GPIO3C GPIO2C GPIO1C GPIO2EOC DIAGSEL

16 I2CNT2:0 I1CNT10:6

17 I1CNT5:0 I1PHA[1:0]

Note: the SRST command, but only after a power-on-reset or through the CLRFLAG command. Soft Reset Command The Soft Reset command (SRST) quickly resets all state machines and memory registers and initializes all the devices in the daisy-chain. The Soft Reset command only needs enough time to propagate up the stack to the next device, after which the device initializes. After t WA K E, all the ADBMS2950B devices enter the STANDBY state and are ready to receive new commands. From the STANDBY state, they automatically transition to the REFUP state (for more details, see the Core State Description section). The host controller must keep log when setting the INJTS bit for requesting the THSD bit to be asserted. After successfully reading THSD, the INJTS bit must be cleared via WRCFGA and the THSD bit must be cleared through CLRFLAG. If a SRST is issued before clearing THSD, the FLAG register reports RESET and THSD bits being set, same as if there is a thermal shutdown. Setting INJTS requests the THSD to be asserted, but by itself does not trigger an internal reset. Serial ID Each ADBMS2950B is programmed at the factory with a unique 48-bit serial identification code (SID) as a part of the internal non-volatile memory NVM1. After power-up or reset, the non-volatile memories are read, and the SID is stored into a volatile register that can be read through the RDSID command. Because of the non-redundant implementation, faults in the SID register cannot be detected. Snapshot Commands To enable reading of coherent data from one ADBMS2950B or several devices in a daisy-chain, the snap command allows freezing of the continuously updated result registers. After sending the snap command, the host can read them at convenience before releasing the freeze by an unsnap command. During the freeze, the ADCs continue to measure. Conversions are accumulated internally to provide IxACC, VBxACC results together with the latest Ix, VBx results once the unsnap command is sent. Sending an additional snap command while the result registers are already frozen does not take a new snapshot. To trigger a new register update while registers are frozen, the host must send a sequence of two commands: unsnap and snap. The CFGA register SNAPST bit indicates the freeze status. Upon reception of a snap or unsnap command, the command counter is incremented. Registers and bits that are subject to the snap protocol are marked with FRZ in the Type column of the register and bit descriptions (for example, see the I1, I2, VB1, VB2, I1CNT, I2CNT, and I1PHA registers). GENERAL-PURPOSE IO PINS The ADBMS2950B features six GPO pins to fulfill the following functions:

• General-purpose static output signals.
• Control of external high-voltage switches, for example, MOSFETs, to reduce leakage in high-voltage resistive dividers when measurement is not needed or to control the isolation measurement sequences as shown in the Typical Application section.
• Control of start-up self-test sequences of external circuitry.
• Additional chip-selects where more than one SPI peripheral must be controlled through the COMM interface. The GPOs provide the following features:
• Set the output state (GPO1C to GPO6C).
• Configurable open-drain mode or push-pull mode, up to VDD voltage (GPO1OD to GPO6OD).
• Dual-threshold readback (GPO1H to GPO6H and GPO1L to GPO6L).

• When set to open-drain mode through GPOxOD = 1 and to high-impedance state through GPOxC = 1, the GPOs become inputs effectively.
• GPO6 can be configured to output 200 kHz, 50% duty-cycle square wave signal (GPO6C). The ADBMS2950B features four GPIO pins to fulfill the following functions:
• General-purpose static input/output signals.
• Connectivity to local SPI or I2C peripheral (see COMM Interface).
• Fault Output. The GPIOs provide the following features:
• Open-drain output control up to VREG voltage (GPIO1C to GPIO4C).
• Single-threshold readback (GPIO1L to GPIO4L).
• GPIO1 can output the fault status of the device (GPIO1FE).
• GPIO2 can signal the end-of-conversion of the OC1ADC (GPIO2EOC). An external SPI or I2C peripheral can be connected to the GPIO/GPO pins. Often, this is an EEPROM to store calibration data, for example, the shunt resistance value of the ratios of external resistive dividers. Access to external serial peripheral devices is provided through the COMM commands controlled by the host. The following serial controller interface connections are supported:
• I2C peripheral devices.
• 3-wire SPI peripheral devices.
• 4-wire SPI peripheral devices. Additional chip-select lines for SPI communication can be provided through the GPOs. GPO Operation The six GPOs are controlled through the configuration A register CFGA. It provides the open-drain mode enable bits (GPO1OD to GPO6OD) and output state control bits (GPO1C to GPO6C) for each individual GPOx pin. Additionally, for the GPO6, a clock output mode can be activated through its 2-bit GPO6C configuration bit field. After reset, all GPOs default to the high-impedance mode.

Figure 41. GPO Model

1. The GPO6L and GPO6H bits are not defined, where

GPO6 has been configured in clock output mode.

1. The GPOxL and GPOxH read-only bits are

signals or to extreme time constants.

1. When a GPOx pin is configured in open-drain mode

the GPOxH readback bit should not be used. Table 79. Relation of GPOxOD, GPOxC Configuration to 0 0 Push-Pull Pull low to GND. 0 1 Push-Pull Push high to VDD. 1 0 Open-Drain Pull low to GND. 1 1 Open-Drain High impedance.

default to a high-impedance state. output pulse every time the OC1ADC completes a conversion. used to overrule the COMM function and to force a GPIO low. The actual state of the GPIOs is available in the STAT register. be dynamic and are not further synchronized nor gated. in the STAT register read zero, the GPIO is confirmed to be low. rising clock edge and differ only in the Idle clock state. of the GPOx through a write to CFGA. Table 80. Serial Controller Pin Assignment Table 81. Serial Controller Signal Description CSBM, CSBMx SPI Controller Chip Select Output. SDIM SPI Controller Data Input. SDIOM SPI Controller Data Input/Output. SDOM SPI Controller Data Output. SCKM SPI Controller Clock Output. SDA I2C Controller Data Input/Output. SCL I2C Controller Clock Output. after (FCOM bit fields) the transaction of the individual bytes. Table 82. COMM Command Codes WRCOMM WR48 1 1 1 0 0 1 0 0 0 0 1 Write COMM register (ADBMS6830B: WRCOMM). RDCOMM RD48 1 1 1 0 0 1 0 0 0 1 0 Read COMM register (ADBMS6830B: RDCOMM). STCOMM CMD 1 1 1 0 0 1 0 0 0 1 1 Send COMM register (ADBMS6830B: STCOMM). Table 83. COMM Register Map

0 ICOM0[3:0] FCOM0[3:0]

1 D0[7:0]

2 ICOM1[3:0] FCOM1[3:0]

3 D1[7:0]

4 ICOM2[3:0] FCOM2[3:0]

5 D2[7:0]

Table 84. COMM Bit Descriptions D0, 1, 2 RW 0x00 Transmit Data Byte 0, 1, 2. Receive Data Byte 0, 1, 2. ICOM0, 1, 2 RW 0000 Control action prior transaction of byte D0, D1, D2. Result of control action. 0000 I2C: BLANK. I2C: SDA is held low between bytes. 0001 I2C: STOP. I2C: Controller generated a STOP. 0110 I2C: START. I2C: Controller generated a START. 0111 I2C: No transmit. I2C: SDA is held high between bytes. 1000 SPI: Drive CSBM low. SPI: Always 0111. 1001 SPI: Drive CSBM high, clock and data continues. 1010 SPI: Drive CSBM high, then low. 1111 SPI: No transmit, release outputs, remaining data ignored. Other Reserved, undetermined behavior. FCOM0, 1, 2 RW 0000 Control action after transaction byte D0, D1, D2. Result of control action. 0000 I2C: Controller ACK on 9th clock. SPI: Holds CSBM low after byte transmission. I2C: Controller generated an ACK. 0001 I2C: Peripheral generated an ACK, Controller a STOP. 0111 I2C: Peripheral generated an ACK. 1000 I2C: Controller NACK on 9th clock. SPI: Holds CSBM low after byte transmission. 1001 I2C: Controller NACK followed by STOP. SPI: Transitions CSBM high after byte transmission. I2C: Peripheral generated a NACK, Controller a STOP. 1111 SPI: Read. I2C: Peripheral generated a NACK. Other Reserved, undetermined behavior. clock cycles (3 bytes) per data byte without releasing CSB high. the length of a daisy-chain, and the data is do not care. of the message and released high after the last byte. controller interfaces are as shown in Figure 44 and Figure 45.

with a specified minimum of 100 ns. Table 86. I2C Controller Timing with a specified minimum of 100 ns.

1. Ensure that GPIOs/GPOs used for SPI transactions

manually asserted through CFGA.

1. Write data and control action through WRCOMM.
2. Perform transmission through STCOMM: 4 bytes for

not care, for example, it can be set to all 0x00.

1. Get data received during transmission through

data is written to the peripheral only).

1. Continue with step 2 for any additional bytes.
2. Write data and control action through WRCOMM.
3. Perform transmission through STCOMM.
4. Get data received during transmission through
5. Write data and control action via WRCOMM for the
6. Perform transmission through STCOMM.

when to stop the transaction.

1. Get received data during transmission via RDCOMM.

WRCFGA de-asserting the used GPOx.

Rev. 0 | Page 65 of 97 1. Ensure that the GPIOs used for I2C transactions are not actively forced low through CFGB register setting, meaning GPIO3C and GPIO4C must be at their default value (1) to release the pins. 2. Write data and control action through WRCOMM. 3. Perform transmission through STCOMM: 4 bytes for CMD+PEC and 3 bytes per byte to be transmitted, maximum 9 bytes, independent of the length of the daisy-chain as all ICs of the daisy-chain perform the transmission simultaneously (no daisy-chain shift register activated for this command). The data is do not care, for example, it can be set to all 0x00. 4. Get data received during transmission via RDCOMM if required. 5. Continue with step 2 for any additional bytes. The following example assumes an I 2C EEPROM as 24LC02BHT-E/OT from Microchip connected to the I2C controller interface of the ADBMS2950B. It shows writing one byte to an address and reading it back. First, write a byte (0x8E) to address 0xA0, and do the following steps: 1. Write data and control action through WRCOMM. ICOM0 = 0x6 (I 2C START), FCOM0 = 0x8 (I2C: Controller NACK on 9th clock) ICOM1 = 0x0 (I2C BLANK), FCOM1 = 0x0 (I2C: Controller ACK on 9th clock) ICOM2 = 0x0 (I2C BLANK), FCOM2 = 0x9 (Controller NACK followed by STOP) DATA0 = 0xA0, DATA1 = 0x00, DATA2 = 0x8E 2. Perform transmission through STCOMM. STCOMM (4 bytes for CMD+PEC) followed by 9 bytes. Next, perform a Read operation by first writing the memory read address to I 2C peripheral write address: 1. Write data and control action through WRCOMM. ICOM0 = 0x6 (I2C START), FCOM0 = 0x8 (I2C: Controller NACK on 9th clock) ICOM1 = 0x0 (I2C BLANK), FCOM1 = 0x0 (I2C: Controller ACK on 9th clock) ICOM2 = 0x6 (I2C START), FCOM0 = 0x8 (I2C: Controller NACK on 9th clock) DATA0 = 0xA0, DATA1 = 0x00, DATA2 = 0xA1 2. Perform transmission through STCOMM. STCOMM (4 bytes for CMD+PEC) followed by 9 bytes. And finally, read back the byte: 1. Write data and control action through WRCOMM for the last two remaining bytes. 2. ICOM0 = 0x0 (I2C BLANK), FCOM0 = 0x9 (Controller NACK followed by STOP) ICOM1 = 0x7 (I2C No transmit), FCOM1 = 0x9 (Controller NACK followed by STOP) ICOM2 = 0x7 (I2C No transmit), FCOM2 = 0x9 (Controller NACK followed by STOP) DATA0 = 0xFF , DATA1 = 0x00, DATA2 = 0x00 (2nd and 3rd byte are do not care) 3. Perform transmission through STCOMM. STCOMM (4 bytes for CMD+PEC) followed by 9 bytes. 4. Get received data during transmission through RDCOMM. DATA0 (Contains 0x8E) The specifics of the write and read address depends on the peripheral that is connected. The I 2C clock rate depends on the frequency of the (iso)SPI clock. It might be necessary to slow down the (iso)SPI clock to not exceed the maximum supported frequency of the I 2C peripheral. ADBMS6830B COMPATIBLE COMMANDS The ADBMS2950B supports all read and write commands of the cell monitors ADBMS6830B to allow operation of daisy- chains consisting of both device types as shown in SPI and isoSPI Interface Topologies section. The Command Code tables show in brackets the Command Code name of the identical ADBMS6830B code. For example, the RDI command is identical to the RDCV A command and has an alternative ADBMS6830B compatible code RDFCA to which the ADBMS2950B responds as it is an RDI command. Also, certain poll or 4-byte-only commands are shared between the ADBMS2950B and ADBMS6830B. For example, the ADI1 command is identical to the ADCV command and ADI2 is identical to ADCV . Certain exceptions apply in the case of ADI1 and ADI2 as listed in the Table 41. Commands without the noted ADBMS6830B code are ignored by the cell monitors and the ADBMS6830B codes that are not listed here, for example, ADAX and ADAX2, are ignored by the ADBMS2950B. This allows certain actions to be triggered in one device type only. Table 87 shows the additional compatible read and write ADBMS6830B command codes. These codes do not have an internal effect on the ADBMS2950B other than behaving as a read command returning do not care data with a valid DPEC or behaving as a write command with the data written being do not care and incrementing the command counter if the DPEC is valid for the do not care data.

Table 87. Additional ADBMS6830B Compatible Command Codes

Rev. 0 | Page 67 of 97 In some cases, the application circuits shown in this section are simplified to show various concepts in a small space. Some components may be omitted. Analog Devices offers full- reference design circuits for the ADBMS2950B that are validated against common requirements for industrial systems. For full-reference designs and questions about specific use cases, contact a local Analog Devices sales office. TYPICAL APPLICATION A typical application of the ADBMS2950B used in a battery junction box is shown in Figure 46. It features the measurement of battery pack voltage and current, high-voltage-system to chassis-GND isolation resistance, link and precharge voltage and shunt resistor temperature. The ADBMS2950B is put into an isoSPI communication daisy-chain together with the ADBMS6830B cell monitors according to Figure 20. GPOs are used to control external high-voltage N-channel MOSFETS to either reduce battery pack leakage when the system is shut down or to toggle the bias states of the isolation resistance measurement. An external I 2C non-volatile memory is connected to the GPIOs to store board calibration parameters such as the shunt resistance or resistive-divider values. The circuit in Figure 46 uses the VBAT1 input to measure the overall battery pack voltage (BAT+ vs. BAT−). When the BMS controller closes the relay toward the chassis-GND, and GPO6 toggles the MOSFET, the VBAT2 input can trace the voltage response continuously and synchronously to the VBAT1 measurement, which enables isolation resistance measurement in noisy environments with minimum error. When the relay and the MOSFET are open, VBAT2 provides a synchronous and continuous mean to measure the pack voltage redundantly. However, where redundant pack voltage monitoring is required permanently, also during isolation resistance measurement, and accuracy of the redundant measurement is key, VBAT2 might use a voltage divider symmetric to the VBAT1 resistor network. The chassis-GND measurement circuitry can then be connected to one of the V1 to V10 inputs. For good noise filtering, the BMS controller can still trigger VxADC measurements during isolation resistance measurement at a high rate and extract the synchronous VBxADC measurements in software to perform the isolation resistance calculations with minimum error. Figure 46. Typical ADBMS2950B Application

pin supplies the DRIVE regulator, and the GPO output stages. the ADBMS2950B, as described in the following sections. Figure 47. ADBMS2950B Power Supply Options ADuM derivative from the Analog Devices isoPower series. of the maximum GPO drive voltage being also limited to 5V . drive N-channel MOSFETS directly through the GPOs. pump that actively pulls-down the output when not enabled. The lower left drawing of Figure 47 shows this diode for clarity. as shown in Figure 46, Figure 47 upper left, and Figure 48.

Rev. 0 | Page 71 of 97 The polarity of the IxADC measurement results is different for the two channels. With the recommended connection as described above, channel I1 battery current is negative when discharging (IxB > IxA) and positive when charging (IxA > IxB); channel I2 inverse. The host controller software can invert the measurement quantities as required. The shunt resistor shorts all current sense inputs to GND, which simplifies the input protection. Additionally, the ADBMS2950B has internal ESD protection on all inputs as shown in the Protection Features section. To further increase protection, an external RC filter can be connected to the current sense inputs as shown in Figure 51. The additional filtering is not required for the IxADC inputs because of the preamplifier having a low-pass filter characteristic. Still, the buffers in front of the OCxADCs do not have this low-pass filter characteristic, which allows to capture short current peaks through those fast ADCs if required. On the other hand, the parasitic inductance of the shunt resistor can cause an additional voltage drop during fast current transients (di/dt), which could cause false overcurrent measurements and false overcurrent alerts when a short deglitch time configuration (OCDGT) is used. The external RC filter can compensate for this effect and also reject common mode signals. RC Filter Selection If the RC filter at the input matches the RL of the shunt (R × C = L ÷ RSHUNT), the measured voltage follows the actual current in an optimum way. The inductance of typical 50 μΩ to 100 μΩ bus bar type shunts is on the order of 1 nH. The shunt manufacturer can be consulted for measurement data if required. A simple recommendation is to set the time constant of the RC filter to the maximum value that is still acceptable for measuring the shortest current spikes to be detected by the overcurrent ADCs. Alternatively, the RC filter can be adjusted to yield the right response to a current step or ramp applied to the shunt. Similar to the compensation that is done for scope probes, but in typical cases the resulting time constants are significantly shorter than what is required for fast overcurrent detection within single-digit multiples of the OCxADC conversion time, thus the first approach fits in typical use cases. The series resistors can be up to 220 Ω per input; larger values should be avoided as they could cause additional offset errors due to pin leakage currents. While low resistor and high capacitor values are preferred for measurement, resistor values in the range from 120 Ω to 150 Ω are recommended for robust diagnostics of the shunt connectivity. The overcurrent detection deglitch time setting (OCDGT) allows additional digital filtering to avoid false positive events in the presence of current spikes. A good compromise for detecting fast current events and filtering high frequency signals is an RC setting of 120 Ω (Rp) and 220 nF (Cp) for all common mode input filters. Because of the single SxA pins per channel, differential filter capacitors should not be added to the current and overcurrent sense input pins as they lead to imbalanced filtering between the Sx and Ix measurements and between the OC3ADC and the other channels. On the other hand, a mismatch between the common mode filters could cause a common mode to differential conversion during AC signals. With the time constant of the RC filter being very short, 26 µs for the recommended RC values, and the mismatch between filters being no more than 10%, the error is averaged out over the IxADC conversion time. An error signal could become visible during the shorter OCxADC conversion time. Assuming a common mode step input signal and 10% RC mismatch, the false differential signal could reach 5% of the step as shown in following calculation. Using the exponential equation describing the voltage at the capacitor of the RC relative to the input signal: V OUT ÷ VIN = 1 − e(−t ÷ τ), where τ = R × C The relative output signal with different time constant after one OCxADC conversion time becomes:

• −10% RC error: RC = 23 µs: 1 − e(−62/23) = 93%
• +10% RC error: RC = 29 µs: 1 − e(−62/29) = 88% The resulting differential signal is 5% of the step. After three OCxADC conversion times, the relative differential signal is decreased to only 1%. Common-mode input signals can be avoided by design and by following the layout rules on the shunt's GND connection that eliminates most signal on the IxA inputs as they are on the GND side of the shunt. This ensures most of the differential sense signal is seen on the IxB pins only. It significantly reduces common mode to differential signal conversion of the values calculated above. Additionally, it avoids OCxADC false trigger events even with short deglitch time settings. Current Sense Layout Recommendation Figure 51 shows the recommended current sense input RC filters. The placement and layout of the current sense input circuitry should be symmetric on all inputs as shown in the layout recommendation along the horizontal axis. This way, temperature gradients that are more appropriate to appear along the vertical axis do not cause differential thermocouple voltage in the sense lines. Instead, all connection points (pad to component, trace to via) are at the same temperature, and the resulting thermocouple voltage that may develop is canceled out. In that sense, it is also recommended to have any required vias within a differential pair to be close together to ensure good thermal coupling between them. For the same reason, any connection points on the PCB should be at same temperature, also the sense pads or pins of the shunt resistor should be at the same temperature to minimize thermocouple voltages that lead to offset errors. Symmetric heat dissipation of the shunt along

the figures in this chapter) helps to achieve this goal. of all capacitors between chassis-GND and the HV network. components cause chassis ground to HV network noise. Figure 51. Current Sense Input Filtering Schematic

Figure 58. Surface Mounted Shunt Layout Solder Paste required frequencies, are recommended to be placed. not exceed 30 cm in typical applications. Sense Layout Recommendation section. measurements only above a minimum current level. additional protection and filtering components can be ensured. a good choice with enough headroom to both limits.

Figure 64. Shunt Resistor with a Center Tap Filter, a cut-off frequency of 1 kHz or smaller is recommended.

Figure 75. IxADC Filter Transfer Function for ACCN 4 to 16 Without External RC

Figure 77. VBxADC Filter Transfer Function for ACCN 4 to 16

VxADC due to its non-continuous operation. Figure 81. VxADC with Average Filter Transfer Function

• Lossless and continuous sampling of the current sense input.
• Equal sample weighting and true average measurement.
• Precise time measurement to integrate the current measurements into charge. The ADBMS2950B provides all functionalities to fulfill those requirements. The first order delta-sigma ADCs have an over- sampling rate of 4.1 MHz, can run continuously on the current (and VBAT) channels, and weigh all samples equally providing the exact average of the input signal over the conversion window, which is either 1 ms (Ix registers) or ACCN × 1 ms (IxACC registers – also see ACCI configuration). The host controller can decide to either read the Ix or the IxACC registers continuously depending on the current measurement period requirement. In both cases, there is no loss of sampling time (no holes) on the inputs. The host controller can synchronize to the continuously updated conversion result registers by reading the conversion (phase) counter I1CNT, I1PHA. The I1CNT register increments by one with every 1 ms conversion result. Assuming an ACCN setting of 8 (ACCI = 1), with the 8th of those 1 ms conversion results, the accumulated registers (IxACC) are updated with the sum of 8 conversions. Consequently, this happens every time the I1CNT value reports a multiple of 8. The conversion phase counter I1PHA provides additional resolution by adding 4 sub-counts per I1CNT count. If the I1CNT, I1PHA counters are treated as a single counter (I1CNTPHA[12:0]), the 1 ms conversion results are updated every time the host reads 0, 4, 8, 12, …. and the 8 ms accumulated conversion results (assuming ACCI = 1) are updated every time the host reads 0, 32, 64, 96, … For any value in between, the conversion result register is not updated, giving the host enough time to read the results. The snap and unsnap commands ensure coherent reading of the I1CNTPHA and Ix (or IxACC) registers retrieved via separate read commands. Lossless Continuous Conversion Reading This chapter shows a procedure to read every 8 ms accumulated conversion (IxACC update rate for ACCN = 8) without missing any result. Not to miss any conversion, the host must read at a period that is shorter than the shortest possible update rate of the IxACC registers, which occurs at the maximum specified IC oscillator frequency. The oscillator frequency of the ADBMS2950B is specified to be within ±10% over the full- operating temperature range. Consequently, the host must read every 7.2 ms or faster (the IxACC registers are updated nominally every 8 ms for ACCN = 8). Table 89 shows the timings of the I1CNT and number of IxACC conversions (CntACC) acquired, assuming a host reads every 7 ms. The values I1CNT and CntACC are shown for a device running at minimum (MIN), nominal (NOM), and

• SNAP (to freeze all the result registers)
• RDFLAG (to get I1CNT, I1PHA)
• RDIACC (to get the accumulated conversion results)
• … (any other readings, for example, VBxACC results)
• UNSNAP (to un-freeze all result registers) This sequence is equivalent to:
• UNSNAP (to un-freeze all result registers)
• SNAP (to freeze all the result registers)
• RDFLAG (to get I1CNT, I1PHA)
• RDIACC (to get the accumulated conversion results)
• … (any other readings without final unsnap) The advantage of the second sequence is that there is an intrinsic check that all commands are executed correctly without relying on the following read command that checks the command counter increment after the final unsnap of the first sequence. The initial commands unsnap, snap used here ensure a new snapshot of the result registers is taken before executing the read commands. When implementing this approach, the unsnap, snap commands must precede any other sequences that read results marked with the FRZ identify in the register and bit description tables. This ensures coherent data reading, for details, see the Snapshot Commands section. In both the sequences, the snapshot commands ensure that I1CNT, I1PHA, and conversion results are read coherently allowing the host to decide for every dataset if a new result is read (CntACC incremented by one in Table 89) or if the dataset is old and can be discarded. For example, Table 89 shows the column CntACC-MIN did not increment between #4 and #5 remaining at 3 conversions. Still, a hypothetical device running at the nominal oscillator frequency has already provided the 4th sample as shown in column CntACC-NOM. Table 89 also shows the I1CNT rolling over to 0 after the maximum value, which is 2 11 − 1 = 2047. The host controller must take this into account when evaluating I1CNT. A simple way is to check if I1CNT is bigger or equal than N × 8, where N initially starts at 1, is incremented by 1 every time the check is true (new conversion) and is reset to 0 every time the current read I1CNT value is smaller than the previous one. After starting continuous measurement, set initial values: INIT N = 1 I1CNT_OLD = 0 ENDINIT In the measurement loop, evaluate the dataset read through the above-described sequence (ReadSequence) and do the following: LOOP ReadSequence() IF I1CNT < I1CNT_OLD N = 0 ENDIF IF I1CNT ≥ N × 8 N = N + 1 // process new conversions read from IxACC (and VBxACC) ELSE // Old conversion was already read // nothing to do I1CNT_OLD = I1CNT ENDIF ENDLOOP Note that this example assumes ACCN = 8 and must be adjusted for different settings of ACCI. Table 89 assumes that the host activates the continuous current measurement (on I1ADC or I1ADC and I2ADC) through ADI1 command at the time t = 0s. The first reading happens directly afterwards and subsequently every 7 ms. # is the index of the read sequence.

Table 89. I1CNT and IxACC Update Timing for Minimum, Nominal and Maximum Oscillator Frequency Assuming ACCN = 8

timer in the host controller. (tCONV ,NOM), and maximum (tC O N V,M I N) oscillator frequency. Table 90. Calculating tCONV from I1CNT drift of the shunt (gcShuntTC).

Figure 82. Figure 82. ADBMS2950B Footprint, Distribution of Vias, and Solder Paste

Figure 83. Outline Dimensions

Figure 84. Legend registered trademarks are the property of their respective owners.