ADBMS1818 (Rev.B)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 92
Technical content
18-Cell Battery Monitor with Daisy Chain Interface Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Measures up to 18 battery cells in series ►3 mV maximum total measurement error ►Stackable architecture for high voltage systems ►Built-in isoSPI interface ►1 Mb isolated serial communications ►Uses a single twisted pair, up to 100 meters ►Low EMI susceptibility and emissions ►Bidirectional for broken wire protection ►290 µs to measure all cells in a system ►Synchronized voltage and current measurement ►16-bit Δ-Σ ADC with programmable third-order noise filter ►Passive cell balancing up to 200 mA (maximum) with program- mable pulse‑ width modulation ►9 general-purpose digital I/O or analog inputs ►Temperature or other sensor inputs ►Configurable as an I2C or SPI master ►6 µA sleep mode supply current ►64-lead LQFP_EP package
APPLICATIONS
►Backup battery systems ►Grid energy storage ►Residential energy storage ►UPS ►High power portable equipment TYPICAL APPLICATION CIRCUIT Figure 1. Typical Application Circuit acquisition rates can be selected for high noise reduction. current consumption is reduced to 6 µA.
analog.com Rev. B | 2 of 92 S Pin Pulse-Width Modulation for Cell I2C/SPI Master on ADBMS1818 Using S Pin Pulsing Using the S Pin Control 4-Wire Serial Peripheral Interface (SPI) 2-Wire Isolated Interface (isoSPI) Physical Discharge Control During Cell
REVISION HISTORY
9/2023—Rev. A to Rev. B 12/2021—Rev. 0 to Rev. A
analog.com Rev. B | 3 of 92 1/2021—Revision 0: Initial Version
analog.com Rev. B | 4 of 92 Specifications are at TA = 25°C, unless otherwise noted. The test conditions are V+ = 59.4 V and VREG = 5.0 V, unless otherwise noted. The ISOMD pin is tied to the V– pin, unless otherwise noted. ADC DC SPECIFICATIONS Table 1. Parameter Test Conditions/Comments Min Typ Max Unit Measurement Resolution 0.1 mV/Bit ADC Offset Voltage1 0.1 mV ADC Gain Error 1 0.01 % TME in Normal Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±0.2 mV C(n) to C(n–1) = 2.0 ±2.6 mV C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature range ±2.8 mV C(n) to C(n–1) = 3.3 ±3.0 mV C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature range ±4.0 mV C(n) to C(n–1) = 4.2 ±3.8 mV C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature range ±4.8 mV C(n) to C(n–1), GPIO(n) to V– = 5.0 ±1 mV Sum of all cells, apply over the full specified temperature range ±0.05 ±0.35 % Internal temperature, T = maximum specified temperature ±5 °C VREG pin, apply over the full specified temperature range –1 –0.15 0 % VREF2 pin, apply over the full specified temperature range –0.05 0.05 0.20 % Digital supply voltage, VREGD, apply over the full specified temperature range–0.5 0.5 1.5 % TME in Filtered Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±0.1 mV C(n) to C(n–1) = 2.0 ±1.6 mV C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature range ±1.8 mV C(n) to C(n–1) = 3.3 ±2.2 mV C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature range ±3.0 mV C(n) to C(n–1) = 4.2 ±2.8 mV C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature range ±3.8 mV C(n) to C(n–1), GPIO(n) to V– = 5.0 ±1 mV Sum of all cells, apply over the full specified temperature range ±0.05 ±0.35 % Internal temperature, T = maximum specified temperature ±5 °C VREG pin, apply over the full specified temperature range –1 –0.15 0 % VREF2 pin, apply over the full specified temperature range –0.05 0.05 0.20 % Digital supply voltage, VREGD, apply over the full specified temperature range–0.5 0.8 1.5 % TME in Fast Mode C(n) to C(n–1), GPIO(n) to V– = 0 ±2 mV C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature range ±6.5 mV C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature range ±8.5 mV C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature range ±12.5 mV C(n) to C(n–1), GPIO(n) to V– = 5.0 ±10 mV Sum of all cells, apply over the full specified temperature range ±0.15 ±0.5 % Internal temperature, T = maximum specified temperature ±5 °C VREG pin, apply over the full specified temperature range –1.5 –0.15 1 %
Table 1. (Continued) 1 The ADC specifications are guaranteed by the TME specification.
Table 3. (Continued)
communications on the isoSPI ports with 50% data 1s and 50% data 0s. Slower clock rates reduce the supply current.
analog.com Rev. B | 8 of 92 SPI DC SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPI Pin Digital Input Voltage High (VIH(SPI)) CSB, SCK, and SDI pins, apply over the full specified temperature range 2.3 V SPI Pin Digital Input Voltage Low （VIL(SPI)) CSB, SCK, and SDI pins, apply over the full specified temperature range 0.8 V Configuration Pin Digital Input Voltage High (VIH(CFG)) ISOMD, DTEN, and GPIO1 to GPIO9 pins, apply over the full specified temperature range 2.7 V Configuration Pin Digital Input Voltage Low (VIL(CFG)) ISOMD, DTEN, and GPIO1 to GPIO9 pins, apply over the full specified temperature range 1.2 V Digital Input Current (ILEAK(DIG)) CSB, SCK, SDI, ISOMD, and DTEN pins, apply over the full specified temperature range ±1 μA Digital Output Low (VOL(SDO)) SDO pin sinking 1 mA, apply over the full specified temperature range 0.3 V ISOSPI DC SPECIFICATIONS See Figure 78. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit Voltage on IBIAS Pin (VBIAS) Ready/active state, apply over the full specified temperature range 1.9 2.0 2.1 V Idle state 0 V Isolated Interface Bias Current (IB) RBIAS = 2 kΩ to 20 kΩ, apply over the full specified temperature range 0.1 1.0 mA Isolated Interface Current Gain (AIB) Transmitter pulse amplitude (VA) = ≤ 1.6 V, IB = 1 mA, apply over the full specified temperature range 18 20 22 mA/mA IB = 0.1 mA, apply over the full specified temperature range18 20 24.5 mA/mA Transmitter Pulse Amplitude (VA) VA = IPx voltage (VIPx) – IMx voltage (VIMx), apply over the full specified temperature range 1.6 V Threshold-Setting Voltage on ICMP Pin (VICMP) Receiver comparator threshold voltage (VTCMP) = receiver comparator threshold voltage gain (ATCMP) × VICMP, apply over the full specified temperature range 0.2 1.5 V Input Leakage Current on ICMP Pin (ILEAK (ICMP)) VICMP = 0 V to VREG, apply over the full specified temperature range ±1 µA Leakage Current on IPx and IMx Pins (ILEAK (IPx/ IMx)) Idle state, VIPx or VIMx, 0 V to VREG, apply over the full specified temperature range ±1 µA Receiver Comparator Threshold Voltage Gain (ATCMP) Receiver common-mode bias (VCM) = VREG/2 to VREG – 0.2 V, VICMP = 0.2 V to 1.5 V, apply over the full specified temperature range 0.4 0.5 0.6 V/V Receiver Common-Mode Bias (VCM) IPx and IMx not driving (VREG – VICMP/3 – 167 mV) V Receiver Input Resistance (RIN) Single-ended to the IPA, IMA, IPB, and IMB pins, apply over the full specified temperature range 26 35 45 kΩ
analog.com Rev. B | 9 of 92 ISOSPI IDLE/WAKE-UP SPECIFICATIONS See Figure 87. Table 7. Parameter Test Conditions/Comments Min Typ Max Unit Differential Wake-Up Voltage (VWAKE) Dwell time at VWAKE before wake detection (tDWELL) = 240 ns, apply over the full specified temperature range 200 mV tDWELL VWAKE = 200 mV, apply over the full specified temperature range 240 ns Start-Up Time After Wake Detection (tREADY) Apply over the full specified temperature range 10 µs Idle Timeout Duration (tIDLE) Apply over the full specified temperature range 4.3 5.5 6.7 ms ISOSPI PULSE TIMING SPECIFICATIONS See Figure 83. Table 8. Parameter Test Conditions/Comments Min Typ Max Unit Chip Select Half Pulse Width (t1/2PW(CS)) Transmitter, apply over the full specified temperature range120 150 180 ns Chip Select Signal Filter (tFILT(CS)) Receiver, apply over the full specified temperature range70 90 110 ns Chip Select Pulse Inversion Delay (tINV(CS)) Transmitter, apply over the full specified temperature range120 155 190 ns Chip Select Valid Pulse Window (tWNDW(CS)) Receiver, apply over the full specified temperature range220 270 330 ns Data Half Pulse Width (t1/2PW(D)) Transmitter, apply over the full specified temperature range40 50 60 ns Data Signal Filter (tFILT(D)) Receiver, apply over the full specified temperature range10 25 35 ns Data Pulse Inversion Delay (tINV(D)) Transmitter, apply over the full specified temperature range40 55 65 ns Data Valid Pulse Window (tWNDW(D)) Receiver, apply over the full specified temperature range70 90 110 ns SPI TIMING REQUIREMENTS See Figure 77 and Figure 86. Table 9. Parameter Test Conditions/Comments Min Typ Max Units SCK Period (tCLK)1 Apply over the full specified temperature range 1 µs SDI Setup Time Before SCK Rising Edge (t1) Apply over the full specified temperature range 25 ns SDI Hold Time After SCK Rising Edge (t2) d Apply over the full specified temperature range 25 ns SCK Low (t3) tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature range 200 ns SCK High (t4) tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature range 200 ns CSB Rising Edge to CSB Falling Edge (t5) Apply over the full specified temperature range 0.65 µs SCK Rising Edge to CSB Rising Edge (t6) 1 Apply over the full specified temperature range 0.8 µs CSB Falling Edge to SCK Rising Edge (t7) 1 Apply over the full specified temperature range 1 µs 1 These timing specifications are dependent on the delay through the cable and include allowances for 50 ns of delay in each direction. 50 ns corresponds to 10 m of Category 5 (CAT-5) cable (which has a velocity of propagation of 66% the speed of light). Using longer cables requires derating these specs by the amount of additional delay.
analog.com Rev. B | 10 of 92 ISOSPI TIMING SPECIFICATIONS See Figure 86. Table 10. Parameter Test Conditions/Comments Min Typ Max Units SCK Falling Edge to SDO Valid (t8)1 Apply over the full specified temperature range 60 ns SCK Rising Edge to Short ±1 Transmit (t9) Apply over the full specified temperature range 50 ns CSB Transition to Long ±1 Transmit (t10) Apply over the full specified temperature range 60 ns CSB Rising Edge to SDO Rising (t11) 1 Apply over the full specified temperature range 200 ns Data Return Delay (tRTN) Apply over the full specified temperature range 325 375 425 ns Chip-Select Daisy-Chain Delay (tDSY(CS)) Apply over the full specified temperature range 120 180 ns Data Daisy-Chain Delay (tDSY(D)) Apply over the full specified temperature range 200 250 300 ns Data Daisy-Chain Lag (vs. Chip Select) (tLAG) = (tDSY(D) + t1/2PW(D)) – (tDSY(CS) + t1/2PW(CS)), apply over the full specified temperature range 0 35 70 ns Chip Select High to Low Pulse Governor (t5(GOV)) Apply over the full specified temperature range 0.6 0.82 µs Data to Chip-Select Pulse Governor (t6(GOV)) Apply over the full specified temperature range 0.8 1.05 µs isoSPI Port Reversal Blocking tBLOCK Window Apply over the full specified temperature range 2 10 µs 1 These specifications do not include rise or fall time of SDO. Although fall time (typically 5 ns due to the internal pull-down transistor) is not a concern, the rising edge transition time (tRISE) is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time requirements of the microcontroller unit (MCU).
ing conditions for extended periods may affect product reliability. Table 12. Thermal Resistance
1 The exposed pad must be connected to the V− plane for proper thermal
2 Board layout impacts thermal characteristics such as θJA. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 13. ADBMS1818, 64-Lead LQFP_EP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 2. Pin Configuration Table 14. Pin Function Descriptions S(n) and C(n–1) for discharging cells. from V– to 5 V. GPIO3, GPIO4, and GPIO5 can be used as I2C or SPI ports. 48 VREG 5 V Regulator Input. Bypass with an external 1 μF capacitor. 49 DRIVE Connect the base of an NPN transistor to the DRIVE pin. Connect the collector to V+ and the emitter to VREG. 50 VREF2 Buffered 2nd Reference Voltage for Driving Multiple 10 kΩ Thermistors. Bypass with an external 1 μF capacitor. 51 VREF1 ADC Reference Voltage. Bypass with an external 1 μF capacitor. No dc loads allowed. 52 DTEN Discharge Timer Enable. Connect DTEN to VREG to enable the discharge timer. open drain NMOS output pin. SDO requires a 5 kΩ pull-up resistor. mode. Connecting ISOMD to V– configures the ADBMS1818 for 4-wire SPI mode. watchdog timer circuit resets the ADBMS1818 and the WDT pin goes high impedance. IB, sourced from the IBIAS pin.
Table 14. Pin Function Descriptions (Continued) threshold of the isoSPI receiver comparators. The comparator thresholds are set to half the voltage on the ICMP pin. 59, 60 V– Negative Supply Pins. The V– pins must be shorted together, external to the IC. 61, 62 IMA, IPA Isolated 2-Wire Serial Interface Port A. IMA (negative) and IPA (positive) are a differential input/output pair. 63, 64 IMB, IPB Isolated 2-Wire Serial Interface Port B. IMB (negative) and IPB (positive) are a differential input/output pair. 65 EPAD (V–) Exposed Pad (V–). The exposed pad must be soldered to the PCB. Table 15. Serial Port Pins
Figure 51. isoSPI Comparator Threshold Gain (Port A and Port B) vs.
Figure 52. Functional Block Diagram
IMPROVEMENTS FROM THE LTC6811-1 analog.com Rev. B | 24 of 92 The ADBMS1818 is an evolution of the LTC6811-1 design. Table 16 summarizes the feature changes and additions in the ADBMS1818. Table 16. Additional ADBMS1818 Features Benefits Relevant Data Sheet Section(s) The ADBMS1818 has 3 ADCs operating simultaneously vs. 2 ADCs on the LTC6811-1. 3 cells can be measured during each conversion cycle.ADC Operation In addition to the 3 ADC Digital filters, there is a 4th filter that is used for redundancy. Checks that all digital filters are free of faults.ADC Conversion with Digital Redundancy for a description and PS, Bits[1:0] in Table 27 Measure Cell 7 with ADC1 and ADC2 simultaneously and then measure Cell 13 with ADC2 and ADC3 simultaneously using the ADOL command. Checks that ADC2 is as accurate as ADC1 and also checks that ADC3 is as accurate as ADC2. Overlap Cell Measurement (ADOL Command) A monitoring feature can be enabled during the discharge timer. Cell balancing can be automatically terminated when cell voltages reach a programmable undervoltage threshold. Improved cell balancing. Discharge Timer Monitor The internal discharge MOSFETs can provide 200 mA of balancing current (80 mA if the die temperature is over 85°C). The balancing current is independent of cell voltage. Faster cell balancing, especially for low cell voltages.Cell Balancing with Internal MOSFETs The C0 pin voltage is allowed to range between 0 V and 1 V without affecting the TME. C0 does not have to connect directly to V–. ADC DC Specifications The mute and unmute commands allow the host to turn off and turn on the discharge pins (S pins) without overwriting register values. Greater control of timing between S pins. Turning off and cell measurements. S Pin Muting Auxiliary measurements have an open-wire diagnostic feature Improved fault detection. Auxiliary Open Wire Check (AXOW Command) Four additional GPIO pins have been added for a total of nine. Increased number of temperature or other sensors that can be measured. Auxiliary (GPIO) Measurements (ADAX Command) and Auxiliary Open Wire Check (AXOW Command) A daisy chain of ADBMS1818s can operate in both directions (both ports can be a master or slave). Redundant communication path. Reversible isoSPI
(see the Watchdog and Discharge Timer section) has timed out. idle state. The DRIVE pin is 0 V. Interface section), the ADBMS1818 enters the standby state. powered by an external supply. disabled, only the watchdog timer is relevant. the sleep state if both timers are expired). The ADBMS1818 performs ADC conversions in the measure state. The reference and ADCs are powered up. either the REFUP or standby state, depending on the REFON bit. REFON = 1 to take advantage of the REFUP state. Note that non ADC commands do not cause a core state transition. Figure 53. ADBMS1818 Operation State Diagram
In the idle state, the isoSPI ports are powered down. In the ready state, the isoSPI port(s) are ready for communication. data, the ADBMS1818 enters the active state. The power consumption varies according to the operational states. Table 17. Core Supply Current Table 18. isoSPI Supply Current Equations
the –3 dB bandwidth of the ADC measurement. because of the optimum combination of speed and accuracy. and average measurement error. also referred to as the filtered mode due to its low –3 dB frequency. and 422 Hz modes is similar to the 7 kHz (normal) mode. have the tREFUP delay before beginning ADC conversions. Table 19. ADC Filter Bandwidth and Accuracy
Table 20. ADC Range and Resolution (Continued) 1 Negative readings are rounded to 0 V. 2 Precision range is the range over which the noise is less than the maximum noise. 3 Noise free resolution is a measure of the noise level within the precision range. Figure 55. Timing for ADCV Command Measuring all 18 Cells Table 21. Conversion and Synchronization Times for ADCV Command Measuring All 18 Cells in Different Modes
422 Hz 0 1890 3770 9408 11,287 12,816 9397
26 Hz 0 29,818 59,624 149,044 178,851 201,325 149,033
Figure 56. Timing for ADCV Command Measuring 3 Cells Table 22 shows the conversion time for the ADCV command measuring only 3 cells. t1C indicates the total conversion time for this command. Table 22. Conversion Times for ADCV Command Measuring 3 Cells in Different Modes
Table 22. Conversion Times for ADCV Command Measuring 3 Cells in Different Modes (Continued)
422 Hz 0 1890 2152
26 Hz 0 29,818 33,570
to undervoltage and overvoltage thresholds stored in the memory. The ADAX command initiates the measurement of the GPIO inputs. Figure 57. Timing for ADAX Command Measuring All GPIOs and 2nd Reference Table 23. Conversion and Synchronization Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
422 Hz 0 1890 3770 16,926 18,805 21,316 16,915
26 Hz 0 29,818 59,624 268,271 298,078 335,498 268,260
set to 0 or 1 during the ADAXD command to enable redundancy. See the ADC Conversion with Digital Redundancy section. in fast mode is within 194 μs. for the command is given by t8C. Figure 58. Timing of ADCVAX Command Table 24. Conversion and Synchronization Times for ADCVAX Command in Different Modes
422 Hz 0 1890 3770 5649 7536 9415 11,302 13,181 15,061 17,104 7525
26 Hz 0 29,818 59,624 89,431 119,245 149,052 178,866 208,672 238,479 268,450 119,234
Measurement section, and Power Supply Measurements section. command measuring all 4 internal device parameters. sion time for the ADSTAT command. Figure 59. Timing for ADSTAT Command Measuring SC, ITMP, VA, and VD Table 25. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, and VD in Different Modes
422 Hz 0 1890 3770 5649 7529 8538 5638
26 Hz 0 29,818 59,624 89,431 119,238 134,211 89,420
supply measurement (VD) is stored in Status Register Group B. dancy. See the ADC Conversion with Digital Redundancy section. redundancy and error checking. range of the ADC and the host identifies this as a fault indication. Table 26. Indication of Digital Redundancy Fault Bit Location the ADBMS1818 automatically selects the ADC path redundancy. by writing to the PS, Bits[1:0] in Configuration Register Group B. Table 27 shows all possible ADC path redundancy selections. of all cells measurements, tSKEW, in fast mode is within 147 μs. for the command is given by t7C.
Table 27. ADC Path Redundancy Selection 2 Note that the ADAX and ADSTAT commands are identical to the ADAXD and ADSTATD commands except that ADAX and ADSTAT do not apply any digital redundancy. Figure 60. Timing of ADCVSC Command Measuring All 19 Cells, SC Table 28. Conversion and Synchronization Times for ADCVSC Command in Different Modes
26 Hz 0 29,818 59,624 89,431 119,245 149,059 178,866 208,672 234,902 89,427
Voltage Register Group E where the Cell 13 result normally resides. Figure 61. Timing for ADOL Command indicates the total conversion time for this command. Table 29. Conversion Times for ADOL Command Table 29. Conversion Times for ADOL Command (Continued)
422 Hz 0 1891 3772 4282
26 Hz 0 29,818 59,626 67,119
groups as the corresponding regular ADC conversion command. in the registers. Table 30 provides a list of the self test commands. Figure 62. Operation of ADBMS1818 ADC Self Test Table 30. Self Test Command Summary
Table 30. Self Test Command Summary (Continued)
verified by comparing it to ADC2 using the ADOL command. on a power-on reset (POR) or after a CLRSTAT command. Group D, are set to 0xFF by the CLRAUX command. are all set to 0xFF by the CLRSTAT command. source current into the two C pins while they are being measured. the current sources are sinking or sourcing 100 μA.
- Run the 18-cell command ADOW with PUP = 1 at least twice.
and store them in array CELLPU(n).
- Run the 18-cell command ADOW with PUP = 0 at least twice.
and store them in array CELLPD(n).
- Take the difference between the pull-up and pull-down meas-
- For all values of n from 1 to 17: If CELL∆(n+1) < –400 mV,
enough difference for the algorithm to detect an open connection. determine how many conversions are necessary. Table 31. Number of ADOW Commands Required current sources are sinking or sourcing 100 μA.
Table 33. Discharge Timer Settings Table 34. Status of the Discharge Timer
0 Disabled (or) timer has timed out
the middle of some commands. Table 33. As a result, the read back data from bytes CFGAR4 result, the read back data may be corrupted. 1 for the PWM feature to operate. all 18 pins to switch (18 × 62.5 ms). Table 35. S Pin Pulse-Width Modulation Settings
Register Group and PWM/S Control Register Group B) are all 1s. in Configuration Register Group B to 1 to enable this feature. either constant discharge or PWM discharge) down to that level. cy failure occurs, all DCC bits are cleared. ADBMS1818 supports SPI Mode 3 (CHPA = 1 and CPOL = 1). groups so these ports are not pulled low internally by the device. ADBMS1818 has a 6-byte COMM register, as shown in Table 36. control actions after transmitting/receiving each data byte. Table 36. COMM Register Memory Map Table 37. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C Master
0001 Stop Generate a stop signal on I2C port
0000 Blank Proceed directly to data transmission on I2C port
0111 No transmit Release SDA and SCL and ignore the rest of the data
1000 Master NACK Master generates a NACK signal on ninth clock cycle
1001 Master NACK + stop Master generates a NACK signal followed by a stop signal
Table 38. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on SPI Master
1010 CSBM falling edge Drives CSBM (GPIO3) high, then low
1001 CSBM high Generates a CSBM high signal on SPI port (GPIO3)
1111 No transmit Releases the SPI port and ignores the rest of the data
1001 CSBM high Transitions CSBM high at the end of byte transmission
slave device: WRCOMM, STCOMM, and RDCOMM. details on a write command format. (SDIOM), and GPIO5 (SCKM) for SPI communication. byte of data transmitted to the slave device while holding CSB low. the STCOMM command and its PEC followed by 72 clock cycles. device is updated in the COMM register. Table 39. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C
0110 Master generated a start signal
0001 Master generated a stop signal
0000 Blank, SDA was held low between bytes
0111 Blank, SDA was held high between bytes
0000 Master generated an ACK signal
0111 Slave generated an ACK signal
1111 Slave generated a NACK signal
0001 Slave generated an ACK signal, master generated a
1001 Slave generated a NACK signal, master generated a
Bits[7:0] contain the data byte transmitted by the SPI slave. Figure 64. ADBMS1818 I2C or SPI Master Using GPIOs out and resets the ports to their default values. signal is only required at the beginning of the entire data stream. and SCL do not reset between different STCOMM commands. not reset between different STCOMM commands. lines are released, and the rest of the data in the word is ignored. and the rest of the data in the word is ignored.
Table 40. I2C Master Timing input, each with a specified minimum of 200 ns. Table 41. SPI Master Timing input, each with a specified minimum of 200 ns. behaviors that can be sent to the LT8584. The S pin pulses occur at a pulse rate of 6.44 kHz (155 μs period). continue to clock SCK in order to poll the status of the pulsing. remains logic low until the S pin pulsing sequence completes. used to determine when the S pin pulsing completes. control settings are cleared. leave the DCC bits set to 0 when using the S pin control settings. diagnostic control loop time in a high reliability application. The following figures show the S pin pulsing behavior. Figure 67. S Pin Behavior when S Pin Control Bits = 0000
Figure 79. Capacitive-Coupled Daisy-Chain Configuration
Figure 80. Transformer-Isolated Daisy-Chain Configuration
are off, the load resistance forces the differential output to 0 V. Table 42. isoSPI Pulse Types pulse. These timing relations are shown in Figure 83. the SPI signals into isoSPI pulses. Figure 83. isoSPI Pulse Detail
Table 43. Port B (Master) isoSPI Port Function command this port can transmit return data pulses. Table 44. Port A (Slave) isoSPI Port Function Table 44. Port A (Slave) isoSPI Port Function (Continued) pulse. The master port recognizes a null response as a Logic 1. isoSPI, communication can be initiated from either Port A or Port B. as a slave or master, depending on the direction of communication.
Figure 84. Reversible isoSPI Daisy Chain
Figure 88. 15-Bit PEC Computation Circuit Table 45. PEC Calculation for 0x0001 Table 46. Write/Read PEC Format
analog.com Rev. B | 59 of 92 While writing any command to ADBMS1818, the command bytes CMD0 and CMD1 (see Table 49 and Table 50) and the PEC bytes PEC0 and PEC1 are sent on Port A in the following order: CMD0, CMD1, PEC0, PEC1 After a write command to daisy-chained ADBMS1818 devices, data is sent to each device followed by the PEC. For example, when writing Configuration Register Group A to two daisy-chained devices (primary device P, stacked device S), the data is sent to the primary device on Port A in the following order: CFGAR0(S), … , CFGAR5(S), PEC0(S), PEC1(S), CFGAR0(P), … , CFGAR5(P), PEC0(P), PEC1(P) After a read command for daisy-chained devices, each device shifts out its data and the PEC that it computed for its data on Port A followed by the data received on Port B. For example, when reading Status Register Group B from two daisy -chained devices (primary device P, stacked device S), the primary device sends out data on Port A in the following order: STBR0(P), … , STBR5(P), PEC0(P), PEC1(P), STBR0(S), … , STBR5(S), PEC0(S), PEC1(S) See the Bus Protocols section for the command format. All devices in a daisy-chained configuration receive the command bytes simultaneously. For example, to initiate ADC conversions in a stack of devices, a single ADCV command is sent, and all devices start conversions at the same time. For read and write commands, a single command is sent, and the stacked devices effectively turn into a cascaded shift register, in which data is shifted through each device to the next higher (on a write) or the next lower (on a read) device in the stack. See the Serial Interface Overview section. Polling Methods The simplest method to determine ADC completion is for the controller to start an ADC conversion and wait for the specified conversion time to pass before reading the results. If using a single ADBMS1818 that communicates in SPI mode (ISOMD pin tied low), there are two methods of polling. The first method is to hold CSB low after an ADC conversion command is sent. After entering a conversion command, the SDO line is driven low when the device is busy performing conversions. SDO is pulled high when the device completes conversions. However, SDO also goes high when CSB goes high even if the device has not completed the conversion (see Figure 89). A problem with this method is that the controller is not free to perform other serial communications while waiting for ADC conversions to complete. The next method overcomes this limitation. The controller can send an ADC start command, perform other tasks, and then send a poll ADC converter status (PLADC) command to determine the status of the ADC conversions (see Figure 90). After entering the PLADC command, SDO goes low if the device is busy performing conver- sions. SDO is pulled high at the end of conversions. However, SDO also goes high when CSB goes high even if the device has not completed the conversion. If using a single ADBMS1818 that communicates in isoSPI mode, the low-side port transmits a data pulse only in response to a master isoSPI pulse received by it. Therefore, after entering the command in either method of polling described previously, isoSPI data pulses are sent to the part to update the conversion status. These pulses can be sent using the LTC6820 by simply clocking its SCK pin. In response to this pulse, the ADBMS1818 sends back a low isoSPI pulse if it is still busy performing conversions or a high data pulse if it has completed the conversions. If a CSB high isoSPI pulse is sent to the device, the device exits the polling command. In a daisy-chained configuration of N stacked devices, the same two polling methods can be used. If the bottom device communi- cates in SPI mode, the SDO of the bottom device indicates the conversion status of the entire stack. That is, SDO remains low until all the devices in the stack have completed the conversions. In the first method of polling, after an ADC conversion command is sent, clock pulses are sent on SCK while keeping CSB low. The SDO status becomes valid only at the end of N clock pulses on SCK. During the first N clock pulses, the bottom ADBMS1818 in the daisy chain outputs a 0 or a low data pulse. After N clock pulses, the output data from the bottom ADBMS1818 gets updated for every clock pulse that follows (see Figure 91). In the second method, the PLADC command is sent followed by clock pulses on SCK while keeping CSB low. Similar to the first method, the SDO status is valid only after N clock cycles on SCK and gets updated after every clock cycle that follows (see Figure 92). If the bottom device communicates in isoSPI mode, isoSPI data pulses are sent to the device to update the conversion status. Using the LTC6820, this action can be achieved by just clocking the SCK pin. The conversion status is valid only after the bottom ADBMS1818 device receives N isoSPI data pulses and the status gets updated for every isoSPI data pulse that follows. The device returns a low data pulse if any of the devices in the stack is busy performing conversions and returns a high data pulse if all the devices are free.
Table 47. Protocol Key Table 47. Protocol Key (Continued) Table 48. Poll Command Table 49. Write Command Table 50. Read Command 16-bit command (CMD0 and CMD1). Table 51. Command Format Table 52 lists all the commands and their options. Table 52. Command Codes
Table 52. Command Codes (Continued)
Table 53. Command Bit Descriptions
0 Discharge Not Permitted
1 Discharge Permitted
0 Pull-down current
1 Pull-up current
01 Self Test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 0x9555 0x9555
10 Self test 2 0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA
000 GPIO1 to
001 GPIO1 and
010 GPIO2 and
011 GPIO3 and
100 GPIO4 and
000 SC, ITMP, VA,
Table 53. Command Bit Descriptions (Continued) 1 Note: Valid options for CHST in ADSTAT command are 0 to 4. If CHST is set to 5/6 in ADSTAT command, the ADBMS1818 ignores the command.
Table 54. Configuration Register Group A Table 55. Configuration Register Group B Table 56. Cell Voltage Register Group A Table 57. Cell Voltage Register Group B Table 58. Cell Voltage Register Group C 1 After performing the ADOL command, CVCR2 and CVCR3 of Cell Voltage Register Group C contain the result of measuring Cell 7 from ADC1. Table 59. Cell Voltage Register Group D
Table 59. Cell Voltage Register Group D (Continued) Table 60. Cell Voltage Register Group E 1 After performing the ADOL command, CVER2 and CVER3 of Cell Voltage Register Group E contain the result of measuring Cell 13 from ADC2. Table 61. Cell Voltage Register Group F Table 62. Auxiliary Register Group A Table 63. Auxiliary Register Group B Table 64. Auxiliary Register Group C
Table 64. Auxiliary Register Group C (Continued) Table 65. Auxiliary Register Group D Table 66. Status Register Group A Table 67. Status Register Group B Table 68. COMM Register Group Table 69. S Control Register Group
Table 70. PWM Register Group Table 71. PWM/S Control Register Group B Table 72. Memory Map Bit Descriptions
Table 72. Memory Map Bit Descriptions (Continued)
1 Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.
measurements are all with respect to V–. Figure 95. Internal ESD Protection Structures of the ADBMS1818
Figure 96. Input Filter Structure Configurations
package, as shown in Figure 99. Figure 99. Internal/External Discharge Circuits used, the resistor in series with the base must be reduced. typical battery imbalance and the allowable time for cell balancing. a 50 mA balancing current, the error can be corrected in 5 hours. data sheet for more details.
Figure 100. 18-Cell Battery Stack Module with Active Balancing
if it was on prior to the measurement command. Table 73. Discharge Control During an ADCV Command with DCP = 0
and read and store the results. ►Step 2: Turn on S1, S7, and S13. ►Step 3: Measure C1 to C0, C7 to C6, and C13 to C12. ►Step 4: Turn off S1, S7, and S13. ►Step 5: Turn on S2, S8, and S14. ►Step 6: Measure C2 to C1, C8 to C7, and C14 to C13. ►Step 7: Turn off S2, S8, and S14. ►Step 17: Turn on S6, S12, and S18. ►Step 18: Measure C6 to C5, C12 to C11, and C18 to C17. ►Step 19: Turn off S6, S12, and S18. results of Step 2 through Step 19. Figure 101. Balancing Self Test Circuit pec15Table[]. This table is used in all future PEC calculations. PEC for byte arrays of any given length.
analog.com Rev. B | 79 of 92 if (remainder & 0x4000) remainder = ((remainder << 1)); remainder = (remainder ^ CRC15_POLY) else remainder = ((remainder << 1)); pec15Table[i] = remainder&0xFFFF; unsigned int16 pec15 (char *data , int len) int16 remainder,address; remainder = 16;//PEC seed for (int i = 0; i < len; i++) address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address remainder = (remainder << 8 ) ^ pec15Table[address]; return (remainder*2);//The CRC15 has a 0 in the LSB so the final value must be multiplied by 2 isoSPI IBIAS and ICMP Setup The ADBMS1818 allows the isoSPI links of each application to be optimized for power consumption or for noise immunity. The power and noise immunity of an isoSPI system is determined by the programmed IB current, which controls the isoSPI signaling currents. IB can range from 100 μA to 1 mA. Internal circuitry scales up this bias current to create the isoSPI signal currents equal to be 20 × IB. A low IB reduces the isoSPI power consumption in the ready and active states, whereas a high IB increases the amplitude of the differential signal voltage VA across the matching termination resistor, RM. The IB current is programmed by the sum of the RB1 and RB2 resistors connected between the 2 V IBIAS pin and GND, as shown in Figure 103. The receiver input threshold is set by the ICMP voltage that is programmed with the resistor divider created by the RB1 and RB2 resistors. The receiver threshold is half of the voltage present on the ICMP pin. The following guidelines must be followed when setting IB (100 μA to 1 mA) and the receiver comparator threshold voltage VICMP/2: R M = Tr ans m i s si o n Li n e C ℎ ar ac t eri s t ic I mp ed anc e Z 0 Signal Amplitude = V A = 20 × I B × R M / 2 Receiver Comparator Threshold (VTCMP) = K × VA Voltage on ICMP Pin (VCIMP) = 2 × VTCMP RB2 = VICMP/IB RB1 = (2/IB) - (RB2) Select IB and K (signal amplitude VA to receiver comparator thresh- old ratio) according to the application: ►For lower power links: IB = 0.5 mA and K = 0.5. ►For full power links: IB = 1 mA and K = 0.5. ►For long links (>50m): IB = 1 mA and K = 0.25. For applications with little system noise, setting IB to 0.5 mA is a good compromise between power consumption and noise immuni- ty. Using this IB setting with a 1:1 transformer and RM = 100 Ω, RB1 must be set to 3.01 k, and RB2 set to 1 kΩ. With a typical CAT5 twisted pair, these settings allow communication up to 50 m. For applications in very noisy environments or that require cables longer than 50 m, it is recommended to increase IB to 1 mA. Higher drive current compensates for the increased insertion loss in the cable and provides high noise immunity. When using cables over 50 m and a transformer with a 1:1 turns ratio and RM = 100 Ω, RB1 is 1.5 k, and RB2 is 499 Ω. The maximum clock rate of an isoSPI link is determined by the length of the isoSPI cable. For cables 10 m or less, the maximum 1 MHz SPI clock frequency is possible. As the length of the cable increases, the maximum possible SPI clock rate decreases. This dependence is a result of the increased propagation delays that can create possible timing violations. Figure 102 shows how the maximum data rate reduces as the cable length increases when using a CAT5 twisted pair. Cable delay affects three timing specifications: tCLK, t6, and t7. In the electrical characteristics table, each of these specifications is derated by 100 ns to allow for 50 ns of cable delay. For longer cables, the minimum timing parameters may be calculated as shown below: tCLK, t6, and t7 > 0.9 μs + 2 × tCABLE (0.2 m per ns)
Figure 105. Daisy Chain Interface Components on Single Board
Figure 106. Capacitive Isolation Coupling for ADBMS1818s on the Same PCB devices and the battery pack. the ICMP pin. Slow rise and fall times cut into the timing margins. device that has an adequate isolation rating for the application. this is not equal to the long-term (permanent) rating of the device.
In most applications, a CMC is also necessary for noise rejection. integrated into the transformer being used. Figure 107. Interfacing an ADBMS1818 with a μC Using an LTC6820 for Isolated SPI Control Table 74. Recommended Transformers
Table 74. Recommended Transformers (Continued) Table 75. Recommended Common-Mode Chokes
- The transformer must be placed as close to the isoSPI cable
- A V– ground plane must not extend under the transformer,
- The isoSPI signal traces must be as direct as possible while
ground plane on an inner layer. to determine the number of bits in a given ADBMS1818 command. synchronizing cell voltage and cell current measurements. Table 76. Daisy Chain Serial Time Equations
Figure 112. Typical Application Circuit
Table 77. Related Devices cell balancing capability of up to 200 mA.
Figure 113. 64-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 114. 64-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]