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Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Embedded Processor ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without no tice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of pro- gramming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages (see Operating Conditions on Page 20) Qualified for Automotive Applications (see Automotive Prod- ucts on Page 62) Programmable on-chip voltage regulator 160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP packages MEMORY Up to 148K bytes of on-chip memory (see Table 1 on Page 3) Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and external memory PERIPHERALS Parallel peripheral interface PPI, supporting ITU-R 656 video data formats 2 dual-channel, full duplex synchronous serial ports, sup- porting eight stereo I2S channels 2 memory-to-memory DMAs 8 peripheral DMAs SPI-compatible port Three 32-bit timer/counters with PWM support Real-time clock and watchdog timer 32-bit core timer Up to 16 general-purpose I/O pins (GPIO) UART with support for IrDA Event handler Debug/JTAG interface On-chip PLL capable of frequency multiplication Figure 1. Function al Block Diagram

Rev. I | Page 2 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533 TABLE OF CONTENTS

REVISION HISTORY

8/13— Rev. H to Rev. I Corrected Conditions value of the V IL specification in Added notes to Table 30 in

ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I | Page 3 of 64 | August 2013 GENERAL DESCRIPTION The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC- like microprocessor instruction set, and single instruction, mul- tiple data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory. Specific perfor- mance and memory configurations are shown in Table 1. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like program- mability, multimedia support, and leading-edge signal processing in one integrated package. PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management—the ability to vary both the volt- age and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, com- pared with just varying the frequency of operation. This translates into longer battery life for portable appliances. SYSTEM INTEGRATION The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are highly integrated system-on-a-chip solutions for the next gener- ation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-pur- pose timers (three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface. PROCESSOR PERIPHERALS The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con- tain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configura- tion as well as excellent overall system performance (see the functional block diagram in Figure 1 on Page 1). The general- purpose peripherals include functions such as UART, timers with PWM (pulse-width modulation) and pulse measurement capability, general-purpose I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. In addition to these general- purpose peripherals, the processors contain high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources; and power management control functions to tailor the performance and power characteristics of the proces- sor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, real-time clock, and timers, are supported by a flexible DMA structure. There is also a separate memory DMA channel dedicated to data transfers between the processor’s various memory spaces, including external SDRAM and asynchronous memory. Multi- ple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activ- ity on all of the on-chip and external peripherals. The processors include an on-chip voltage regulator in support of the processor’s dynamic power management capability. The voltage regulator provides a range of core voltage levels from V DDEXT. The voltage regulator can be bypassed at the user’s discretion. Table 1. Processor Comparison Parallel Peripheral Interface 1 1 1 GPIOs 16 16 16 Memory Configuration L1 Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes L1 Instruction SRAM 16K bytes 32K bytes 64K bytes L1 Data SRAM/Cache 16K bytes 32K bytes 32K bytes L1 Data SRAM 32K bytes L1 Scratchpad 4K bytes 4K bytes 4K bytes L3 Boot ROM 1K bytes 1K bytes 1K bytes Maximum Speed Grade 400 MHz 400 MHz 600 MHz Package Options: CSP_BGA Plastic BGA LQFP 160-Ball 169-Ball 176-Lead 160-Ball 169-Ball 176-Lead 160-Ball 169-Ball 176-Lead

Rev. I | Page 4 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533 BLACKFIN PROCESSOR CORE As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 2 32 multiply, divide primitives, satu- ration and rounding, and sign/exponent detection. The set of video instructions includes byte alignment and packing opera- tions, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). Quad 16-bit operations are possible using the second ALU. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-over- head looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory manage- ment unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3, Figure 4, and Figure 5 on Page 6. The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip mem- ory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high bandwidth data- movement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-Chip) Memory The processors have three blocks of on-chip memory that pro- vide high bandwidth access to the core. The first block is the L1 instruction memory, consisting of up to 80K bytes SRAM, of which 16K bytes can be configured as a four way set-associative cache. This memory is accessed at full processor speed.

tionality. This memory block is accessed at full processor speed. as data SRAM and cannot be configured as cache memory. EPROM, ROM, SRAM, and memory mapped I/O devices. resources are mapped through the flat 32-bit address space. space to on-chip peripherals. Figure 2. Blackfin Processor Core

the general-purpose interrupts of the CEC. table (EVT), and lists their priorities. prioritized general-purpose interrupt inputs of the CEC. and the default mappings into the CEC.

• CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it can also be written to clear (cancel) latched events. This register can be read while in supervisor mode and can only be written while in supervisor mode when the correspond- ing IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – The IMASK regis- ter controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register can be read or written while in supervisor mode. Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.

Table 2. Core Event Controller (CEC)

2 Nonmaskable Interrupt NMI

5 Hardware Error IVHW

6 Core Timer IVTMR

7 General Interrupt 7 IVG7

8 General Interrupt 8 IVG8

9 General Interrupt 9 IVG9

10 General Interrupt 10 IVG10

11 General Interrupt 11 IVG11

12 General Interrupt 12 IVG12

13 General Interrupt 13 IVG13

14 General Interrupt 14 IVG14

15 General Interrupt 15 IVG15

Table 3. System Interrupt Controller (SIC)

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• CEC interrupt pending regi ster (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but can be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3.
• SIC interrupt mask register (SIC_IMASK) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in this register, that peripheral event is unmasked and is processed by the sys- tem when asserted. A cleared bit in this register masks the peripheral event, preventing the processor from servicing the event.
• SIC interrupt status regist er (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event.
• SIC interrupt wakeup enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. See Dynamic Power Management on Page 11. Because multiple interrupt sources can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the proces- sor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general-purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. DMA CONTROLLERS The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA-capable peripherals. Addition- ally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The DMA controller supports both 1-dimensional (1-D) and 2- dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on the fly. Examples of DMA types supported by the DMA controller include:
• A single, linear buffer that stops upon completion
• A circular, autorefreshing buffer that interrupts on each full or fractionally full buffer
• 1-D or 2-D DMA using a li nked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are two pairs of memory DMA channels provided for transfers between the various memories of the processor system. This enables transfers of blocks of data between any of the memo- ries—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. REAL-TIME CLOCK The processor real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the pro- cessor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per sec- ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hour counter, and a 32,768 day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. The two alarms are time of day and a day and time of that day.

enabled and the counter underflows, an interrupt is generated. sleep mode upon generation of any RTC wakeup event. regulator from a powered-down state. to an external noise condition or software error. autobaud detect function for a serial channel. clock or to a count of external signals. clock for generation of operating system periodic interrupts.

• Bidirectional operation – Each SPORT has two sets of inde- pendent transmit and receive pins, enabling eight channels of I2S stereo audio.
• Buffered (8-deep) transmit an d receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.
• Clocking – Each tran smit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most-signifi- cant-bit first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync.
• Companding in hardware – Each SPORT can perform A-law or μ-law companding according to ITU recommen- dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.
• DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory.

Figure 6. External Components for RTC NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Rev. I | Page 10 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533

• Interrupts – Each transmit a nd receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through DMA.
• Multichannel capability – Each SPORT supports 128 chan- nels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. An additional 250 mV of SPORT input hysteresis can be enabled by setting Bit 15 of the PLL_CTL register. When this bit is set, all SPORT input pins have the increased hysteresis. SERIAL PERIPHERAL INTERFACE (SPI) PORT The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have an SPI-compatible port that enables the processor to communi- cate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the proces- sor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are recon- figured general-purpose I/O pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface which sup- ports both master/slave modes and multimaster environments. The baud rate and clock phase/polarities for the SPI port are programmable, and it has an integrated DMA controller, con- figurable to support transmit or receive data streams. The SPI DMA controller can only service unidirectional accesses at any given time. The SPI port clock rate is calculated as: where the 16-bit SPI_BAUD register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. UART PORT The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pro- vide a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-sup- ported, asynchronous transfers of serial data. The UART port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The baud rate, serial data format, error code generation and sta- tus, and interrupts for the UART port are programmable. The UART programmable features include:
• Supporting bit rates ranging from (f SCLK/1,048,576) bits per second to (fSCLK/16) bits per second.
• Supporting data formats from seven bits to 12 bits per frame.
• Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port’s clock rate is calculated as: where the 16-bit UART_Divisor comes from the UART_DLH register (most significant 8 bits) and UART_DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA®) serial infrared physi- cal layer link specification (SIR) protocol. GENERAL-PURPOSE I/O PORT F The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have 16 bidirectional, general-purpose I/O pins on Port F (PF15–0). Each general-purpose I/O pin can be individually controlled by manipulation of the GPIO control, status and interrupt registers:
• GPIO direction control register – Specifies the direction of each individual PFx pin as input or output.
• G P I O c o n t r o l a n d s t a t u s r e g isters – The processor employs a “write one to modify” mechanism that allows any combi- nation of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One register is written in order to set GPIO pin values, one register is writ- ten in order to clear GPIO pin values, one register is written in order to toggle GPIO pin values, and one register is writ- ten in order to specify GPIO pin values. Reading the GPIO status register allows software to interrogate the sense of the GPIO pin.
• GPIO interrupt mask register s – The two GPIO interrupt mask registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear individual GPIO pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO inter- rupt mask register clears bits to disable interrupt function. SPI Clock Rate fSCLK UART Clock Rate fSCLK

ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I | Page 11 of 64 | August 2013 PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be trig- gered by software interrupts.

• GPIO interrupt sensitivity re gisters – The two GPIO inter- rupt sensitivity registers specify whether individual PFx pins are level- or edge-sensitive and specify—if edge-sensi- tive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. PARALLEL PERIPHERAL INTERFACE The processors provide a parallel peripheral interface (PPI) that can connect directly to parallel ADCs and DACs, video encod- ers and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bi-directional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also pro- vided. In ITU-R 656 mode, the PPI provides half-duplex bi- directional transfer of 8- or 10-bit video data. Additionally, on- chip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported. General-Purpose Mode Descriptions The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct sub modes are supported:
• Input mode – Frame syncs and data are inputs into the PPI.
• Frame capture mode – Frame syncs are outputs from the PPI, but data are inputs.
• Output mode – Frame syncs an d data are outputs from the PPI. Input Mode Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_- CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit and 10-bit through 16-bit data, programmable in the PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. ITU-R 656 Mode Descriptions The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applica- tions. Three distinct sub modes are supported:
• A c t i v e v i d e o o n l y m o d e
• Vertical blanking only mode
• Entire field mode Active Video Only Mode Active video only mode is used when only the active video por- tion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_COUNT register). Vertical Blanking Interval Mode In this mode, the PPI only transfers vertical blanking interval (VBI) data. Entire Field Mode In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that can be embedded in horizontal and verti- cal blanking intervals. Data transfer starts immediately after synchronization to Field 1. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core. DYNAMIC POWER MANAGEMENT The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pro- vides four operating modes, each with a different performance/ power profile. In addition, dynamic power management pro- vides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode. Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum per- formance can be achieved. The processor core and all enabled peripherals run at full speed.

access is available to appropriately configured L1 memories. re-enabled before it can transition to the full-on or sleep modes. processor will transition to the active mode. to removing power if the processor state is to be preserved. the power savings can be dramatic. quency (fCCLK) to be dynamically controlled. power savings factor and % power savings calculations. Table 4. Power Settings Table 5. Power Domains

All on-chip peripherals are clocked by the system clock (SCLK).

1. Table 6 illustrates typical system clock ratios.

clock signals from the SCLK signal. changed by means of the CSEL1–0 bits of the PLL_DIV register. Table 7. This programmable core clock capability is useful for fast core frequency modifications.

• Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The flash boot routine located in boot ROM memory space is set up using asynchronous Memory Bank 0. All configuration set- tings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit addressable, or Atmel AT45DB041, AT45DB081, or AT45DB161) – The SPI uses the PF2 output pin to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit addressable EEPROM/flash device is detected, and begins clocking data into the processor at the beginning of L1 instruction memory.
• Boot from SPI serial master – The Blackfin processor oper- ates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. To hold off the host device from transmitting while the boot ROM is busy, the Blackfin processor asserts a GPIO pin, called host wait (HWAIT), to signal the host device not to send any

Figure 9. Frequency Mo dification Methods Table 6. Example System Clock Ratios Table 7. Core Clock Ratios Table 8. Booting Modes

00 Execute from 16-bit external memory (bypass

01 Boot from 8-bit or 16-bit FLASH

10 Boot from serial master connected to SPI

11 Boot from serial slave EEPROM/flash (8-,16-, or 24-

ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I | Page 15 of 64 | August 2013 more bytes until the flag is deasserted. The GPIO pin is chosen by the user and this information is transferred to the Blackfin processor via bits[10:5] of the FLAG header in the LDR image. For each of the boot modes, a 10-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks can be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM. In addition, Bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory. INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of opera- tion, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the proces- sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified program- ming model.
• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and supervisor stack pointers.
• Code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore® Embed- ded Studio and/or VisualDSP++®), evaluation products, emulators, and a wide variety of software add-ins. Integrated Development Environments (IDEs) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. The newest IDE, CrossCore Embedded Studio, is based on the EclipseTM framework. Supporting most Analog Devices proces- sor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/ cces. The other Analog Devices IDE, VisualDSP++, supports proces- sor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite ® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders ®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZ- KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of Cross- Core Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZ- KITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly inte- grate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware pack- ages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed.

Rev. I | Page 16 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533 Board Support Packages for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZ- Extender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZ- Extender product. The link is found in the Product Download area of the product web page. Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/ IP stacks. For more information see the following web pages:

• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add-ins that per- form popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices sup- plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emu- lator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set break- points, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emu- lators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the Engineer-to-Engineer Note “Analog Devices JTAG Emulation Technical Reference” (EE-68) on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION The following publications that describe the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF533 Blackfin Processor Hardware Reference
• Blackfin Processor Programming Reference
• ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Processor Anomaly List RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the "signal chain" entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Application Signal Chains page in the Circuits from the Lab TM site (http://www.analog.com/circuits) provides:
• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection guides and application information
• Reference designs applying be st practice design techniques

definitions are listed in Table 9. stated unless otherwise noted in Table 9. ups or pull-downs as noted in the table. Table 9. Pin Descriptions

Table 9. Pin Descriptions (Continued)

1 Refer to Figure 33 on Page 43 to Figure 44 on Page 44.

Rev. I | Page 20 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533 SPECIFICATIONS Component specifications are subject to change without notice. OPERATING CONDITIONS Parameter Conditions Min Nominal Max Unit VDDINT Internal Supply Voltage1 Nonautomotive 400 MHz and 500 MHz speed grade models 2 2 See Ordering Guide on Page 63. 0.8 1.2 1.45 V VDDINT Internal Supply Voltage1 Nonautomotive 533 MHz speed grade models2 0.8 1.25 1.45 V VDDINT Internal Supply Voltage1 600 MHz speed grade models2 0.8 1.30 1.45 V VDDINT Internal Supply Voltage1 Automotive 400 MHz speed grade models2 0.95 1.2 1.45 V VDDINT Internal Supply Voltage1 Automotive 533 MHz speed grade models2 0.95 1.25 1.45 V VDDEXT External Supply Voltage3 3 When VDDEXT < 2.25 V, on-chip voltage regulation is not supported. Nonautomotive grade models2 1.75 1.8/3.3 3.6 V VDDEXT External Supply Voltage Automotive grade models 2 2.7 3.3 3.6 V VDDRTC Real-Time Clock Power Supply Voltage Nonautomotive grade models2 1.75 1.8/3.3 3.6 V VDDRTC Real-Time Clock Power Supply Voltage Automotive grade models2 2.7 3.3 3.6 V VIH High Level Input Voltage4, 5 4 Applies to all input and bidirectional pins except CLKIN. 5 The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0, RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE1–0). VDDEXT =1.85 V 1.3 V VIH High Level Input Voltage4, 5 VDDEXT =Maximum 2.0 V VIHCLKIN High Level Input Voltage6 6 Applies to CLKIN pin only. VDDEXT =Maximum 2.2 V VIL Low Level Input Voltage7 7 Applies to all input and bidirectional pins. VDDEXT =1.75 V +0.3 V VIL Low Level Input Voltage7 VDDEXT =2.7 V +0.6 V TJ Junction Temperature 160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ T AMBIENT = 0°C to +70°C 0 +95 °C TJ Junction Temperature 160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ T AMBIENT = –40°C to +85°C –40 +105 °C TJ Junction Temperature 160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ T AMBIENT = –40°C to +105°C –40 +125 °C TJ Junction Temperature 169-Ball Plastic Ball Grid Array (PBGA) @ T AMBIENT = –40°C to +105°C –40 +125 °C TJ Junction Temperature 169-Ball Plastic Ball Grid Array (PBGA) @ T AMBIENT = –40°C to +85°C –40 +105 °C TJ Junction Temperature 176-Lead Quad Flatpack (LQFP) @ T AMBIENT = –40°C to +85°C –40 +100 °C

Table 10. Core Clock (CCLK) Requirement s—500 MHz, 533 MHz, and 600 MHz Models 1 Applies to 600 MHz models only. See Ordering Guide on Page 63. 2 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 63. 533 MHz models cannot support internal regulator levels above 1.25 V. 3 Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 63. 500 MHz models cannot support internal regulator levels above 1.20 V. Table 11. Core Clock (CCLK) Requirements—400 MHz Models 1 1 See Ordering Guide on Page 63. 2 See Operating Conditions on Page 20. Table 12. Phase-Locked Loop Operating Conditions Table 13. System Clock (SCLK) Requirements 1 tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.

Rev. I | Page 22 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533

ELECTRICAL CHARACTERISTICS

400 MHz1

1 Applies to all 400 MHz speed grade models. See Ordering Guide on Page 63.

500 MHz/533 MHz/600 MHz2

2 Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 63. Parameter Test Conditions Min Typical Max Min Typical Max Unit VOH High Level Output Voltage3 3 Applies to output and bidirectional pins. VDDEXT = 1.75 V, IOH = –0.5 mA VDDEXT = 2.25 V, IOH = –0.5 mA VDDEXT = 3.0 V, IOH = –0.5 mA 1.5 1.9 2.4 1.5 1.9 2.4 V V V VOL Low Level Output Voltage3 VDDEXT = 1.75 V, IOL = 2.0 mA VDDEXT = 2.25 V/3.0 V, IOL =2 . 0m A 0.2 0.4 0.2 0.4 V V IIH High Level Input Current4 4 Applies to input pins except JTAG inputs. VDDEXT = Max, VIN = VDD Max 10.0 10.0 μA IIHP High Level Input Current JTAG5 VDDEXT = Max, VIN = VDD Max 50.0 50.0 μA IIL

6 Low Level Input

VDDEXT = Max, VIN = 0 V 10.0 10.0 μA IOZH Three-State Leakage Current7 VDDEXT = Max, VIN = VDD Max 10.0 10.0 μA IOZL

6 Three-State

VDDEXT = Max, VIN = 0 V 10.0 10.0 μA CIN Input Capacitance8 fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V 48 9 48 9 pF IDDDEEPSLEEP

10 VDDINT Current in

V DDINT = 1.0 V, fCCLK = 0 MHz, TJ = 25°C, ASF = 0.00 7.5 32.5 mA IDDSLEEP VDDINT Current in Sleep Mode VDDINT = 0.8 V, TJ = 25°C, SCLK = 25 MHz 10 37.5 mA IDD-TYP 11 VDDINT Current V DDINT = 1.14 V, fCCLK = 400 MHz, TJ = 25°C 125 152 mA IDD-TYP 11 VDDINT Current V DDINT = 1.2 V, fCCLK = 500 MHz, TJ = 25°C 190 mA IDD-TYP 11 VDDINT Current V DDINT = 1.2 V, fCCLK = 533 MHz, TJ = 25°C 200 mA IDD-TYP 11 VDDINT Current V DDINT = 1.3 V, fCCLK = 600 MHz, TJ = 25°C 245 mA IDDHIBERNATE

10 V DDEXT Current in

VDDEXT = 3.6 V, CLKIN = 0 MHz, TJ = Max, voltage regulator off (VDDINT = 0 V) 50 100 50 100 A IDDRTC VDDRTC Current V DDRTC = 3.3 V, TJ = 25°C2 0 2 0 A IDDDEEPSLEEP f CCLK = 0 MHz 6 Table 15 16 Table 14 mA IDD-INT VDDINT Current f CCLK > 0 MHz I DDDEEPSLEEP + (Table 17  ASF) IDDDEEPSLEEP + (Table 17  ASF) mA

1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics

DDINT) and frequency (Table 17). 5 Applies to JTAG input pins (TCK, TDI, TMS, TRST). 7 Applies to three-statable pins. 8 Applies to all signal pins. 9 Guaranteed, but not tested. 10See the ADSP-BF533 Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes. 11See Table 16 for the list of IDDINT power vectors covered by various Activity Scaling Factors (ASF). Table 14. Static Current–500 MHz, 533 MHz, and 600 MHz Speed Grade Devices (mA)1 1 Values are guaranteed maximum IDDDEEPSLEEP specifications. 2 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20. Table 15. Static Current–400 MHz Speed Grade Devices (mA) 1 1 Values are guaranteed maximum IDDDEEPSLEEP specifications. 2 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.

Table 16. Activity Scaling Factors 1 See EE-229 for power vector definitions. 2 All ASF values determined using a 10:1 CCLK:SCLK ratio. Table 17. Dynamic Current (mA, with ASF = 1.0) 1 1 The values are not guaranteed as stand-alone maximum specificatio ns, they must be combined with static current per the equations of Electrical Characteristics on Page 22 . 2 Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.

nent damage to the device. These are stress ratings only. Table 18. Absolute Maximum Ratings 1 Applies to 100% transient duty cycle. For other duty cycles see Table 19. fications, the range is VDDEXT  0.2 V. Table 19. Maximum Duty Cycle for Input Transient Voltage 1 1 Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0.

2 The individual values cannot be combined for analysis of a single instance of

3 Duty cycle refers to the percentage of time the signal exceeds the value for the

overshoot or undershoot as a percentage of the period of occurrence. ESD (electrostatic discharge) sensitive device. may occur on devices subjected to high energy ESD. avoid performance degradation or loss of functionality.

Rev. I | Page 26 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533

PACKAGE INFORMATION

The information presented in Figure 10 and Table 20 provides details about the package branding for the Blackfin processors. For a complete listing of product availability, see the Ordering Guide on Page 63. Figure 10. Product Information on Package Table 20. Package Br and Information1 products, contact Analog Devices Inc.

Table 23. Asynchronous Memory Read Cycle Timing 1 Output pins include AMS3–0 , ABE1–0 , ADDR19–1, DATA15–0, AOE , ARE. Figure 13. Asynchronous Memory Read Cycle Timing

2 CYCLES

3 CYCLES

1 CYCLE

Table 24. Asynchronous Memory Write Cycle Timing 1 Output pins include AMS3–0 , ABE1–0 , ADDR19–1, DATA15–0, AOE, AWE. Figure 14. Asynchronous Memory Write Cycle Timing

Table 25. SDRAM Interface Timing 1 1 SDRAM timing for TJ > 105°C is limited to 100 MHz. 2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. 3 Refer to Table 13 on Page 21 for maximum fSCLK at various VDDINT. Figure 15. SDRAM Interface Timing NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Table 26. External Port Bus Request and Grant Cycle Timing Figure 16. External Port Bus Request and Grant Cycle Timing

through Figure 26 on Page 37 describe Serial Port operations. Table 28. Serial Ports—External Clock 1 Referenced to sample edge. 2 For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz). 3 Verified in design but untested. After bein g enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port. Table 29. Serial Ports—Internal Clock 1 Referenced to sample edge.

Table 30. Serial Ports—Enable and Three-State 2 Applicable to multichannel mode only. Figure 25. Enable and Three-State

Table 31. External Late Frame Sync 1 In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE. 2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply. Figure 26. External Late Frame Sync

Table 32. Serial Peripheral Interface (SPI) Port—Master Timing Figure 27. Serial Peripheral Interface (SPI) Port—Master Timing

Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing Figure 28. Serial Peripheral Interface (SPI) Port—Slave Timing

Table 34. General-Purpose I/O Port F Pin Cycle Timing Figure 29. GPIO Cycle Timing

Table 37. JTAG Port Timing RESET, NMI, BMODE1–0, BR, PPI3–0.

44 T C K

TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG , BGH, PPI3–0. Figure 32. JTAG Port Timing

TJ = Junction temperature (°C). JT = From Table 38 through Table 40. and the tables on 23 for the method to calculate PD). TA = ambient temperature (°C). Table 38. Thermal Characteristics for BC-160 Package Table 39. Thermal Characterist ics for ST-176-1 Package Table 40. Thermal Characteristics for B-169 Package

on Page 51 lists the CSP_BGA ball assignment by ball number. Table 41. 160-Ball CSP_BGA Ball Assign ment (Alphabetical by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.

Table 42. 160-Ball CSP_BGA Ball Assign ment (Numerical by Ball Number)

Page 54 lists the PBGA ball assignment by ball number. Table 43. 169-Ball PBGA Ball Assign ment (Alphabetical by Signal)

Table 44. 169-Ball PBGA Ball Assignme nt (Numerical by Ball Number)

lists the LQFP pinout by lead number. Table 45. 176-Lead LQFP Pin Assign ment (Alphabetical by Signal)

163 GND 41 PF10 34 V DDEXT 6

Table 46. 176-Lead LQFP Pin Assignme nt (Numerical by Lead Number)

1 GND 41 GND 81 TX 121 ADDR19 161 AMS0

2 GND 42 GND 82 RX 122 ADDR18 162 ARDY

4 VROUT1 44 GND 84 TRST 124 ADDR16 164 SA10

7 GND 47 PF4 87 TDO 127 ADDR13 167 SRAS

8 GND 48 PF3 88 GND 128 GND 168 V DDINT

9 GND 49 PF2 89 GND 129 GND 169 CLKOUT

10 CLKIN 50 PF1 90 GND 130 GND 170 GND

11 XTAL 51 PF0 91 GND 131 GND 171 V DDEXT

12 V DDEXT 52 V DDINT 9 2 G N D1 3 2 G N D1 7 2 S M S

13 RESET 53 SCK 93 V DDEXT 133 GND 173 SCKE

14 NMI 54 MISO 94 TCK 134 V DDEXT 174 GND

15 GND 55 MOSI 95 BMODE1 135 ADDR12 175 GND

16 RTXO 56 GND 96 BMODE0 136 ADDR11 176 GND

17 RTXI 57 V

18 V DDRTC 58 DT1SEC 98 DATA15 138 ADDR9

19 GND 59 DT1PRI 99 DATA14 139 ADDR8

20 V DDEXT 60 TFS1 100 DATA13 140 ADDR7

21 PPI_CLK 61 TSCLK1 101 DATA12 141 ADDR6

22 PPI0 62 DR1SEC 102 DATA11 142 ADDR5

23 PPI1 63 DR1PRI 103 DATA10 143 V

24 PPI2 64 RFS1 104 DATA9 144 GND

25 V DDINT 65 RSCLK1 105 DATA8 145 V DDEXT

26 PPI3 66 V DDINT 106 GND 146 ADDR4

27 PF15 67 DT0SEC 107 V DDEXT 147 ADDR3

28 PF14 68 DT0PRI 108 DATA7 148 ADDR2

29 PF13 69 TFS0 109 DATA6 149 ADDR1

30 GND 70 GND 110 DATA5 150 ABE1

31 V DDEXT 71 V DDEXT 111 V DDINT 151 ABE0

32 PF12 72 TSCLK0 112 DATA4 152 AWE

33 PF11 73 DR0SEC 113 DATA3 153 ARE

34 PF10 74 DR0PRI 114 DATA2 154 AOE

35 PF9 75 RFS0 115 DATA1 155 GND

36 PF8 76 RSCLK0 116 DATA0 156 V

37 PF7 77 TMR2 117 GND 157 V DDINT

38 PF6 78 TMR1 118 V DDEXT 158 AMS3

39 GND 79 TMR0 119 BG 159 AMS2

40 GND 80 V DDINT 120 BGH 160 AMS1

Figure 64. 176-Lead Low Profile Quad Flat Package [LQFP]

0.08 MAX

Figure 65. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

0.40 NOM

0.25 MIN

Figure 66. 169-Ball Plastic Ball Grid Array [PBGA]

0.20 MAX

0.50 NOM

0.40 MIN

Table 47. BGA Data for Use with Surface-Mount Design

Table 48. Automotive Products 2 xx denotes silicon revision. specification which is the only temperature specification.

ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I | Page 63 of 64 | August 2013 ORDERING GUIDE Model 1 1 Z = RoHS compliant part. Temperature Range2 2 Referenced temperature is ambient temperature. The ambie nt temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ) specification which is the only temperature specification. Speed Grade (Max) Package Description Package Option ADSP-BF531SBB400 –40°C to +85°C 400 MHz 169-Ball PBGA B-169 ADSP-BF531SBBZ400 –40°C to +85°C 400 MHz 169-Ball PBGA B-169 ADSP-BF531SBBC400 –40°C to +85°C 400 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF531SBBCZ400 –40°C to +85°C 400 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF531SBBCZ4RL –40°C to +85°C 400 MHz 160-Ball CSP_BGA, 13" Tape and Reel BC-160-2 ADSP-BF531SBSTZ400 –40°C to +85°C 400 MHz 176-Lead LQFP ST-176-1 ADSP-BF532SBBZ400 –40°C to +85°C 400 MHz 169-Ball PBGA B-169 ADSP-BF532SBBC400 –40°C to +85°C 400 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF532SBBCZ400 –40°C to +85°C 400 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF532SBSTZ400 –40°C to +85°C 400 MHz 176-Lead LQFP ST-176-1 ADSP-BF533SBBZ400 –40°C to +85°C 400 MHz 169-Ball PBGA B-169 ADSP-BF533SBBC400 –40°C to +85°C 400 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SBBCZ400 –40°C to +85°C 400 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SBSTZ400 –40°C to +85°C 400 MHz 176-Lead LQFP ST-176-1 ADSP-BF533SBB500 –40°C to +85°C 500 MHz 169-Ball PBGA B-169 ADSP-BF533SBBZ500 –40°C to +85°C 500 MHz 169-Ball PBGA B-169 ADSP-BF533SBBC500 –40°C to +85°C 500 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SBBCZ500 –40°C to +85°C 500 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SBBC-5V –40°C to +85°C 533 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SBBCZ-5V –40°C to +85°C 533 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SKBC-6V 0°C to +70°C 600 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SKBCZ-6V 0°C to +70°C 600 MHz 160-Ball CSP_BGA BC-160-2 ADSP-BF533SKSTZ-5V 0°C to +70°C 533 MHz 176-Lead LQFP ST-176-1

Rev. I | Page 64 of 64 | August 2013 ADSP-BF531/ADSP-BF532/ADSP-BF533 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03728-0-8/13(I)