ADAV803_17 AD | Alldatasheet

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Audio Codec for Recordable DVD ADAV803 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.

FEATURES

Stereo analog-to-digital converter (ADC) Supports 48 kHz/96 kHz sample rates 102 dB dynamic range Single-ended input Automatic level control Stereo digital-to-analog converter (DAC) Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz sample rates 101 dB dynamic range Single-ended output Asynchronous operation of ADC and DAC Stereo sample rate converter (SRC) Input/output range: 8 kHz to 192 kHz 140 dB dynamic range Digital interfaces Record Playback Auxiliary record Auxiliary playback S/PDIF (IEC 60958) input and output Digital interface receiver (DIR) Digital interface transmitter (DIT) PLL-based audio MCLK generators Generates required DVDR system MCLKs Device control via I2C-compatible serial port 64-lead LQFP package FUNCTIONAL BLOCK DIAGRAM ANALOG-TO-DIGITAL CONVERTER REFERENCE SRC DIGITAL-TO-ANALOG CONVERTER ADAV803 DIT AUX DATA OUTPUT RECORD DATA OUTPUT CONTROL REGISTERS PLL DIGITAL INPUT/OUTPUT SWITCHING MATRIX (DATA PATH) PLAYBACK DATA INPUT AUX DATA INPUT DIR VINL VINR VREF VOUTR FILTD IAUXLRCLK IAUXBCLK IAUXSDATA DIRIN OLRCLK OBCLK OSDATA OAUXLRCLK OAUXBCLK OAUXSDATA DITOUT SDA SCL AD0 AD1 SYSCLK3 SYSCLK2 SYSCLK1 ZEROL/INT ZEROR MCLKI XOUT XIN MCLKO VOUTL 04756-001 ILRCLK IBCLK ISDATA Figure 1.

APPLICATIONS

The ADAV803 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV803 features Analog Devices, Inc. proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC) on a single chip. The ADAV803 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo ADC whose digital output is sent to the record interface. The record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. The playback channel features a high performance stereo DAC with independent digital volume control. The sample rate converter (SRC) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. The SRC input can be selected from playback, auxiliary, DIR, or ADC (record). The SRC output can be applied to the playback DAC, both main and auxiliary record channels, and a DIT. Operation of the ADA V803 is controlled via an I 2C®-compatible serial interface, which allows the programming of individual control register settings. The ADAV803 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with an optional digital interface range of 3.0 V to 3.6 V . The part is housed in a 64-lead LQFP package and is character- ized for operation over the commercial temperature range of −40°C to +85°C.

ADAV803* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

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  • Symbols and Footprints DISCUSSIONS View all ADAV803 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. A | Page 2 of 60 TABLE OF CONTENTS

REVISION HISTORY

7/07—Rev. 0 to Rev. A 7/04—Revision 0: Initial Version

Rev. A | Page 3 of 60 SPECIFICATIONS TEST CONDITIONS Test conditions, unless otherwise noted. Table 1. Test Parameter Condition Supply Voltage Analog 3.3 V Digital 3.3 V Ambient Temperature 25°C Master Clock (MCLKI) 12.288 MHz Measurement Bandwidth 20 Hz to 20 kHz Word Width (All Converters) 24 bits Load Capacitance on Digital Outputs 100 pF ADC Input Frequency 1007.8125 Hz at −1 dBFS DAC Output Frequency 960.9673 Hz at 0 dBFS Digital Input Slave Mode, I2S Justified Format Digital Output Slave Mode, I2S Justified Format ADAV803 SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Comments PGA SECTION Input Impedance 4 kΩ Minimum Gain 0 dB Maximum Gain 24 dB Gain Step 0.5 dB REFERENCE SECTION Absolute Voltage, VREF 1.5 V VREF Temperature Coefficient 80 ppm/°C ADC SECTION Number of Channels 2 Resolution 24 Bits Dynamic Range −60 dB input Unweighted 99 dB fS = 48 kHz 98 dB fS = 96 kHz A-Weighted 98 102 dB fS = 48 kHz 101 dB fS = 96 kHz Total Harmonic Distortion + Noise Input = −1.0 dBFS −88 dB fS = 48 kHz −87 dB fS = 96 kHz Analog Input Input Range (± Full Scale) 1.0 V rms DC Accuracy Gain Error −1.5 −0.8 dB Interchannel Gain Mismatch 0.05 dB Gain Drift 1 mdB/°C Offset −10 mV

Rev. A | Page 4 of 60 Parameter Min Typ Max Unit Comments Crosstalk (EIAJ Method) −110 dB Volume Control Step Size (256 Steps) 0.39 % per step Maximum Volume Attenuation −48 dB Mute Attenuation ∞ dB ADC outputs all zero codes Group Delay fS = 48 kHz 910 μs fS = 96 kHz 460 μs ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS1 Pass-Band Frequency 22 kHz fS = 48 kHz 44 kHz fS = 96 kHz Stop-Band Frequency 26 kHz fS = 48 kHz 52 kHz fS = 96 kHz Stop-Band Attenuation 120 dB fS = 48 kHz 120 dB fS = 96 kHz Pass-Band Ripple ±0.01 dB fS = 48 kHz ±0.01 dB fS = 96 kHz ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS Cutoff Frequency 0.9 Hz fS = 48 kHz SRC SECTION Resolution 24 Bits Sample Rate 8 192 kHz XIN = 27 MHz SRC MCLK 138 × fS- MAX

33 MHz fS-MAX is the greater of the input or

Maximum Sample Rate Ratios Upsampling 1:8 Downsampling 7.75:1 Dynamic Range 140 20 Hz to fS/2, 1 kHz, −60 dBFS input, fIN = 44.1 kHz, fOUT = 48 kHz Total Harmonic Distortion + Noise 120 dB 20 Hz to fS/2, 1 kHz, 0 dBFS input, fIN = 44.1 kHz, fOUT = 48 kHz DAC SECTION Number of Channels 2 Resolution 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input Unweighted 99 dB fS = 48 kHz 98 dB fS = 96 kHz A-Weighted 97 101 dB fS = 48 kHz 100 dB fS = 96 kHz Total Harmonic Distortion + Noise Referenced to 1V rms −91 dB fS = 48 kHz −90 dB fS = 96 kHz Analog Outputs Output Range (± Full Scale) 1.0 V rms Output Resistance 60 Ω Common-Mode Output Voltage 1.5 V DC Accuracy Gain Error −2 −0.8 dB Interchannel Gain Mismatch 0.05 dB Gain Drift 1 mdB/°C DC Offset −30 +30 mV

Rev. A | Page 5 of 60 Parameter Min Typ Max Unit Comments Crosstalk (EIAJ Method) −110 dB Phase Deviation 0.05 Degrees Mute Attenuation −95.625 dB Volume Control Step Size (256 Steps) 0.375 dB Group Delay 48 kHz 630 μs 96 kHz 155 μs 192 kHz 66 μs DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS Pass-Band Frequency 20 kHz fS = 44.1 kHz 22 kHz fS = 48 kHz 42 kHz fS = 96 kHz Stop-Band Frequency 24 kHz fS = 44.1 kHz 26 kHz fS = 48 kHz 60 kHz fS = 96 kHz Stop-Band Attenuation 70 dB fS = 44.1 kHz 70 dB fS = 48 kHz 70 dB fS = 96 kHz Pass-Band Ripple ±0.002 dB fS = 44.1 kHz ±0.002 dB fS = 48 kHz ±0.005 dB fS = 96 kHz PLL SECTION Master Clock Input Frequency 27/54 MHz Generated System Clocks MCLKO 27/54 MHz SYSCLK1 256 768 × fS 256/384/512/768 × 32 kHz/44.1 kHz/48 kHz SYSCLK2 256 768 × fS 256/384/512/768 × 32 kHz/44.1 kHz/48 kHz SYSCLK3 256 512 × fS 256/512 × 32 kHz/44.1 kHz/48 kHz Jitter SYSCLK1 65 ps rms SYSCLK2 75 ps rms SYSCLK3 75 ps rms DIR SECTION Input Sample Frequency 27.2 200 kHz Differential Input Voltage 200 mV DIT SECTION Output Sample Frequency 27.2 200 kHz DIGITAL I/O Input Voltage High, VIH 2.0 DVDD V Input Voltage Low, VIL 0.8 V Input Leakage, IIH @ VIH = 3.3 V 10 μA Input Leakage, IIL @ VIL = 0 V 10 μA Output Voltage High, VOH @ IOH = 0.4 mA 2.4 V Output Voltage Low, VOL @ IOL = −2 mA 0.4 V Input Capacitance 15 pF

Rev. A | Page 6 of 60 Parameter Min Typ Max Unit Comments POWER Supplies Voltage, AVDD 3.0 3.3 3.6 V Voltage, DVDD 3.0 3.3 3.6 V Voltage, ODVDD 3.0 3.3 3.6 V Operating Current All supplies at 3.3 V Analog Current 60 mA Digital Current 38 mA Digital Interface Current 13 mA DIRIN/DIROUT Current 5 mA PLL Current 18 mA Power-Down Current RESET low, no MCLK Analog Current 18 mA Digital Current 2.5 mA Digital Interface Current 700 μA DIRIN/DIROUT Current 3.5 mA PLL Current 900 μA Power Supply Rejection Signal at Analog Supply Pins −70 dB 1 kHz, 300 mV p-p −70 dB 20 kHz, 300 mV p-p 1 Guaranteed by design.

Rev. A | Page 7 of 60 TIMING SPECIFICATIONS Timing specifications are guaranteed over the full temperature and supply range. Table 3. Parameter Symbol Min Typ Max Unit Comments MASTER CLOCK AND RESET MCLKI Frequency fMCLK 12.288 54 MHz XIN Frequency fXIN 27 54 MHz RESET Low tRESET 20 ns I2C PORT SCL Clock Frequency fSCL 400 kHz SCL High tSCLH 0.6 μs SCL Low tSCLL 1.3 μs Start Condition Setup Time tSCS 0.6 μs Relevant for repeated start condition Hold Time tSCH 0.6 μs After this period, the first clock is generated Data Setup Time tDS 100 ns SCL Rise Time tSCR 300 ns SCL Fall Time tSCF 300 ns SDA Rise Time tSDR 300 ns SDA Fall Time tSDF 300 ns Stop Condition Setup Time tSCS 0.6 μs SERIAL PORTS1 Slave Mode xBCLK High tSBH 40 ns xBCLK Low tSBL 40 ns xBCLK Frequency fSBF 64 × fS xLRCLK Setup tSLS 10 ns To xBCLK rising edge xLRCLK Hold tSLH 10 ns From xBCLK rising edge xSDATA Setup tSDS 10 ns To xBCLK rising edge xSDATA Hold tSDH 10 ns From xBCLK rising edge xSDATA Delay tSDD 10 ns From xBCLK falling edge Master Mode xLRCLK Delay tMLD 5 ns From xBCLK falling edge xSDATA Delay tMDD 10 ns From xBCLK falling edge xSDATA Setup tMDS 10 ns From xBCLK rising edge xSDATA Hold tMDH 10 ns From xBCLK rising edge 1 The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name. TEMPERATURE RANGE Table 4. Parameter Min Typ Max Unit Specifications Guaranteed 25 °C Functionality Guaranteed −40 +85 °C Storage −65 +150 °C

Rev. A | Page 8 of 60 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating DVDD to DGND and ODVDD to DGND 0 V to 4.6 V AVDD to AGND 0 V to 4.6 V Digital Inputs DGND − 0.3 V to DVDD + 0.3 V Analog Inputs AGND − 0.3 V to AVDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 2. ADAV803 Pin Configuration Table 6. Pin Function Descriptions 1 VINR I Analog Audio Input, Right Channel. 2 VINL I Analog Audio Input, Left Channel. 4 AVDD Analog Voltage Supply. 5 DIR_LF DIR Phase-Locked Loop (PLL) Filter Pin. 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND. 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD. 8 RESET I Asynchronous Reset Input (Active Low). 10 SDA I/O Data Input/Output of I2C-Compatible Control Interface. 11 SCL I Clock Input of I2C Compatible Control Interface. the INTRPT bit in DAC Control Register 4. 14 ZEROR O Right Channel (Output) Zero Flag. 15 DVDD Digital Voltage Supply. 17 ILRCLK I/O Sampling Clock (LRCLK) of Playback Digital Input Port. 18 IBCLK I/O Serial Clock (BCLK) of Playback Digital Input Port. 19 ISDATA I Data Input of Playback Digital Input Port. 20 OLRCLK I/O Sampling Clock (LRCLK) of Record Digital Output Port. 21 OBCLK I/O Serial Clock (BCLK) of Record Digital Output Port. 22 OSDATA O Data Output of Record Digital Output Port. 23 DIRIN I Input to Digital Input Receiver (S/PDIF). 24 ODVDD Interface Digital Voltage Supply. 25 ODGND Interface Digital Ground. 26 DITOUT O S/PDIF Output from DIT.

Rev. A | Page 10 of 60 Pin No. Mnemonic I/O Description 27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port. 28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Input Port. 31 IAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Input Port. 32 IAUXSDATA I Data Input of Auxiliary Digital Input Port. 33 DGND Digital Ground. 34 DVDD Digital Supply Voltage. 35 MCLKI I External MCLK Input. 36 MCLKO O Oscillator Output. 37 XOUT I Crystal Input. 38 XIN I Crystal or External MCLK Input. 39 SYSCLK3 O System Clock 3 (from PLL2). 40 SYSCLK2 O System Clock 2 (from PLL2). 41 SYSCLK1 O System Clock 1 (from PLL1). 42 DGND Digital Ground. 43 PLL_VDD Supply for PLL Analog Section. This pin should be connected to AVDD. 44 PLL_GND Ground for PLL Analog Section. This pin should be connected to AGND. 45 PLL_LF1 Loop Filter for PLL1. 46 PLL_LF2 Loop Filter for PLL2. 47 ADGND Analog Ground (Mixed Signal). This pin should be connected to AGND. 48 ADVDD Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD. 49 VOUTR O Right Channel Analog Output. 50 NC No Connect. 51 VOUTL O Left Channel Analog Output. 52 NC No Connect. 53 AVDD Analog Voltage Supply. 54 AGND Analog Ground. 55 FILTD Output DAC Reference Decoupling. 56 AGND Analog Ground. 57 VREF Voltage Reference Voltage. 58 AGND Analog Ground. 59 AVDD Analog Voltage Supply. 60 CAPRN ADC Modulator Input Filter Capacitor (Right Channel, Negative). 61 CAPRP ADC Modulator Input Filter Capacitor (Right Channel, Positive). 62 AGND Analog Ground. 63 CAPLP ADC Modulator Input Filter Capacitor (Left Channel, Positive). 64 CAPLN ADC Modulator Input Filter Capacitor (Left Channel, Negative).

Figure 21. ADC Dynamic Range, fS = 96 kHz Figure 22. ADC THD + N, fS = 96 kHz

Rev. A | Page 16 of 60 Automatic Level Control (ALC) The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined. The PGA can be used to amplify the unknown signal, and the ALC reduces the gain until the ADC output is within the preset limits. This results in maximum front end gain. Because the ALC block monitors the output of the ADC, the volume control function should not be used. The ADC volume control scales the results from the ADC, and any distortion caused by the input signal exceeding the input range of the ADC is still present at the output of the ADC, but scaled by a value determined by the volume control register. The ALC block has two functions, attack mode and recovery mode. Recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. These modes are discussed in the following sections. Figure 26 is a flow diagram of the ALC block. When the ALC has been enabled, any changes made to the PGA or ALC settings are ignored. To change the functionality of the ALC, it must first be disabled. The settings can then be changed and the ALC re-enabled. Attack Mode When the absolute value of the ADC output exceeds the level set by the attack threshold bits in ALC Control Register 2, attack mode is initiated. The PGA gain for both channels is reduced by one step (0.5 dB). The ALC then waits for a time determined by the attack timer bits before sampling the ADC output value again. If the ADC output is still above the threshold, the PGA gain is reduced by a further step. This procedure continues until the ADC output is below the limit set by the attack threshold bits. The initial gains of the PGAs are defined by the ADC left PGA gain register and the ADC right PGA gain register, and they can have different values. The ALC subtracts a common gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA gains exceed their initial values. The initial gain setting, therefore, also serves as a maximum value. The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds the set limits. If this bit is a 1, both channels must exceed the threshold before the gain is reduced. This mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. If the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold. No Recovery Mode By default, there is no gain recovery. Once the gain has been reduced, it is not recovered until the ALC is reset, either by toggling the ALCEN bit in ALC Control Register 1 or by writing any value to ALC Control Register 3. The latter option is more efficient because it requires only one write operation to reset the ALC function. No recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. The gain can be reduced but not recovered. Therefore, care should be taken that spurious signals do not interfere with the input signal because these might trigger a gain reduction unnecessarily. Normal Recovery Mode Normal recovery mode allows for the PGA gain to be recovered, provided that the input signal meets certain criteria. First, the ALC must not be in attack mode, that is, the PGA gain has been reduced sufficiently such that the input signal is below the level set by the attack threshold bits. Second, the output result from the ADC must be below the level set by the recovery threshold bits in the ALC control register. If both of these criteria are met, the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC output level is below the recovery threshold at intervals determined by the recovery time bits. If the ADC output level exceeds the recovery threshold while the PGA gain is being restored, the PGA gain value is held and does not continue restoration until the ADC output level is again below the recovery threshold. Once the PGA gain is restored to its original value, it is not changed again unless the ADC output value exceeds the attack threshold and the ALC then enters attack mode. Care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments. Limited Recovery Mode Limited recovery mode offers a compromise between no recov- ery and normal recovery modes. If the output level of the ADC exceeds the attack threshold, attack mode is initiated. When attack mode has reduced the PGA gain to suitable levels, the ALC attempts to recover the gain to its original level. If the ADC output level exceeds the level set by the recovery threshold bits, a counter is incremented (GAINCNTR). This counter is incremented at intervals equal to the recovery time selection, if the ADC has any excursion above the recovery threshold. If the counter reaches its maximum value, determined by the GAINCNTR bits in ALC Control Register 1, the PGA gain is deemed suitable and no further gain recovery is attempted. Whenever the ADC output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.

the ADC modulator should be set to run at ADC MCLK/4. clock for the DAC can reduce the performance of the ADC. Figure 26. ALC Flow Diagram

Figure 50. SPORT Clocking Scheme output port-control register. the serial data port formats.

27 MHz video clock from a 27 MHz crystal connected between

Figure 35. The capacitor values should be specified by the crystal manufacturer. clock can be connected directly to the XIN pin. Figure 51. Serial Data Modes

Figure 54. Reading from the DAC Left Volume Register in I2C frame and the register data is written to that register address.

Table 17. SRC and Clock Control Register Bit Map Table 18. SRC and Clock Control Register Bit Descriptions SRCDIV[1:0] Divides the SRC master clock. 00 = SRC master clock is not divided. 01 = SRC master clock is divided by 1.5. 10 = SRC master clock is divided by 2. 11 = SRC master clock is divided by 3. CLK2DIV[1:0] Clock divider for Internal Clock 2 (ICLK2). CLK1DIV[1:0] Clock divider for Internal Clock 1 (ICLK1). MCLKSEL[1:0] Clock selection for the SRC master clock. 10 = PLL recovered clock (512 × fS). 11 = PLL recovered clock (256 × fS). Table 19. S/PDIF Loopback Control Register Bit Map Table 20. S/PDIF Loopback Control Register Bit Descriptions TxMUX Selects the source for S/PDIF output (DITOUT). 0 = S/PDIF transmitter, normal mode.

Table 21. Playback Port Control Register Bit Map Table 22. Playback Port Control Register Bit Descriptions CLKSRC[1:0] Selects the clock source for generating the ILRCLK and IBCLK. SPMODE[2:0] Selects the serial format of the playback port. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified. Table 23. Auxiliary Input Port Register Bit Map Table 24. Auxiliary Input Port Register Bit Descriptions CLKSRC[1:0] Selects the clock source for generating the IAUXLRCLK and IAUXBCLK. SPMODE[2:0] Selects the serial format of auxiliary input port. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified.

Table 25. Record Port Control Register Bit Map Table 26. Record Port Control Register Bit Descriptions CLKSRC[1:0] Selects the clock source for generating the OLRCLK and OBCLK. 00 = Record port is a slave. WLEN[1:0] Selects the serial output word length. SPMODE[1:0] Selects the serial format of the record port. Table 27. Auxiliary Output Port Register Bit Map Table 28. Auxiliary Output Port Register Bit Descriptions CLKSRC[1:0] Selects the clock source for generating the OAUXLRCLK and OAUXBCLK. 00 = Auxiliary record port is a slave. WLEN[1:0] Selects the serial output word length. SPMODE[1:0] Selects the serial format of the auxiliary record port.

Table 29. Group Delay and Mute Register Bit Map Table 30. Group Delay and Mute Register Bit Descriptions MUTE_SRC Soft-mutes the output of the sample rate converter. GRPDLY[6:0] Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples. Table 31. Receiver Configuration 1 Register Bit Map Table 32. Receiver Configuration 1 Register Bit Descriptions NOCLOCK Selects the source of the receiver clock when the PLL is not locked. 0 = Recovered PLL clock is used. RxCLK[1:0] Determines the oversampling ratio of the recovered receiver clock. 00 = RxCLK is a 128 × fS recovered clock. 01 = RxCLK is a 256 × fS recovered clock. 10 = RxCLK is a 512 × fS recovered clock. AUTO_DEEMPH Automatically de-emphasizes the data from the receiver based on the channel status information. 0 = Automatic de-emphasis is disabled. 1 = Automatic de-emphasis is enabled. ERR[1:0] Defines what action the receiver should take, if the receiver detects a parity or biphase error. 01 = Last valid sample is held. 10 = Invalid sample is replaced with zeros. LOCK[1:0] Defines what action the receiver should take, if the PLL loses lock. 01 = Last valid sample is held. 10 = Zeros are sent out after the last valid sample. 11 = Soft-mute of the last valid audio sample.

Table 33. Receiver Configuration 2 Register Bit Map Table 34. Receiver Configuration 2 Register Bit Descriptions RxMUTE Hard-mutes the audio output for the AES3/S/PDIF receiver. 0 = AES3/S/PDIF receiver is not muted. 1 = AES3/S/PDIF receiver is muted. SP_PLL AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock. 0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL. 1 = Left/right clock from one of the serial ports is the reference clock to the PLL. SP_PLL_SEL[1:0] Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set. 00 = Playback port is selected. 01 = Auxiliary input port is selected. 10 = Record port is selected. 11 = Auxiliary output port is selected. from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit. 0 = AES3/S/PDIF receiver data is sent to the SRC. 1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set. NO_VALIDITY When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC. 0 = AES3/S/PDIF receiver data is sent to the SRC. 1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.

Table 35. Receiver Buffer Configuration Register Bit Map Table 36. Receiver Buffer Configuration Register Bit Descriptions interrupt is enabled only when there is a change in the start (ID) bit. 0 = User bit interrupt is enabled in normal mode. 1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit. 0 = User bits are stored together. 1 = User bits are stored separately. RxBCONF3 Defines the function of RxCSBINT. 0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames. RxBCONF[2:1] Defines the user bit buffer. 01 = Updates the second user bit buffer when the first user bit buffer is full. the PRO bit is not set, formats the user bits according to the IEC60958-3 standard. RxBCONF0 Defines the user bit buffer size, if RxBCONF[2:1] = 01. 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bits with Preamble Z as the start of the buffer. Table 37. Transmitter Control Register Bit Map Table 38. Transmitter Control Register Bit Descriptions TxVALIDITY This bit is used to set or clear the VALIDITY bit in the AES3/S/PDIF transmit stream. 0 = Audio is suitable for digital-to-analog conversion. 1 = Audio is not suitable for digital-to-analog conversion. TxRATIO[2:0] Determines the AES3/S/PDIF transmitter to AES3/S/PDIF receiver ratio. 000 = Transmitter to receiver ratio is 1:1. 001 = Transmitter to receiver ratio is 1:2. 010 = Transmitter to receiver ratio is 1:4. 101 = Transmitter to receiver ratio is 2:1. 110 = Transmitter to receiver ratio is 4:1. TxCLKSEL[1:0] Selects the clock source for the AES3/S/PDIF transmitter. 00 = Internal Clock 1 is the clock source for the transmitter. 01 = Internal Clock 2 is the clock source for the transmitter. 10 = Recovered PLL clock is the clock source for the transmitter. TxENABLE Enables the AES3/S/PDIF transmitter. 0 = AES3/S/PDIF transmitter is disabled. 1 = AES3/S/PDIF transmitter is enabled.

Table 39. Transmitter Buffer Configuration Register Bit Map Table 40. Transmitter Buffer Configuration Register Bit Descriptions IU_Zeros[3:0] Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8. TxBCONF3 Transmitter user bits can be stored in separate buffers or stored together. 0 = User bits are stored together. 1 = User bits are stored separately. TxBCONF[2:1] Configures the transmitter user bit buffer. 00 = Zeros are transmitted for the user bits. 01 = Transmitter user bit buffer size is configured according to TxBCONF0. 10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard. TxBCONF0 Determines the buffer size of the transmitter user bits when TxBCONF[2:1] is 01. 0 = 384 bits with Preamble Z as the start of the buffer. 1 = 768 bits with Preamble Z as the start of the buffer. Table 41. Channel Status Switch Buffer and Transmitter Register Bit Map Table 42. Channel Status Switch Buffer and Transmitter Register Bit Description places the data into the Channel Status B buffer. 0 = Channel status for A and B are separate. 1 = Channel status for A and B are the same. 0 = Copying transmitter channel status is enabled. 1 = Copying transmitter channel status is disabled. TxCSSWITCH Toggle switch for the transmit channel status buffer. 0 = 24-byte Transmitter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F. 1 = 24-byte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F. RxCSSWITCH Toggle switch for the receive channel status buffer. 0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37. 1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.

Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description MSBZeros[7:0] Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Table 45. Transmitter Message Zeros Least Significant Byte Register Bit Map Table 46. Transmitter Message Zeros Least Significant Byte Register Bit Descriptions LSBZeros[7:0] Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09. Table 47. Autobuffer Register Bit Map Table 48. Autobuffer Register Bit Descriptions Zero_Stuff_IU Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format. 0 = No zeros added or subtracted. 1 = Zeros can be added or subtracted between IUs. Auto_UBits Enables the user bits to be autobuffered between the AES3/S/PDIF receiver and transmitter. 0 = User bits are not autobuffered. 1 = User bits are autobuffered. Auto_CSBits Enables the channel status bits to be autobuffered between the AES3/S/PDIF receiver and transmitter. 0 = Channel status bits are not autobuffered. 1 = Channel status bits are autobuffered. IU_Zeros[3:0] Sets the maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8. Table 49. Sample Rate Ratio MSB Register (Read-Only) Bit Map Table 50. Sample Rate Ratio MSB Register (Read-Only) Bit Descriptions SRCRATIO[14:8] Seven most significant bits of the15-bit sample rate ratio.

Table 51. Sample Rate Ratio LSB Register (Read-Only) Bit Map Table 52. Sample Rate Ratio LSB Register (Read-Only) Bit Descriptions SRCRATIO[7:0] Eight least significant bits of the15-bit sample rate ratio. Table 53. Preamble-C MSB Register (Read-Only) Bit Map Table 54. Preamble-C MSB Register (Read-Only) Bit Descriptions standard; otherwise, bits show zeros. Table 55. Preamble-C LSB Register (Read-Only) Bit Map Table 56. Preamble-C LSB Register (Read-Only) Bit Descriptions standard; otherwise, bits show zeros. Table 57. Preamble-D MSB Register (Read-Only) Bit Map Table 58. Preamble-D MSB Register (Read-Only) Bit Descriptions of the 16-bit Preamble-C of Channel B. Table 59. Preamble-D LSB Register (Read-Only) Bit Map Table 60. Preamble-D LSB Register (Read-Only) Bit Descriptions of the 16-bit Preamble-C of Channel B.

Table 61. Receiver Error Register (Read-Only) Bit Map Table 62. Receiver Error Register (Read-Only) Bit Descriptions RxValidity This is the VALIDITY bit in the AES3 received stream. interrupt unless it changes state. unless the data becomes audio or the type of nonaudio data changes. CRCError This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register is read. not generate an interrupt unless it changes state. BiPhase/Parity This bit is set if a biphase or parity error occurred in the AES3/S/PDIF stream. This bit is not cleared until the register is read. generate an interrupt unless it changes state. Table 63. Receiver Error Mask Register Bit Map Table 64. Receiver Error Mask Register Bit Descriptions RxValidity Mask Masks the RxValidity bit from generating an interrupt. 0 = RxValidity bit does not generate an interrupt. 1 = RxValidity bit generates an interrupt. Emphasis Mask Masks the Emphasis bit from generating an interrupt. 0 = Emphasis bit does not generate an interrupt. 1 = Emphasis bit generates an interrupt. NonAudio Mask Masks the NonAudio bit from generating an interrupt. 0 = NonAudio bit does not generate an interrupt. 1 = NonAudio bit generates an interrupt. NonAudio Preamble Mask Masks the NonAudio preamble bit from generating an interrupt. 0 = NonAudio preamble bit does not generate an interrupt. 1 = NonAudio preamble bit generates an interrupt. CRCError Mask Masks the CRCError bit from generating an interrupt. 0 = CRCError bit does not generate an interrupt. 1 = CRCError bit generates an interrupt. NoStream Mask Masks the NoStream bit from generating an interrupt. 0 = NoStream bit does not generate an interrupt. 1 = NoStream bit generates an interrupt. BiPhase/Parity Mask Masks the BiPhase/Parity bit from generating an interrupt. 0 = BiPhase/Parity bit does not generate an interrupt. 1 = BiPhase/Parity bit generates an interrupt. Lock Mask Masks the Lock bit from generating an interrupt. 0 = Lock bit does not generate an interrupt. 1 = Lock bit generates an interrupt.

Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions clipped. This bit is not cleared until the register is read. been clipped. This bit is not cleared until the register is read. MUTE_IND Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data. and does not generate an interrupt until it has changed state. Table 67. Sample Rate Converter Error Mask Register Bit Map Table 68. Sample Rate Converter Error Mask Register Bit Descriptions OVRL Mask Masks the OVRL from generating an interrupt. 0 = OVRL bit does not generate an interrupt. 1 = OVRL bit generates an interrupt. OVRR Mask Masks the OVRR from generating an interrupt. 0 = OVRR bit does not generate an interrupt. 1 = OVRR bit generates an interrupt. Reserved. MUTE_IND MASK Masks the MUTE_IND from generating an interrupt. 0 = MUTE_IND bit does not generate an interrupt. 1 = MUTE_IND bit generates an interrupt.

Table 69. Interrupt Status Register Bit Map Table 70. Interrupt Status Register Bit Descriptions rate converter error register. This bit remains high until the interrupt status register is read. copied from the transmitter CS buffer to the S/PDIF transmit buffer. TxUBINT This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read. until the interrupt status register is read. high until read, but does not generate an interrupt. RxBCONF3 = 1. This bit remains high until the interrupt status register is read. error register. This bit remains high until the interrupt status register is read. Table 71. Interrupt Status Mask Register Bit Map Table 72. Interrupt Status Mask Register Bit Descriptions SRCError Mask Masks the SRCError bit from generating an interrupt. 0 = SRCError bit does not generate an interrupt. 1 = SRCError bit generates an interrupt. TxCSTINT Mask Masks the TxCSTINT bit from generating an interrupt. 0 = TxCSTINT bit does not generate an interrupt. 1 = TxCSTINT bit generates an interrupt. TxUBINT Mask Masks the TxUBINT bit from generating an interrupt. 0 = TxUBINT bit does not generate an interrupt. 1 = TxUBINT bit generates an interrupt. TxCSBINT Mask Masks the TxCSBINT bit from generating an interrupt. 0 = TxCSBINT bit does not generate an interrupt. 1 = TxCSBINT bit generates an interrupt. RxUBINT Mask Masks the RxUBINT bit from generating an interrupt. 0 = RxUBINT bit does not generate an interrupt. 1 = RxUBINT bit generates an interrupt. RxCSBINT Mask Masks the RxCSBINT bit from generating an interrupt. 0 = RxCSBINT bit does not generate an interrupt. 1 = RxCSBINT bit generates an interrupt. RxError Mask Masks the RxError bit from generating an interrupt. 0 = RxError bit does not generate an interrupt. 1 = RxError bit generates an interrupt.

Table 73. Mute and De-Emphasis Register Bit Map Table 74. Mute and De-Emphasis Register Bit Descriptions TxMUTE Mutes the AES3/S/PDIF transmitter. 0 = Transmitter is not muted. SRC_DEEM[1:0] Selects the de-emphasis filter for the input data to the sample rate converter. Table 75. NonAudio Preamble Type Register (Read-Only) Bit Map Table 76. NonAudio Preamble Type Register (Read-Only) Bit Descriptions DTS-CD Preamble This bit is set if the DTS-CD preamble is detected. standard or nonaudio data according to SMPTE337M. Table 77. Receiver Channel Status Buffer Register Bit Map Table 78. Receiver Channel Status Buffer Register Bit Descriptions only if the channel status is not autobuffered between the receiver and transmitter. Table 79. Transmitter Channel Status Buffer Register Bit Map Table 80. Transmitter Channel Status Buffer Register Bit Descriptions disabled when autobuffering between the receiver and transmitter is enabled.

Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions RxUBADDR[7:0] Indirect address pointing to the address location in the receiver user bit buffer. Table 83. Receiver User Bit Buffer Data Register Bit Map Table 84. Receiver User Bit Buffer Data Register Bit Descriptions RxUBDATA[7:0] A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR0[7:0]. This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer. Table 85. Transmitter User Bit Buffer Indirect Address Register Bit Map Table 86. Transmitter User Bit Buffer Indirect Address Register Bit Descriptions TxUBADDR[7:0] Indirect address pointing to the address location in the transmitter user bit buffer. Table 87. Transmitter User Bit Buffer Data Register Bit Map Table 88. Transmitter User Bit Buffer Data Register Bit Descriptions TxUBDATA[7:0] A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0[7:0]. When user bit autobuffering is enabled, this buffer is disabled. Table 89. Q Subcode CRCError Status Register (Read-Only) Bit Map Table 90. Q Subcode CRCError Status Register (Read-Only) Bit Descriptions bit is cleared once the register is read. QSUB This bit is set if a Q subcode has been read into the Q subcode buffer (see Table 91).

Table 91. Q Subcode Buffer Bit Map Table 92. Datapath Control Register 1 Bit Map Table 93. Datapath Control Register 1 Bit Descriptions SRC[1:0] Datapath source select for sample rate converter (SRC). REC[2:0] Datapath source select for record output port. AUXO[2:0] Datapath source select for auxiliary output port.

Table 94. Datapath Control Register 2 Bit Map Table 95. Datapath Control Register 2 Bit Descriptions DAC[2:0] Datapath source select for DAC. DIT[2:0] Datapath source select for DIT. Table 96. DAC Control Register 1 Bit Map Table 97. DAC Control Register 1 Bit Descriptions DR_ALL Hard reset and power-down. 0 = Normal, output pins go to VREF level. 1 = Hard reset and low power, output pins go to AGND. 1 = Reset all except registers. CHSEL[1:0] DAC channel select. POL[1:0] DAC channel polarity.

Table 98. DAC Control Register 2 Bit Map Table 99. DAC Control Register 2 Bit Descriptions DMCLK[1:0] DAC MCLK divider. DFS[1:0] DAC interpolator select. DEEM[1:0] DAC de-emphasis select. Table 100. DAC Control Register 3 Bit Map Table 101. DAC Control Register 3 Bit Descriptions ZFVOL DAC zero flag on mute and zero volume. ZFDATA DAC zero flag on zero data disable. ZFPOL DAC zero flag polarity.

Table 102. DAC Control Register 4 Bit Map Table 103. DAC Control Register 4 Bit Descriptions INTRPT This bit selects the functionality of the ZEROL/INT pin. 0 = Pin functions as a ZEROL flag pin. 1 = Pin functions as an interrupt pin. ZEROSEL[1:0] These bits control the functionality of the ZEROR pin when the ZEROL/INT pin is used as an interrupt. 00 = Pin functions as a ZEROR flag pin. 01 = Pin functions as a ZEROL flag pin. 10 = Pin is asserted when either the left or right channel is zero. 11 = Pin is asserted when both the left and right channels are zero. Table 104. DAC Left Volume Register Bit Map Table 105. DAC Left Volume Register Bit Descriptions DVOLL[7:0] DAC left channel volume control. Table 106. DAC Right Volume Register Bit Map Table 107. DAC Right Volume Register Bit Descriptions DVOLR[7:0] DAC right channel volume control. Table 108. DAC Left Peak Volume Register Bit Map Table 109. DAC Left Peak Volume Register Bit Descriptions DLP[5:0] DAC left channel peak volume detection.

Table 110. DAC Right Peak Volume Register Bit Map Table 111. DAC Right Peak Volume Register Bit Descriptions DRP[5:0] DAC right channel peak volume detection. Table 112. ADC Left Channel PGA Gain Register Bit Map Table 113. ADC Left Channel PGA Gain Register Bit Descriptions AGL[5:0] PGA left channel gain control. Table 114. ADC Right Channel PGA Gain Register Bit Map Table 115. ADC Right Channel PGA Gain Register Bit Descriptions AGR[5:0] PGA right channel gain control.

Table 116. ADC Control Register 1 Bit Map Table 117. ADC Control Register 1 Bit Descriptions HPF High-pass filter enable. ANA_PD ADC analog section power-down. MUTER Mute ADC right channel. MUTEL Mute ADC left channel. Table 118. ADC Control Register 2 Bit Map Table 119. ADC Control Register 2 Bit Descriptions BUF_PD Reference buffer power-down control. MCD[1:0] ADC master clock divider.

Table 120. ADC Left Volume Register Bit Map Table 121. ADC Left Volume Register Bit Descriptions AVOLL[7:0] ADC left channel volume control. Table 122. ADC Right Volume Register Bit Map Table 123. ADC Right Volume Register Bit Descriptions AVOLR[7:0] ADC right channel volume control. Table 124. ADC Left Peak Volume Register Bit Map Table 125. ADC Left Peak Volume Register Bit Descriptions ALP[5:0] ADC left channel peak volume detection. Table 126. ADC Right Peak Volume Register Bit Map Table 127. ADC Right Peak Volume Register Bit Descriptions ARP[5:0] ADC right channel peak volume detection.

Table 128. PLL Control Register 1 Bit Map Table 129. PLL Control Register 1 Bit Descriptions DIRIN_CLK[1:0] Recovered S/PDIF clock sent to SYSCLK3. 00 = SYSCLK3 comes from PLL block. 11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN. MCLKODIV Divide input MCLK by 2 to generate MCLKO. PLLDIV Divide XIN by 2 to generate the PLL master clock. XTLPD Power-down XTAL oscillator. SYSCLK3 Clock output for SYSCLK3.

Table 130. PLL Control Register 2 Bit Map Table 131. PLL Control Register 2 Bit Descriptions FS2_[1:0] Sample rate select for PLL2. SEL2 Oversample ratio select for PLL2. DOUB2 Double-selected sample rate on PLL2. FS[1:0] Sample rate select for PLL1. SEL1 Oversample ratio select for PLL1. DOUB1 Double-selected sample rate on PLL1.

Table 132. Internal Clocking Control Register 1 Bit Map Table 133. Internal Clocking Control Register 1 Bit Descriptions DCLK[2:0] DAC clock source select. ACLK[2:0] ADC clock source select. ICLK2_[1:0] Source selector for internal clock ICLK2. Table 134. Internal Clocking Control Register 2 Bit Map Table 135. Internal Clocking Control Register 2 Bit Descriptions ICLK1_[1:0] Source selector for internal clock ICLK1. PLL2INT[1:0] PLL2 internal selector (see Figure 38). PLL1INT PLL1 internal selector.

Table 136. PLL Clock Source Register Bit Map Table 137. PLL Clock Source Register Bit Descriptions PLL2_Source Selects the clock source for PLL2. PLL1_Source Selects the clock source for PLL1. Table 138. PLL Output Enable Register Bit Map Table 139. PLL Output Enable Register Bit Descriptions DIRINPD This bit powers down the S/PDIF receiver. DIRIN_PIN This bit determines the input levels of the DIRIN pin. 0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements. 1 = DIRIN accepts input signals as defined in the Specifications section. SYSCLK1 Enables the SYSCLK1 output. SYSCLK2 Enables the SYSCLK2 output. SYSCLK3 Enables the SYSCLK3 output.

Table 140. ALC Control Register 1 Bit Map Table 141. ALC Control Register 1 Bit Descriptions FSSEL[1:0] These bits should equal the sample rate of the ADC. GAINCNTR[1:0] These bits determine the limit of the counter used in limited recovery mode. RECMODE[1:0] These bits determine which recovery mode is used by the ALC section. LIMDET These bits limit detect mode. 0 = ALC is used when either channel exceeds the set limit. 1 = ALC is used only when both channels exceed the set limit. ALCEN These bits enable ALC.

Table 142. ALC Control Register 2 Bit Map Table 143. ALC Control Register 2 Bit Descriptions RECTH[1:0] Recovery threshold. ATKTH[1:0] Attack threshold. RECTIME[1:0] Recovery time selection. ATKTIME Attack timer selection. Table 144. ALC Control Register 3 Bit Map Table 145. ALC Control Register 3 Bit Description register gives the gain reduction factor.

place, usually under the ADAV803, to prevent ground loops. placed as close as possible to the supply pins. PLLs or clocks, should not be routed close to the ADC section. electrically quiet is a key factor in ensuring good performance. possible to CAPxN and CAPxP . requirements of the application. can be routed on either side of the PLL clock signal, if required. PLL supply to the analog (AVDD) or digital (DVDD) supply. this section helps to reduce these effects. the control registers to gain significant power savings. Table 146. Typical Power Requirements

Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP] Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips. registered trademarks are the property of their respective owners.