ADAV400

ADAV400 Audio Codec with Embedded SigmaDSP Processor Data Sheet (Rev. A)

Document overview

• Manufacturer or author: Analog Devices
• PDF pages: 36

Technical content

Embedded SigmaDSP Processor ADAV400 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. FEATURES Features SigmaStudio™, a proprietary graphical programming tool for fast development of custom signal flows Fully programmable audio digital signal processing (DSP) for enhanced sound processing Includes various third-party audio algorithms Scalable digital audio delay line I2C control interface Pool of 400 ms @ 48 kHz (200 ms for stereo channel) Operates from 3.3 V (analog), 1.8 V (digital core),

3.3 V (digital interface)

High performance, integrated analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) Features on-chip regulator for single 3.3 V operation 1 stereo analog input (ADC) 80-lead LQFP (14 mm × 14 mm) 4 stereo analog inputs with mux-to-stereo ADC Temperature range: 0°C to 70°C 4 stereo (8-channel) analog outputs (DACs) Dedicated headphone output with integrated amplifier APPLICATIONS Multichannel digital I/O ATV and AV audio applications 8-channel I2S input and output modes TV audio processing 8- and 16-channel TDM input and output modes Set-top box (STB) 2-channel (1 stereo) asynchronous I2S input with integrated sample rate converter (SRC), supporting sample rates from 5 kHz to 50 kHz HTiB General audio enhancement FUNCTIONAL BLOCK DIAGRAM MULTICHANNEL DIGITAL OUTPUTS I2C INTERFACE SRC ASYNCHRONIZE DIGITAL INPUT SYNCHRONIZE MULTICHANNEL DIGITAL INPUT PROGRAMMABLE AUDIO PROCESSOR CORE A–V SYNC DELAY MEMORY PLL VOUT1 VOUT2 AUXL2 AUXR2 ADAV400 DAC ADC HPOUTL HPOUTR DAC AUXL1 AUXR1 LRCLK1 BCLK1 MCLKI MCLKO SCL SDA AD0 SDIN0 SDIN1 SDIN2 SDIN3 BCLK0 LRCLK0 AINL1 AINR1 AINL4 AINR4 SDO0 SYSTEM CLOCKS SDO1 SDO2 SDO3 DAC VOUT3 VOUT4 DAC 05811-001 Figure 1.

Rev. A | Page 2 of 36 TABLE OF CONTENTS Recommended Program/Parameter Loading Procedures.... 20

REVISION HISTORY

7/07—Rev. 0 to Rev. A Change to DAC Outputs (Single-Ended), 1/06—Revision 0: Initial Version

Rev. A | Page 3 of 36 GENERAL DESCRIPTION The ADAV400 is an enhanced audio processor. Integrating high performance analog and digital I/Os with a powerful, audio- specific, programmable core enables designers to differentiate their products through audio performance. The audio processing core is based on Analog Devices SigmaDSP® technology featuring full 28-bit processing (56-bit in double precision mode); a sophisticated, fully programmable dynamics processor; and delay memory. This technology allows the system designer to compensate for real-world limitations of speakers, amplifiers, and listening environments. This compensation results in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression and limiting, and third- party-branded algorithms. The analog I/O integrates Analog Devices proprietary continuous time, multibit, sigma-delta (Σ-Δ) architecture. This integration brings a higher level of performance to systems that are required to meet system branding certification by third-party algorithm providers. The analog inputs feature a 95 dB dynamic range stereo ADC fed from a four-stereo input mux. The four stereo analog outputs are each driven by a 95 dB dynamic range DAC. A dedicated headphone channel is included with integrated amplifiers. The ADAV400 supports multichannel digital inputs and outputs. An integrated SRC on one channel provides the capability to support any input sample rate in the range of 5 kHz to 50 kHz, synchronizing this input to the internal DSP engine. The ADAV400 is supported by a powerful graphical programming tool that includes blocks such as general filters, EQ filters, dynamics processing, mixers, volume, and third-party algorithms for fast development of custom signal flows.

Rev. A | Page 4 of 36 SPECIFICATIONS AVDDn1 = 3.3 V , ODVDD = 3.3 V , DVDD = internal voltage regulator, temperature = 0°C to 70°C, master clock = 12.288 MHz, measurement bandwidth = 20 Hz to 20 kHz, ADC input signal = 1 kHz, DAC output signal = 1 kHz, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE SECTION Absolute Voltage (VREF) 1.5 V VREF Temperature Coefficient 130 ppm/°C ANALOG INPUTS (SINGLE ENDED) Number of Channels 8 Four stereo input channels Full-Scale Analog Input 100 μA rms 2 V rms input with 20 kΩ series resistor DC Offset ±10 mV Relative to VREF ADC SECTION Stereo ADC Resolution 24 Bits Dynamic Range A-Weighted 90 95 dB −60 dB with respect to full-scale analog input Total Harmonic Distortion + Noise −90 dB −3 dB with respect to full-scale analog input Interchannel Gain Mismatch 0.1 dB Left and right channel gain mismatch Crosstalk −78 dB Analog channel crosstalk (AINYm2 to AINYm2) One channel = −3 dB, other channel = 0 V Gain Error −6 % Power Supply Rejection −83 dB 1 kHz, 300 mV p-p signal at AVDDn1 ADC DIGITAL DECIMATOR FILTER CHARACTERISTICS @ 48 kHz3 Pass Band 22.5 kHz Pass-Band Ripple ±0.0002 dB Transition Band 24 kHz Stop Band 26.5 kHz Stop-Band Attenuation 100 dB Group Delay 1040 μs DAC OUTPUTS (SINGLE-ENDED) DAC amplifier register contents = 0x0010 Number of Channels 8 Four stereo output channels Resolution 24 Bits Full-Scale Analog Output 1 V rms Dynamic Range A-Weighted 90 95 dB −60 dB with respect to full-scale code input Total Harmonic Distortion + Noise4 −93 dB −3 dB with respect to full-scale code input Crosstalk −100 dB Analog channel crosstalk (VOUTm2 to VOUTm2) One channel = −3 dB, other channels = 0 V Gain Error 5 % Interchannel Gain Mismatch 0.1 dB Left and right channel gain mismatch DC Offset 1 mV Relative to VREF Power Supply Rejection −87 dB 1 kHz, 300 mV p-p signal at AVDDn1 DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS @ 48 kHz3 Pass Band 21.769 kHz Pass-Band Ripple ±0.01 dB Transition Band 23.95 kHz Stop Band 26.122 kHz Stop-Band Attenuation 75 dB Group Delay 580 μs

Rev. A | Page 5 of 36 Parameter Min Typ Max Unit Test Conditions/Comments HEADPHONE OUTPUT (SINGLE ENDED) Measured at headphone output with 32 Ω load, headphone amplifier register contents = 0x0001 Number of Channels 2 One stereo channel Resolution 24 Bits Full-Scale Analog Output 1 V rms Dynamic Range A-Weighted 92 dB −60 dBFS with respect to full-scale code input Total Harmonic Distortion + Noise −84 dB −3 dBFS with respect to full-scale code input Gain Error 4 % Interchannel Gain Mismatch 0.5 dB DC Offset −30 mV Relative to VREF Power Supply Rejection −84 dB 1 kHz, 300 mV p-p signal at AVDDn1 PLL SECTION3 Master Clock Input (MCLKI) 64 × fS 512 × fS MHz SRC3 Dynamic Range A-Weighted 115 dB −60 dBFS input (worst-case input, fS = 50 kHz) Total Harmonic Distortion + Noise −113 dB 0 dBFS input (worst-case input, fS = 50 kHz) Sample Rate 5 50 kHz DIGITAL INPUT/OUTPUT Input Voltage High (VIH) 2.0 ODVDD V Input Voltage Low (VIL) 0.8 V Input Leakage (IIH @ VIH = ODVDD) 10 μA Input Leakage (IIL @ VIL = 0 V) −60 μA Output Voltage High (VOH @ IOH = 0.4 mA) 2.4 V Output Voltage Low (VOL @ IOL = −3.2 mA) 0.4 V Input Capacitance 10 pF SUPPLIES Analog Supplies (AVDDn)1 3.15 3.30 3.45 V Digital Supplies (DVDD) 1.6 1.8 2.0 V Interface Supply (ODVDD) 3.15 3.30 3.45 V Supply Current, Normal Mode Analog Current (AVDD1) 90 110 mA Digital and Interface Current 120 135 mA MCLK = 12.288 MHz, ADCs and DACs active, headphone outputs active and driving a 32 Ω load, Power control register = 0xFFFF PLL Current 5 6 mA Supply Current, Power-Down Mode Analog Current 6 8.5 mA RESET low, MCLK = 3.074 MHz, AINx = AGND, DAC and headphone outputs floating Digital and Interface Current 1.5 6 mA PLL Current 5 50 μA 1 The n refers to supply number. 2 The m refers to channel number, and the Y refers to stereo channel identifier: L for left channel or R for right channel. 3 Guaranteed by design. 4 Measured on one DAC with other DACs and ADCs off.

Rev. A | Page 6 of 36 DIGITAL TIMING Table 2. Parameter Min Max Unit Comments MASTER CLOCK AND RESET fMCLKI (MCLKI Frequency) 3.024 24.576 MHz tMCH (MCLKI High) 10 ns tMCL (MCLKI Low) 10 ns tRLPW (RESET Low Pulse Width) 20 ns I2C® PORT fSCL (SCL Clock Frequency) 400 kHz tSCLH (SCL High) 0.6 μs tSCLL (SCL Low) 1.3 μs Start Condition tSCS (Setup Time) 0.6 μs Relevant for repeated start condition tSCH (Hold Time) 0.6 μs The first clock is generated after this period tDS (Data Setup Time) 100 ns tSCR (SCL Rise Time) 300 ns tSCF (SCL Fall Time) 300 ns tSDR (SDA Rise Time) 300 ns tSDF (SDA Fall Time) 300 ns Stop Condition tSCSH (Setup Time) 0.6 μs SERIAL PORTS Slave Mode tSBH (BCLKx High) 40 ns tSBL (BCLKx Low) 40 ns fSBF (BCLKx Frequency) 64 × fS tSLS (LRCLKx Setup) 10 ns To BCLK rising edge tSLH (LRCLKx Hold) 10 ns From BCLK rising edge tSDS (SDINx Setup) 10 ns To BCLK rising edge tSDH (SDINx Hold) 10 ns From BCLK rising edge tSDD (SDOx Delay) 40 ns From BCLK falling edge Master Mode tMLD (LRCLKx Delay) 5 ns From BCLK falling edge tMDD (SDOx Delay) 40 ns From BCLK falling edge tMDS (SDINx Setup) 10 ns From BCLK rising edge tMDH (SDINx Hold) 10 ns From BCLK rising edge

Rev. A | Page 8 of 36 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DVDD to DGND 0 V to 2.2 V ODVDD to DGND 0 V to 4.0 V AVDD to AGND 0 V to 4.0 V AGND to DGND −0.3 V to +0.3 V Digital Inputs DGND − 0.3 V to ODVDD + 0.3 V Analog Inputs AGND − 0.3 V to ADVDD + 0.3 V Reference Voltage Indefinite short circuit to ground ESD CAUTION Soldering (10 sec) 300°C

51 AGND

49 AVDD2

48 DGND

47 DVDD

46 RESET

43 SDO3

42 SDO2

41 DGND

50 PLL_LF

Figure 5. Pin Configuration Table 4. Pin Function Descriptions 1 FILTA O ADC Filter Decoupling Node for the ADC. Decouple this pin to AGND (Pin 3). 2 VREF Voltage Reference. This pin is driven by an internal 1.5 V reference voltage. Decouple this pin to AGND (Pin 3). 3 AGND ADC Ground. Connect this pin to the analog ground plane. 4 AVDD1 Analog Power Supply Pin for the ADC. Connect this pin to 3.3 V and decouple to AGND (Pin 3). Digital Power Supply Pins. Connect these pins to 1.8 V, either directly or by using the on-chip regulator. Address 0x2A (write) and Address 0x2B (read). 16 SDA I/O Serial Data Input/Output for the I2C Control Port. 17 SCL I Serial Clock for the I2C Control Port. 18 TEST0 Test Pin. Connect to ODVDD. 19 TEST1 Test Pin. Connect to ODVDD. 22 to 25 SDIN [0:3] I Serial Data Inputs. BCLK1 and LRCLK1 are used as the timing signals for SDIN0 to SDIN3. with SDIN0 to SDIN3 when one of these input channels is redirected to the SRC. these input channels is redirected to the SRC. 30 VDRIVE Drive for External PNP Transistor. This is used with the on-chip 1.8 V regulator circuit.

Rev. A | Page 10 of 36 Pin No. Mnemonic I/O Description 33 MCLKI I Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate the appropriate internal clock for the DSP core. 34 MCLKO O Audio Clock Output. The MCLKO pin can be programmed to output the internal audio clock. 35 BCLK1 I/O Bit Clock for Serial Data Input/Output. This clock and the LRCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a slave, and outputs when the port is configured as a master. On power up, these pins are set to slave mode to avoid conflicts with external master mode devices. 36 LRCLK1 I/O Left/Right Clock for Serial Data Input/Output. This clock and the BCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. 37, 38, 42, 43 SDO [0:3] 0 Serial Data Outputs. 39, 44, NC These pins should be left unconnected. 46 RESET I Active Low Reset Signal. After RESET the ADAV400 is powered down. 49 AVDD2 Analog Power Supply Pin for the PLL. Connect this pin to 3.3 V and decouple to AGND (Pin 51). 50 PLL_LF PLL Loop Filter. External components are required to allow the PLL to function correctly. See the PLL Block section for details of these components. 51 AGND PLL Ground. Connect this pin to the analog ground plane. 52 AGND Headphone Driver Ground. Connect this pin to the analog ground plane. 53 HPOUTL O Left Headphone Output. Analog output from the headphone amplifiers. 54 HPOUTR O Right Headphone Output. Analog output from the headphone amplifiers. 55 AVDD3 Analog Power Supply Pin for the Headphone Amplifier. Connect this pin to 3.3 V and decouple to AGND (Pin 52). 56 AUXL1 O Auxiliary Analog Output Left 1. 57 AUXR1 O Auxiliary Analog Output Right 1. 58 to 61 VOUT [1:4] O Main Analog Output 1 to Output 4. 62 AUXL2 O Auxiliary Analog Output Left 2. 63 AUXR2 O Auxiliary Analog Output Right 2. 64 TEST2 Test Pin. This pin should be left unconnected. 67 FILTD DAC Filter Decoupling Node. Decouple this pin to AGND (Pin 69). 68 AVDD4 Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 69). 69, 70 AGND DAC Ground. Connect this pin to the analog ground plane. 71 AVDD5 Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 70). 72, 74, 76, 78 AINL [1:4] I Left Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor for 2 V rms input, as shown in Figure 17. 73, 75, 77, 79 AINR [1:4] I Right Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor for 2 V rms input, as shown in Figure 17. 80 IDAC DAC External Bias Resistor. This is an external bias pin for the DAC circuitry. Connect a 20 kΩ resistor between this pin and AGND.

address of the location being written to or read from. details on the I2C write and read formats. and before the start of the next sample period. between the ADAV400 and the system I2C master controller. recognized by a unique address. the AD0 pin of the ADAV400 to Logic Level 0 or Logic Level 1. Table 5. I2C Addresses Figure 20 shows the timing of an I2C write. terminated by a stop condition.

register counter every two bytes until a stop condition occurs. The timing of a single word read operation is shown in Table 8. Note that the first R/W bit is still a 0, indicating a write operation. followed by the chip address byte with the R/W set to 1 (read). increments after the appropriate number of bytes. Table 6. Single Word I2C Write Table 7. Burst Mode I2C Write Table 8. Single Word I2C Read Table 9. Burst Mode I2C Read

of all signal processing functions. Figure 22. Numeric Precision and Clipping Structure is set in the audio core control register. the program RAM of the ADAV400 through the control port.

• Single- and double-precision biquad filters Examples 1000 0000 0000 0000 0000 0000 0000 = −16.0 1110 0000 0000 0000 0000 0000 0000 = −4.0 1111 1000 0000 0000 0000 0000 0000 = −1.0 1111 1110 0000 0000 0000 0000 0000 = −0.25 1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0) 0000 0000 0000 0000 0000 0000 0000 = 0.0 0000 0010 0000 0000 0000 0000 0000 = +0.25 0000 1000 0000 0000 0000 0000 0000 = +1.0 0010 0000 0000 0000 0000 0000 0000 = +4.0 0111 1111 1111 1111 1111 1111 1111 = (+16.0 − 1 LSB)
• Monochannel and multichannel dynamics processors
• Mixers and splitters
• Tone and noise generators
• First-order filters
• Fixed and variable gain
• RMS look-up tables
• Loudness
• Delay
• Stereo enhancement (Phat Stereo™)
• Dynamic bass boost
• Interpolators and decimators The serial port accepts up to 24 bits on the input and is sign- extended to the full 28 bits of the core. This allows internal gains of up to 24 dB without encountering internal clipping. Additional blocks are always in development. Analog Devices also provides proprietary and third-party algorithms for appli- cations such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices for information about licensing these algorithms.

Table 10. Control Port Addresses Table 11. RAM Read/Write Modes 1 To avoid clicks or pops, mute the DSP core first. registers and three RAMs: parameter, program, and target/slew. parameter, program, and target/slew RAMs.

• Direct Read/Write. This method allows direct access to the program and parameter RAMs. It is normally used during a complete new load of the RAMs using burst mode addressing. To avoid clicks or pops in the outputs, it is recommended to set the clear registers bit in the audio core control register to 0.
• Safe Load Write. Up to five safe load registers can be loaded with parameter RAM address data. The data is transferred to the requested address when the RAM is idle. It is recommended to use this method for dynamic updates during run time. For example, a complete update of one biquad section can occur in one audio frame. This method is not available for writing to the program RAM or control registers. The following sections discuss these two options in more detail.

several mechanisms for disabling the core.

1. Assert Bit 9 (low to assert—default setting) and Bit 6 (high
2. Fill the program RAM using burst mode writes.
3. Fill the parameter RAM using burst mode writes.
4. Assert Bit 7 of the audio core control register to initiate a
5. Deassert Bit 9 and Bit 6 of the audio core control register to
6. Assert Bit 12 of the audio core control register. This begins

control register, or simply wait for a given amount of time).

1. Assert Bit 9 (low to assert) and Bit 6 (high to assert) of the

the serial output registers, and the serial input registers.

1. Fill the program RAM using burst mode writes.
2. Fill the parameter RAM using burst mode writes.
3. Assert Bit 7 of the audio core control register to initiate a
4. Deassert Bit 9 and Bit 6 of the audio core control register.
5. If the newly loaded program also uses the target/slew RAM,

target. The value is updated once per audio frame (LRCLK period). contain 16 bits in 2.14 format and 12 bits to set the current step. Table 12. Table 13 shows the data write format for the constant time ramping. their original premuted states. Table 12. Linear, Constant dB, and RC Ramp Data Write Table 13. Constant Time Ramp Data Write

• Linear. The value slews to the target value using a fixed step size.
• Constant dB. The value slews to the target value using the current value to calculate the step size. The resulting curve has a constant rise and decay when measured in decibels.
• RC. The value slews to the target value using the difference between the target and current values to calculate the step size, resulting in a simple RC response.
• Constant Time. The value slews to the target value in a fixed number of steps in a linear fashion. The control port mute has no effect on this type of ramping curve.

01 Constant dB

11 Constant time

The result of the equation is normalized to a 5.23 data format. the fastest, and 0xF being the slowest).

• Ramp type (two bits).
• Time constant (four bits).
• 0000 = fastest 1111 = slowest
• Data (28 bits): 5.23 format. Ramp Type 4—Constant Time (34-Bit Write) The target word for the constant time ramp type is written in five parts, with the 34-bit command written with six leading 0s to extend the data write to five bytes. The parts of the constant time target RAM write are 0• Ramp type (two bits).
• Update step (one bit). Set to 1 when a new target is loaded to trigger a step value update. The value is automatically reset after the step value is updated.

Figure 23. Slew RAM—Linear Update Increasing Ramp

• Number of steps (three bits). The number of steps needed to slew to the target value is set by these three bits, with the number of steps equal to 2 3-bit setting + 6. 000 = 64 001 = 128 010 = 256 011 = 512 100 = 1024 101 = 2048 110 = 4096 111 = 8196
• Data (16 bits): 2.14 format. 0
• Reserved (12 bits). When writing to the RAM, set all of these bits to 0.

Figure 24. Slew RAM—Linear Update Decreasing Ramp

Rev. A | Page 23 of 36 –1.0 –0.8 –0.6 –0.4 –0.2 0.2 0.4 0.6 0.8 1.0 TIME (ms) OUTPUT LEVEL (V) 05811-030 3525155 20100 The ADAV400 data capture feature allows the data at any node in the signal processing flow to be sent to one of six registers that can be read by the control port or to a serial output pin. Use this feature to monitor and display information about internal signal levels or compressor/limiter activity. The ADAV400 contains six independent data capture registers that can be read via the I2C control port and can be used for monitoring static signals. In addition, two I2S digital output capture registers are available for monitoring dynamic signals. For each of the data capture registers, a capture count and a register select must be set. The capture count is a number between 0 and 2559 that corresponds to the program step number where the capture will occur (see Table 15). Figure 30. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale SAFE LOAD REGISTERS Table 15. Data Capture Control Registers Many applications require real-time control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. Register Bits Function 13:2 12-bit program counter address 1:0 Register select 00 = Mult_X_input For example, if we consider a biquad to prevent instability from occurring, all five parameters of a biquad filter must be updated at the same time. Otherwise, the filter may execute with a mix of old and new coefficients for one or two audio frames. To eliminate this problem, the ADAV400 uses the safe load registers; there are five registers for the 28-bit parameter data and five for the parameter addresses. These addresses will indirectly address either the parameter RAM or the target/slew RAM. 01 = Mult_Y_input 10 = MAC_output 11 = Accum_fback The register select field selects which one of four registers within the DSP core will be transferred to the data capture register when the program counter equals the capture count. The capture count and register select bits are set by writing to one of the eight data capture registers at the following register addresses: Once these registers are loaded, the appropriate initiate safe transfer bit (there are separate bits for parameter and target/slew loads) in the audio core control register should be set.

• 4170: Control Port Data Capture Setup Register 0 The last five instructions of the program RAM are used for the safe load process, so the program length should be limited to 2555 cycles (2560 − 5). It is guaranteed that the safe load occurs within one LRCLK period (21 μs at f S = 48 kHz) of the initiate safe transfer bit being set. Safe load only updates those safe load registers that have been loaded with new data since the last safe load operation. For example, if only two parameters or target RAM locations are to be updated, it is only necessary to load two of the safe load registers; the other safe load registers are ignored because they contain old data.
• 4171: Control Port Data Capture Setup Register 1
• 4172: Control Port Data Capture Setup Register 2
• 4173: Control Port Data Capture Setup Register 3
• 4174: Control Port Data Capture Setup Register 4
• 4175: Control Port Data Capture Setup Register 5
• 4176: Digital Out Data Capture Setup Register 0
• 4177: Digital Out Data Capture Setup Register 1 The captured data is in 5.19 twos complement data format for all eight register select fields. The four LSBs are truncated from the internal 5.23 data-word. DATA CAPTURE REGISTERS Data capture registers are used for debugging user-programmed blocks and are not required when using pre-existing library blocks. The formats for writing and reading to the data capture registers are listed in Table 22 and Table 23.

Burst mode is used to fill contiguous register or RAM locations. boundaries of the different RAMs and registers locations. Table 16. Parameter RAM Read/Write Format (Single Address) Table 17. Parameter RAM Block Read/Write Format (Burst Mode) Table 18. Program RAM Read/Write Format (Single Address) Table 19. Program RAM Block Read/Write Format (Burst Mode) Table 20. Control Register Read/Write Format (16-Bit Register) Table 21. Control Register Read/Write Format (8-Bit Register) Table 22. Data Capture Register Write Format

Table 23. Data Capture (Control Port Readback) Register Read Format Table 24. Safe Load Register Data Write Format Table 25. Safe Load Register Address Write Format

Slot 15 (16-channel TDM) are in the second half of the frame. to left-justified is not a valid state. which are outlined in Table 26. There are two modes of operation. input for the TDM stream and SDO0 is the output. description of the modes of operation. redirected to the serial input and output ports. Table 26. Serial Output Port Master/Slave Mode Capabilities Table 27. Data Format Configurations

Figure 31. I2S Mode—16 to 24 Bits per Channel Figure 32. Left-Justified Mode—16 to 24 Bits per Channel Figure 33. Right-Justified Mode—16 to 24 Bits per Channel

32 BCLKs

256 BCLKs

Figure 34. 8-Channel TDM Mode with Clock Figure 35. TDM Mode with Pulse Word Clock

Table 28. Audio Register Map Table 29. Audio Core Control Register

15 Reserved (set to 0)

141 Enable SDO2 and SDO3

13 Indicates when slew RAM is muted (read only)

12 Equivalent to writing 0s to the target RAM

11 Reserved (set to 0)

10 Reserved (set to 0)

9 Clears internal processor registers (active low)

8 Forces multiplier input to 0

7 Initializes data RAM to 0

6 Mutes serial input ports

5 Initiates safe load-to-target/slew RAM

4 Initiates safe load-to-parameter RAM

1 The polarity of this bit is inverted when read.

Table 30. RAM Modulo Control Register (Eight Bits) Table 31. Serial Output Control Register

15 Dither enable

14 TDM output mode

13 LRCLK polarity

12 BCLK polarity

11 Master/slave mode select

6 Frame sync type

5 TDM enable

Table 32. Serial Input Control Register (Eight Bits)

5 TDM input mode

4 LRCLK polarity

3 BCLK polarity

Table 33. SRC Serial Port Control Register (Eight Bits)

7 Reserved (set to 0)

Table 34. ADC Input Mux Control Register

3 AIN4 to ADC

2 AIN3 to ADC

1 AIN2 to ADC

0 AIN1 to ADC

Table 35. Power Control Register

15 PLL

14 Reference buffer

13 ADC

12 VOUT4 DAC

11 VOUT3 DAC

10 VOUT2 DAC

9 VOUT1 DAC

8 AUX2 right DAC

7 AUX2 left DAC

6 AUX1/HP right DAC

5 AUX1/HP left DAC

4 Headphone amplifier right

3 Headphone amplifier left

2 SRC

1 Digital ADC and DAC engine

0 Audio processor

1 0 = powered down, 1 = powered up. Table 36. User Control Register 2

7 Headphone amplifier mute

Table 37. User Control Register 1

8 SRC mux enable

7 SRC lock indicator (read only)

6 MCLKO pin enable

0 PLL enable

Table 38. DAC Amplifier Register

4 DAC amplifier chopping1

1 Set this bit to 1 to obtain maximum performance from the DAC amplifier. Table 39. Headphone Amplifier Register

0 Headphone amplifier chopping1

1 Set this bit to 1 to obtain maximum performance from the DAC amplifier.

Rev. A | Page 31 of 36 AUDIO CORE CONTROL REGISTER The bits in this register control the operation of the DSP core of the ADAV400 (see Table 29). Enable SDO2 and SDO3 (Bit 14) This bit is set to 1 by default and can be used to disable SDO2 and SDO3 if required. Slew RAM Muted (Bit 13) This bit is set to 1 when the slew RAM mute operation has been completed. This bit is read only and is automatically cleared by reading. Write 0 to Target RAM (Bit 12) Setting this bit to 1 is equivalent to writing 0s to all locations in the target RAM. This effectively mutes any slew RAMs, such as volume controls used in a signal flow. To enable normal operation, clear this bit to 0. Clear Registers to All 0s (Bit 9) Setting this bit to 0 sets the contents of the accumulators and serial output registers to 0. This bit defaults to 0; therefore, the ADAV400 powers up in clear mode and does not pass signals until a 1 is written to this bit. This is intended to prevent noises from inadvertently occurring during the power-up sequence. Force Multiplier to 0 (Bit 8) When this bit is set to 1, the input to the DSP multiplier is set to 0, which results in the multiplier output being 0. This control bit is included for maximum flexibility and is normally not used. Initialize Data Memory with 0s (Bit 7) Setting this bit to 1 initializes all data memory locations to 0. This bit is cleared to 0 after the operation is complete. Assert this bit after a complete program/parameter download has occurred to ensure click-free operation. Zero Serial Input Port (Bit 6) When this bit is set to 1, all input channels to the DSP core are forced to all 0s, effectively muting the output. Initiate Safe Transfer to Target RAM (Bit 5) Setting this bit to 1 initiates a safe load transfer to the target/slew RAM. This bit clears when the operation is complete. Of five safe load register pairs (address/data), only those registers that have been written since the last safe load event occurred are transferred. Address 0 corresponds to the first target RAM location. Initiate Safe Transfer to Parameter RAM (Bit 4) Setting this bit to 1 initiates a safe load transfer to the parameter RAM. This bit clears when the operation is complete. Of five safe load registers pairs (address/data), only those registers that have been written since the last safe load event occurred are transferred. Address 0 corresponds to the first parameter RAM location. Program Length (Bits [1:0]) 96 kHz and 192 kHz Modes These bits set the length of the internal program. The default program length is 2560 instructions for fS = 48 kHz, but the program length can be shortened by factors of 2 to accommodate sample rates higher than 48 kHz. For f S = 96 kHz, set the program length to 1280 (01), and for fS = 192 kHz, set the length to 640 steps (10). Note that this is only valid for digital inputs and outputs.

Figure 37. Typical Application Circuit

Figure 38. 80-Lead Low Profile Quad Flat Package [LQFP]

Rev. A | Page 36 of 36 NOTES ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05811-0-7/07(A)