ADAU1797BCBZRL

ADAU1797 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 86

Technical content

High-Performance Audio Codec with Integrated HiFi 3z and FastDSP Cores Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT

FEATURES

 FastDSP™ audio processing engine  Low latency at sample rates up to 768kHz  Supports up to 128 instructions  Tensilica® HiFi 3z DSP with TIE accelerators  Quad MAC/cycle and 1024kB total memory  2-way SIMD IEEE floating point multiplier  Supports both 50MHz and 200MHz modes  5μs group delay (analog input to amp output)  768kHz sample rate (FastDSP bypass mode)  Three low power 24-bit ADC record channels  104dB SNR, -91dB THD+N, 0.6mW (PGA on)  Flexible differential or single-ended inputs  Ten digital microphone (DMIC) input channels  Two clock outputs (384kHz to 6.144MHz)  Mono low power 24-bit DAC playback channel  113dB SNR, -93dB THD+N, 1.4mW PQ  High-efficiency, low-noise, Class-D amplifier  Two high-performance PDM output channels  Supports 3.072MHz or 6.144MHz clock rates  Two 32-bit I2S/TDM serial audio data ports  Sync clock frequencies from 8kHz to 768kHz  Two full-duplex, 4-channel ASRCs  Supports low power, single-supply mode (1.8V)  Integrated LDO or switch-cap regulator  Digital I/O supports 1.2V or 1.8V logic levels  Digital Control and Communication interfaces  I2C/SPI control and I3C combined interfaces  Master QSPI, UART, and JTAG interfaces  Supports self-boot from QSPI Flash/EEPROM  Multi-purpose I/O pins for GPIO / IRQ support

APPLICATIONS

 True wireless stereo (TWS) ANC headphones  Over-ear stereo ANC headphones  VR and AR headsets and wearable devices  Hearing assist and PSAP devices  Soundbar and smart speaker systems  Gaming devices and tablets GENERAL DESCRIPTION The device is a low power, high -performance audio codec that provides three analog input channels, ten DMIC input channels, two PDM output channels, and one high-efficiency Class-D amplifier output channel. The device features a low power HiFi 3z audio DSP core and a low -latency FastDSP core. The audio DSP cores paired with high-fidelity audio data converters are ideal for applications like noise cancellation, transparency, personal sound amplification, and voice processing. When operating in low -power mode, the DSP cores are optimized for small form factor applications such as true wireless stereo (TWS) headphones. In this mode, the device delivers the right level of processing power while still minimizing power consumption to extend play time. The device has the flexibility to also support applications requiring additional processing capability such as over - ear headphones, VR and AR headsets, wearables, hearing assist, and PSAP devices. In high-performance mode, the HiFi 3z core is boosted from 50Mhz to 200MHz, and the FastDSP supports double the number of instructions (up from 64 to 128). This increased processing capability can either be used to offload cycles from the host processor or enable a lowe r-cost host processor without requiring an additional external audio DSP or MCU. The device supports a -40°C to +85°C temperature range and is available in a space-saving 77-ball WLCSP package (0.4mm pitch, 3.24mm × 4.83mm)

analog.com Rev. 0 2 of 86 FUNCTIONAL BLOCK DIAGRAM HPOUT+ FB_HPOUT+ HPOUT- FB_HPOUT- DMIC_CLK0/MP13 DMIC_CLK1/MP14 DMIC01/MP8 DMIC23/ MP9 MASTER CLOCK BCLK_1 FSYNC_1 ADC FDSP SAI_0 SAI_1 ASRCI_0 ASRCO_0 DMIC ADAU1797 SERIAL AUDIO PORT 0 DIGITAL MICROPHONE DECIMATION 8kHz TO 768kHz OUTPUT OUTPUT ASYCHRONOUS SAMPLE RATE CONVERTER INPUT ASYNCHRONOUS SAMPLE RATE CONVERTER DAC FastDSP Up to 128 Instructions (25 or 50MHz) 0.9V or 1.1V LX7 (HiFi-3z) DSP up to 200 MHz at 1.1V or 50MHz at 0.9V DECIMATION 8kHz TO 768kHz OUTPUT ADC CM GENERATOR LDO or CP (0.9V or 1.1V) PLL I2C OR SPI CONTROL PORT ROUTE HPGND PGA AGND AGND REG_EN DGND DVDD AVDD BCLK_0/MP2 AVDD FSYNC_0/MP3 SAI_0 IOVDD SADATAO_0\\MP0 IOVDD SDATAI_0/MP1 CM BCLK_1/MP6 XTALI/MCLKIN FSYNC_1/MP7 XTALO SADATAO_1/MP4 SDATAI_1/MP5 ADDR0/SS ADDR1/MOSI SCL/SCLK SDA/MISO SELFBOOT/MP31 BCLK_0 FSYNC_0 CLK OSCILLATOR ADMA_0 3-LEVEL SIGMA DELTA MODULATOR 3-LEVEL FULL BRIDGE POWER STAGE OUTPUT ASYCHRONOUS SAMPLE RATE CONVERTER ASRCO_1 AIN0- AIN0+ ADC PGA AIN1- AIN1+ ADC PGA AIN2- AIN2+ DMIC45/MP10 DMIC67/MP11 DMIC89/MP12 ADMA_1 ADMA_2 SAI_0 SAI_1 ASRCI_1 INPUT ASYNCHRONOUS SAMPLE RATE CONVERTER AUDIO BUS MAP QSPI Master QSPIM_SDIO_2\\MP20 QSPIM_CLK\\MP15 QSPIM_SDIO_0/MP18 QSPIM_SDIO_1\\MP19 QSPIM_SDIO_3\\MP21 QSPIM_CS0\\MP16 QSPIM_CS1\\MP17 ROUTE SERIAL AUDIO PORT 1 ROUTE SAI_0 I3C CONTROL PORT SCL1 SDA1 UART UART_RX/MP28 UART_TX/MP27 UART_RTS/MP29 UART_CTS/MP30 JTAG JTAG_TDO/MP26 JTAG_TDI/MP25 JTAG_TMS/MP23 JTAG_TRST/MP22 JTAG_TCK/MP24 CP1+ CP1- CP2+ CP2- ROUTE ROUTE ROUTE HIFI_TIE_FDSP DVDD DVDD HPVDD HPVDD DGND DGND DGND PD ROUTE SYSTEM MEMORY 8ADMA_0 SYSTEM BUS AMAP FAST TO SLOW DECIMATOR (FDEC) SLOW TO FAST INTERPOLATOR (FINT) FINT FDEC SAI_0 SAI_1 ADC ASRCI_0 FDSP ADMA_0 INTERNAL ROUTING MATRIXADMA_1 ADMA_2 ASRCI_1 HIFI_TIE_ROUTE DMIC AMAP SAI_0 SAI_1 ADC ASRCI_0 FDSP ASRCI_1 FDEC DMIC ADMA_1 ADMA_2 ROUTE HIFI_TIE_ROUTE SAI_0 SAI_1 ADC ASRCI_0 FINT ADMA_0 ADMA_1 ADMA_2 ASRCI_1 DMIC AMAP FINT ROUTE ROUTE ROUTE PDM MODULATOR OUTPUTROUTE PDM_OUT ROUTE FDEC FINT ASRCO_0 ASRCO_1 Figure 1. Top Level Block Diagram

REVISION HISTORY

9/2023—Revision 0: Initial Version

Table 1. Electrical Characteristics

analog.com Rev. 0 4 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS SINGLE-ENDED OR PSEUDO-DIFFERENTIAL LINE INPUT MODE (DIRECT TO ADC INPUT) Full-Scale Input Voltage Input level for a 0dBFS output 0.64 VRMS

1.8 VP-P

Dynamic Range(1) A-weighted filter, fIN = 1kHz, -60dBFS output Normal operation mode (default) 100 dB Dynamic Range(1) A-weighted filter, fIN = 1kHz, -60dBFS output Extreme power- saving mode 96 dB Unweighted filter, fIN = 1kHz, -60dBFS output Normal operation mode (default) Extreme power- saving mode 93 Signal-to-Noise Ratio (SNR)(2) Normal operation mode A-weighted filter 100 dB Unweighted filter 97 THD+N Level(3) fIN = 1kHz, -1dBFS output, normal operation mode -87 dBFS Interchannel Gain Mismatch 0.04 dB Offset Error ±0.1 mV Gain Error ±0.2 dB Interchannel Isolation CCM = 10μF 100 dB Power Supply Rejection Ratio (PSRR) CCM = 10μF, 100mVP-P signal fIN = 1kHz 70 dB fIN = 10kHz 50 DIFFERENTIAL LINE INPUT MODE (DIRECT TO ADC INPUT) Full-Scale Input Voltage Input level for a 0dBFS output 1.08 VRMS

3.05 VP-P

Dynamic Range(1) A-weighted filter, fIN = 1kHz, -60dBFS output Normal operation mode (default) 106 dB Extreme power- saving mode 100

analog.com Rev. 0 5 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Unweighted filter, fIN = 1kHz, -60dBFS output Normal operation mode (default) 103 Extreme power- saving mode 97 Signal-to-Noise Ratio (SNR)(2) Normal operation mode A-weighted filter 106 dB Unweighted filter 103 THD+N Level(3) fIN = 1kHz, -1dBFS output, normal operation mode -93 dBFS CMRR 60 dB Interchannel Gain Mismatch 0.04 dB Offset Error ±0.1 mV Gain Error ±0.2 dB Interchannel Isolation CCM = 10μF 100 dB Power Supply Rejection Ratio (PSRR) CCM = 10μF, 100mVP-P signal fIN = 1kHz 70 dB fIN = 10kHz 50 SINGLE-ENDED OR PSEUDO-DIFFERENTIAL PGA INPUT MODE (PGA ENABLED) Full-Scale Input Voltage Input level for a 0dBFS output 0.54 VRMS

1.53 VP-P

Dynamic Range(1) A-weighted filter, fIN = 1kHz, -60dBFS output, +6dB PGA gain Normal operation mode (default) dB Extreme power- saving mode 98 Unweighted filter, fIN = 1kHz, -60dBFS output, +6dB PGA gain Normal operation mode (default) Extreme power- saving mode 94 Signal-to-Noise Ratio (SNR)(2) +6dB PGA gain, normal operation mode A-weighted filter 98 dB Unweighted filter 95 THD+N Level(3) fIN = 1kHz, -1dBFS output, +6dB PGA gain, normal operation mode -90 dBFS

analog.com Rev. 0 6 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS PGA Gain Range -9 +29.25 dB PGA Gain Step Size 0.75 dB PGA Gain Variation with 0dB Setting 0.05 dB PGA Gain Variation with +24dB Setting 0.15 dB Interchannel Gain Mismatch 0.005 dB Offset Error ±0.1 mV Gain Error ±0.2 dB Interchannel Isolation CCM = 10μF 100 dB Power Supply Rejection Ratio (PSRR) CCM = 10μF, 100mVP-P signal, fIN = 1kHz 70 dB DIFFERENTIAL PGA INPUT MODE (PGA ENABLED) Full-Scale Input Voltage Input level for a 0dBFS output 1.08 VRMS Dynamic Range(1) A-weighted filter, fIN = 1kHz, -60dBFS output, 0dB PGA gain Normal operation mode 104 dB A-weight(RMS)ed filter, fIN = 1kHz, -60dBFS output, 0dB PGA gain Extreme power- saving mode 100 Unweighted filter, fIN = 1kHz, -60dBFS output, 0dB PGA gain Normal operation mode 100 Extreme power- saving mode 97 Signal-to-Noise Ratio (SNR)(2) 0dB PGA gain, normal operation mode A-weighted filter 103 dB Unweighted filter 100 THD+N Level(3) fIN = 1kHz, -1dBFS output, 0dB PGA gain, normal operation mode -93 dBFS PGA Gain Range -6 +30 dB PGA Gain Step Size 0.75 dB

analog.com Rev. 0 7 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS PGA Gain Variation With 0dB Setting 0.05 dB PGA Gain Variation With +24dB Setting 0.15 dB CMRR 1kHz input frequency 60 dB Interchannel Gain Mismatch 0.005 dB Offset Error ±0.1 mV Gain Error ±0.2 dB Interchannel Isolation CCM = 10μF 100 dB Power Supply Rejection Ratio (PSRR) CCM = 10μF, 100mVP-P signal, fIN = 1kHz 70 dB DIGITAL-TO-ANALOG CONVERTER (DAC) DAC Resolution 24 Bits Digital Volume Step 0.375 dB Digital Volume Range -71 +24 dB Digital Volume Ramp Rate 4.5 dB/ms DIFFERENTIAL HEADPHONE OUTPUT Full-Scale Output Voltage 0dBFS input to analog output channel, 16Ω load 1.15 VRMS Dynamic Range(1) A-weighted filter, fIN = 1kHz, -60dBFS input 113 dB Unweighted filter, fIN = 1kHz, -60dBFS input 110 Signal-to-Noise Ratio (SNR)(2) A-weighted filter 113 dB Unweighted filter 110 Output Noise A-weighted filter, zero code digital input 2.57 µVRMS THD+N Level(3) -2dBFS, 16Ω load -90 dBV THD+N Ratio 32Ω load POUT = 1mW -83 dB POUT = 30mW -90 24Ω load, POUT = 40mW -90 16Ω load, POUT = 60mW -90

analog.com Rev. 0 8 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Headphone Output Power HPVDD = 1.8V, <0.1% THD+N ratio 32Ω load 40 mW HPVDD = 1.8V, <0.1% THD+N ratio 24Ω load 54 16Ω load 80 Gain Error ±2.5 % DC Offset ±0.1 mV Pop-Click Level A-weighted peak transient voltage 0.5 mVP Peak Output Current 350 mA Minimum Load Resistance 6 Ω Minimum Load Inductance 5 µH Maximum Load Capacitance From HPOUTP or HPOUTN to GND or HPVDD 470 pF Power Efficiency 55mW into a 16Ω load 90 % PSRR 100mVP-P signal fIN = 1kHz 89 dB fIN = 10kHz 75 COMMON MODE REFERENCE Output 0.85 V Source Impedance 5 kΩ PHASED-LOCKED LOOP (PLL) Input Frequency After input prescale 0.9 2.1 MHz Output Frequency 195.5 196.608 198 MHz Fractional Limits Fractional mode, fraction portion (N/M ratio) 0.1 0.9 Integer Limits Fractional mode, integer portion 2 256 Input Pre-Divide 1 32 Lock Time 1.024MHz input 1 ms PLL Bypass XTAL Frequency 49.152 MHz INTEGRATED LDO REGULATOR Line Regulation 1.1 mV/V Load Regulation 0.3 mV/mA

analog.com Rev. 0 9 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS INTEGRATED SWITCHED-CAP REGULATOR Line Regulation VHPVDD = 1.8V, see Figure 47 for full HPVDD range 5 mV/V Load Regulation 0.3 mV/mA CRYSTAL AMPLIFIER Jitter 270 500 ps Frequency Range 0.9 50 MHz Load Capacitance 20 pF DIGITAL INPUT AND OUTPUT Input Voltage High VIH 0.7 × VIOVDD V Input Voltage Low VIL 0.3 × VIOVDD V Input Leakage High IIH VIOVDD = 1.8V VIH = 1.1V 10 µA Input Leakage Low IIL VIOVDD = 1.8V VIL = 0.45V 10 µA Output Voltage High VOH 0.71 × VIOVDD 0.83 × VIOVDD V Output High Current Drive Strength IOH Low output drive strength 1 mA High output drive strength 3 Output Voltage Low VOL 0.1 × VIOVDD 0.3 × VIOVDD V Output Low Current Drive Strength IOL Low output drive strength 1 mA High output drive strength 3 Input Capacitance 5 pF SERIAL AUDIO DATA PORT DIGITAL INTERFACE CURRENT Digital Current (IOVDD) Single serial audio data port disabled (SPTx), crystal oscillator enabled (24.576MHz) VIOVDD = 1.8V 0.422 mA Single serial audio data port enabled (SPTx), crystal oscillator enabled (24.576MHz), Slave mode, fS = 48kHz, fBCLK = 3.072MHz 0.475 Slave mode, fS = 192kHz, fBCLK = 12.288MHz 0.481

analog.com Rev. 0 10 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS 25pF line loads, VIOVDD = 1.8V Master mode, fS = 48kHz, fBCLK = 3.072MHz 0.697 Master mode, fS = 192kHz, fBCLK = 12.288MHz 1.336 ADC INPUT TO DAC OUTPUT SIGNAL PATH Pass-Band Ripple DC to 20kHz Bandwidth, fS = 192kHz, ADCxx_FCOMP = 1, DAC_FCOMP = 1 ±0.02 dB Group Delay(4) fS = 192kHz 12.9 µs fS = 384kHz 7.5 fS = 768kHz 5 ASYNCHRONOUS SAMPLE RATE CONVERTERS Pass-Band Frequency fLRCLK < 63kHz 0.475 x fS kHz 63kHz ≤ fLRCLK < 112kHz 0.4286 x fS 112kHz ≤ fLRCLK 0.4286 x fS Audio-Band Ripple 20Hz to 20kHz bandwidth -0.1 +0.1 dB Sample Rate Frequency Range Input and output ASRCs 7 224 kHz Dynamic Range(1) ASRCIx_LPM or ASRCOx_LPM = 0 130 dB ASRCIx_LPM or ASRCOx_LPM = 1 130 ASRCIx_LPM_II or ASRCOx_LPM_II = 1 130 THD+N Level(3, 6) ASRCIx_LPM or ASRCOx_LPM = 0 -130 -120 dBFS ASRCIx_LPM or ASRCOx_LPM = 1 -120 -110 ASRCIx_LPM_II or ASRCOx_LPM_II = 1 -115 -90 Startup Lock-On Time 25 ms PULSE DENSITY MODULATION (PDM) OUTPUTS Dynamic Range(1) A-weighted filter 126 dB THD+N Level(3) -6dBFS input level -125 dBFS

analog.com Rev. 0 11 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Group Delay(5) fS = 384kHz, fPDM_CLK = 6.144MHz 7.5 µs fS = 768kHz, fPDM_CLK = 6.144MHz 4.9 MASTER CLOCK TIMING SPECIFICATIONS Master Clock Period tMP 900kHz to 49.152MHz input clock frequency 0.0203 1.11 µs SERIAL AUDIO DATA PORT TIMING SPECIFICATIONS Nominal Bit Clock Frequency fBCLK Maximum valid frequency Slave mode 49.152 MHz Nominal Bit Clock Frequency Range fBCLK Maximum valid frequency Master mode 24.576 MHz Minimum valid frequency Slave mode 0.512 Master mode 2.048 Bit Clock Low Pulse Width tBL Master or slave mode 18 ns Bit Clock High Pulse Width tBH Master or slave mode 18 ns Frame Sync Clock Frequency Range fSYNC Maximum setting 768 kHz Minimum setting 8 Frame Sync to Bit Clock Active Edge Setup Time tLS Slave mode, setup time to bit clock active edge 3 ns Bit Clock Active Edge to Frame Sync Hold Time tLH Slave mode, hold time from bit clock active edge 5 ns Data Input to Bit Clock Active Edge Setup Time tSS Master or slave mode, setup time to bit clock active edge 3 ns Bit Clock Active Edge to Data Input Hold Time tSH Master or slave mode, hold time from bit clock active edge 10 ns Bit Clock Inactive Edge to Frame Sync Edge Timing Skew tTS Master mode 6 ns Bit Clock Inactive Edge to Data Output Delay tSOD Master or slave mode, delay until VIOVDD ≥ 1.62V 0 16 ns

analog.com Rev. 0 12 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS data output logic level change Master or slave mode, delay until data output level change VIOVDD ≥ 1.1V 0 32 Bit Clock Inactive Edge to Data Output Active tSOTD Master or slave mode, delay until high-Z data output is active 0 16 ns Bit Clock Inactive Edge to Data Output High-Z tSOTX Master or slave mode, delay until active data output is high-Z 0 16 ns I2C CONTROL PORT TIMING SPECIFICATIONS Serial Clock (SCL) Frequency fSCL 1 MHz SCL Pulse Width High tSCLH 0.26 µs SCL Pulse Width Low tSCLL 0.5 µs SCL Setup Time for a Repeated Start Condition tSCS Setup time from SCL rising to SDA falling 0.26 µs SCL Hold Time for a Start Condition tSCH Hold time from SDA falling to SCL falling 0.26 µs SCL Setup Time for a Stop Condition tBFT Setup time from SCL rising to SDA rising 0.5 µs Serial Data (SDA) Setup Time tDS SDA setup time to SCL rising 50 ns Serial Data (SDA) Hold Time tDH SDA hold time from SCL falling 0 ns SCL and SDA Rise Time tSCR 400pF load 120 ns SCL and SDA Fall Time tSCF 400pF load 120 ns Bus Free Time Between Stop and Start Condition tBUF Master mode 0.5 µs I3C CONTROL PORT TIMING SPECIFICATIONS Maximum Serial Clock (SCL) Frequency fSCL Master or slave mode 6.144 MHz

analog.com Rev. 0 13 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Maximum Serial Data (SDA) Rate fSDA Master DDR mode 6.144 MHz SCL Pulse Width High tSCLH Slave mode 24 ns SCL Pulse Width Low tSCLL Slave mode 24 ns SDA Input Setup Time tDS Setup time from SDA edge to SCL rising edge Slave mode 19 ns Master mode 10 SDA Input Hold Time tDH Slave mode 11 ns SERIAL PERIPHERAL INTERFACE (SPI) PORT TIMING SPECIFICATIONS Serial Clock Frequency fSCLK 10 MHz Serial Clock Pulse Width tCCPL Low pulse 35 ns tCCPH High pulse 35 Slave Select to Serial Clock Setup Time tCLS Setup time to serial clock rising edge 5 ns Serial Clock to Slave Select Hold Time tCLH Hold time from serial clock rising 40 ns Slave Select Pulse Width tCLPH Minimum high pulse 10 ns MOSI to Serial Clock Setup Time tCDS Setup time to serial clock rising 10 ns Serial Clock to MOSI Hold Time tCDH Hold time from serial clock rising 10 ns Serial Clock to MISO Data Delay Time tCOD Delay until MISO level change 30 ns Slave Select to MISO High-Z Delay Time tCOTS Delay until MISO becomes high-Z 30 ns QUAD-SPI (QSPI) MASTER PORT TIMING SPECIFICATIONS QSPI Clock Frequency fSCLK QSPI output clock (QSPI_CLK) during self-boot 12.5 MHz QSPI Data Input Setup Time tCDS QSPI data input to clock rising edge setup time 10 ns QSPI Data Input Hold Time tCDH QSPI clock rising to data input edge hold time 10 ns

analog.com Rev. 0 14 of 86 (Supply voltages VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V (external), Supply bypass CAVDD = CHPVDD = CIOVDD = 48kHz, Audio data word width = 24-bits, Headphone amplifier load = 16Ω +33µH, default analog power modes, AC measurement bandwidth = 20Hz to 20kHz, Ambient temperature (TA) = -40°C to +85°C with typical values at +25°C unless otherwise noted, see the System Block Diagram for other external component values.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS QSPI Data Output Delay Time tCOD QSPI data output delay from clock falling edge 1 ns QSPI Data Output High-Z Delay Time tCODS QSPI data output high-Z delay from chip select rising edge 1 ns UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER (UART) PORT TIMING SPECIFICATIONS UART Baud Rate 3.125 Mbps ACTIVE-LOW HARDWARE POWER-DOWN INPUT PIN TIMING SPECIFICATIONS Power-Down Input Assert Time tRLPW Minimum time PD input must be asserted low to power down the device 20 ns Power-Down Input Hardware Enable Time REG_EN is pulled high, fMCLK = 24.576MHz 15 ms GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PIN TIMING SPECIFICATIONS GPIO (MPx) Input Latency tGIL Time delay until MPx logic level is read internally 1.5 x 1/fS µs DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS DMIC Clock Output Fall Time tCF 2mA output drive strength, 25pF load 12 ns DMIC Clock Output Rise Time tCR 2mA output drive strength, 25pF load 14 ns DMIC Data Setup time tSETUP Setup time from DMIC data edge to DMIC clock edge 10 ns DMIC Data Hold Time tHOLD Hold time from PDM clock edge to DMIC data edge 3 ns PULSE DENSITY MODULATION (PDM) OUTPUT TIMING SPECIFICATIONS PDM Clock Frequency fPDM_CLK PDM_RATE = 0 12.288 MHz PDM_RATE = 1 6.144 PDM_RATE = 2 3.072 PDM Clock Output Fall Time tCF 2mA output drive strength, 25pF load 12 ns PDM Clock Output Rise Time tCR 2mA output drive strength, 25pF load 14 ns PDM Data Hold Time tHOLD Delay time from PDM clock edge to PDM data change 35 46 ns

analog.com Rev. 0 15 of 86 1 Dynamic range is the ratio of the sum of the inband noise and harmonic power with a -60dBFS input signal level at 1kHz relative to the full-scale power level in decibels. Normal operating mode uses default settings, while extreme power saving mode changes ADCx_IBIAS to 0x1 and ADC_LP_MODE to 1. 2 SNR is the ratio of the sum of all inband noise power with no input signal relative to the full-scale power level in decibels. 3 THD+N level is the ratio of the sum of the inband harmonic power with the specified input signal level at 1kHz relative to either full-scale code (in dBFS) or a 1VRMS reference level (in dBV).

4 Group delay specified from analog input to Class-D amplifier output with FastDSP in bypass mode,

ADCxx_FCOMP = 0, and DAC_FCOMP = 0. Point group delay values taken at fIN = 1kHz, see the group delay Typical Performance Characteristics for the delay over the entire audio band. 5 Group delay specified from input to the PDM output channels to the PDM output pins. Point group delay values taken at fIN = 1kHz at the specified PDM sample rate.

6 ASRC THD+N typical value is specified at fIN = 1kHz and the maximum value is specified at fIN = 20kHz

Figure 2. I2C Interface Slave Mode Timing Diagram

1 BIT CLOCK DELAY

Figure 3. Serial Audio Data Port Input Timing (Slave Mode, Bit Clock Rising Active Edge) Figure 4. Serial Audio Data Port Output Timing (Master Mode, Bit Clock Rising Active Edge, Tristate Enabled)

Supplies externally connected at VAVDD = VHPVDD = VIOVDD = 1.8V and VDVDD = 0.9V, PLL and crystal oscillator disabled. Table 2. Quiescent Power Consumption for Power-Down Mode Configurations Configuration models a typical active noise canceling (ANC) use case with different analog power mode settings. 2 output ASRC channels. Quiescent current state (zero code or no signal input to all audio channels). Table 3. Quiescent Power Consumption Comparison for Power Management Modes 1 THD+N ratio is measured at fIN = 1kHz with a -1dBFS output for ADC input channels and at fIN = 1kHz with 50mW into 16Ω for Class-D amplifier.

TA = +25°C unless otherwise specified. Table 4. Absolute Maximum Ratings extended periods may affect product reliability.

design is required. θJA and θJC are determined using JESD51-9 on a 4-layer PCB with natural convection cooling. Table 5. Thermal Resistance Table 6. ESD Ratings negative discharges. The withstand voltage for three positive and three negative discharges is ±15,000 V; IEC Level 4. protection circuitry, damage may occur on devices subjected to high-energy ESD.

Figure 9. Top View Ball Configuration (View from Top-Side)

Table 7. Pin Function Descriptions to DGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor. to DGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor.

analog.com Rev. 0 23 of 86 C1 SCL0 / SCLK I2C Clock 0 (SCL0) or SPI Clock (SCLK). In I2C mode, this pin is an open- collector input. When the device is in self-boot mode, this pin is an open- collector output (I2C master). In I2C mode, the line connected to this pin must have a 2.0kΩ pullup resistor. In SPI mode, this pin is the SPI Clock. This pin can either run continuously or be gated off between SPI transactions. D_IN C2 SCL1 I2C/I3C Master Clock Output D_O QSPIM_ SDI03 / MP21 Quad Master SPI Data I/O 3 (QSPIM_SDIO3) or Multipurpose I/O 21 D_IO QSPIM_ SDIO1 / MP19 Quad Master SPI Data I/O 1 (QSPIM_SDIO1) or Multipurpose I/O 19 D_IO C5 QSPIM_CS0 / MP16 Quad Master SPI Chip Select 0 (QSPIM_CS0) or Multipurpose I/O 16 D_IO C6 DMIC01 / MP8 Digital Microphone Stereo Input 0 and 1 (DMIC01) or Multipurpose I/O 8 D_IO C7 XTALO Crystal Clock Amp Output. This pin is the output of the crystal amplifier. Do not use this pin to provide a clock to other ICs in the system. A_OUT D1 UART_RX / MP28 UART Port Data Receiver Input (UART_RX) or Multipurpose I/O 28 D_IO D2 UART_RTS / MP29 UART Port Flow Control Ready to Send Output (UART_RTS) or Multipurpose I/O 29 D_IO D3 ADDR0 / SS I2C Address 0 (ADDR0) or SPI Latch Signal (SS). In I2C mode, ADDR0 and ADDR1 are used to select one of four I2C address options. In SPI mode, this pin must go low at the beginning of a transaction and high at the end of a transaction. Each SPI transaction may take a different number of SCLK cycles to complete, depending on the address and read/write bit that is sent at the beginning of the SPI transaction. D_IN D4 QSPIM_CS1 / MP17 Quad Master SPI Chip Select 1 (QSPIM_CS1) or Multipurpose I/O 17 D_IO D5 DMIC45 / MP10 Digital Microphone Stereo Input 4 and 5 (DMIC45) or Multipurpose I/O 10 D_IO D6 DMIC23 / MP9 Digital Microphone Stereo Input 2 and 3 (DMIC23) or Multipurpose I/O 9 D_IO D7 DMIC_CLK0 / MP13 Digital Microphone Clock Output 0 (DMIC_CLK0) or Multipurpose I/O 13 D_IO E1 DGND Digital Ground. The AGND and DGND pins can be tied directly together in a common ground plane. PWR E2 UART_TX / MP27 UART Port Data Transmit Output (UART_TX) or Multipurpose I/O 27 D_IO

analog.com Rev. 0 24 of 86 E3 UART_CTS / MP30 UART Port Flow Control Clear to Send Input (UART_CTS) or Multipurpose I/O 30 D_IO E4 DMIC67 / MP11 Digital Microphone Stereo Input 6 and 7 (DMIC67) or Multipurpose I/O 11 D_IO E5 SDATAO_0 / MP0 Serial Audio Port 0 Output Data (SDATAO_0) or Multipurpose I/O 0 D_IO E6 DMIC_CLK1 / MP14 Digital Microphone Clock Output 1 (DMIC_CLK1) or Multipurpose I/O 14 D_IO E7 DGND Digital Ground. The AGND and DGND pins can be tied directly together in a common ground plane. PWR F1 DVDD Digital Core Supply. The digital supply can be generated from an on-chip regulator or supplied directly from an external supply. Decouple each DVDD input to DGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor. PWR F2 SELFBOOT / MP31 Self-Boot Select or Multipurpose I/O 31. Connect this pin to IOVDD through a 100kΩ resistor at power-up to enable the self-boot mode. This pin also outputs the buffered Crystal Oscillator clock by default at the start-up. Otherwise, set this pin to DGND through a 100kΩ resistor. Once the power- up is completed, this pin can be re-configured as Multipurpose I/O 31. D_IN F3 ADDR1 / MOSI I2C Address 1 (ADDR1) or SPI Data Input (MOSI). In I2C mode, ADDR0 and ADDR1 are used to select one of four I2C address options. In SPI mode, the SPI data input is used for writing registers and memory locations. D_IN F4 DMIC89 / MP12 Digital Microphone Stereo Input 8 and 9 (DMIC89) or Multipurpose I/O 12 D_IO F5 SDATAI_0 / MP1 Serial Audio Port 0 Input Data (SDATAI_0)/Multipurpose I/O 1 D_IO F6 FSYNC_0 / MP3 Serial Audio Port 0 Frame Sync/Left Right Clock (FSYNC_0) or Multipurpose I/O 3 D_IO F7 DVDD Digital Core Supply. The digital supply can be generated from an on-chip regulator or supplied directly from an external supply. Decouple each DVDD input to DGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor. PWR G1 CP2+ Switched-Cap Regulator Capacitor 2 Positive Connection. Connect a 1µF capacitor between CP2+ and CP2-. PWR G2 CP2- Switched-Cap Regulator Capacitor 2 Negative Connection. Connect a 1µF capacitor between CP2+ and CP2-. PWR G3 PD Active Low Power-Down Input. All digital and analog circuits are powered down. The external pulldown resistor to DGND is recommended on this pin to hold the device in power-down mode if the input signal from the system micro-controller is floating while power is applied to the supply pins. D_IN G4 I.C. Internally Connected. Connect to DGND. DGND

analog.com Rev. 0 25 of 86 G5 JTAG_TDI / MP25 JTAG Debug Port Data Input (JTAG_TDI) or Multipurpose I/O 25 D_IO G6 JTAG_TMS / MP23 JTAG Debug Port Master Select (JTAG_TMS) or Multipurpose I/O 23 D_IO G7 BCLK_0 / MP2 Serial Audio Port 0 Bit Clock (BCLK_0) or Multipurpose I/O 2 D_IO H1 HPVDD Headphone Amplifier 1.8V Analog Power Supply. The PCB trace to this pin must be wider to supply the higher current necessary for driving the headphone outputs. Decouple each HPVDD input to HPGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor to provide the peak current necessary for low frequency signals. PWR H2 CP1+ Switched-Cap Regulator Capacitor 1 Positive Connection. Connect a 1µF capacitor between CP1+ and CP1-. PWR H3 CP1- Switched-Cap Regulator Capacitor 1 Negative Connection. Connect a 1µF capacitor between CP1+ and CP1-. PWR H4 DGND Digital Ground. The AGND and DGND pins can be tied directly together in a common ground plane. PWR H5 JTAG_TDO / MP26 JTAG Debug Port Data Output (JTAG_TDO) or Multipurpose I/O 26 D_IO H6 JTAG_TRST / MP22 JTAG Debug Port Reset (JTAG_TRST) or Multipurpose I/O 22 D_IO H7 JTAG_TCK / MP24 JTAG Debug Port Clock (JTAG_TCK) or Multipurpose I/O 24 D_IO J1 HPOUT- Headphone Output Inverted A_OUT J2 FB_HPOUT- Headphone Output Inverted Feedback Signal. Connect close to the inverted side of the headphone load after any filtering components. A_IN J3 REG_EN Regulator Enable. Tie this pin to HPVDD to enable the internal DVDD regulator and tie this pin to ground to disable the regulator. A_IN J4 I.C. Internally Connected. Leave this pin unconnected. DNC I.C. Internally Connected. Connect to DGND. DGND J6 Internally Connected. Leave this pin unconnected. DNC J7 AGND Analog Ground. The AGND and DGND pins can be tied directly together in a common ground plane. PWR K1 HPVDD Headphone Amplifier 1.8V Analog Power Supply. The PCB trace to this pin must be wider to supply the higher current necessary for driving the headphone outputs. Decouple each HPVDD input to HPGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor to provide the peak current necessary for low frequency signals. PWR K2 FB_HPOUT+ Headphone Output Noninverted Feedback Signal. Connect close to the noninverted side of the headphone load after any filtering components. A_IN

analog.com Rev. 0 26 of 86 K3 AGND Analog Ground. The AGND and DGND pins can be tied directly together in a common ground plane. PWR K4 AIN2+ Analog Input ADC2 Non-Inverting Input A_IN K5 AIN1- Analog Input ADC1 Inverting Input A_IN K6 AIN1+ Analog Input ADC1 Non-Inverting Input A_IN K7 AVDD 1.8V Analog Supply. Decouple each AVDD input to AGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor. PWR L1 HPOUT+ Headphone Output Noninverted A_OUT L2 HPGND Headphone Amplifier and Regulator Ground PWR L3 AVDD 1.8V Analog Supply. Decouple each AVDD input to AGND with a 0.1μF capacitor, and a single shared 2.2µF bulk capacitor. PWR L4 AIN2- Analog Input ADC2 Inverting Input A_IN L5 CM Common-Mode Reference Output. The CM output is fixed at 0.85V nominal. Connect a 10μF and 0.1μF decoupling capacitor between this pin and AGND to reduce crosstalk between the ADC channels. The material of the capacitors is not critical. This pin can supply a reference bias to external analog circuits as long as they are not drawing current from the CM output (Example: high impedance input of an external amplifier). A_OUT L6 AIN0- Analog Input ADC0 Inverting Input A_IN L7 AIN0+ Analog Input ADC0 Non-Inverting Input A_IN

Figure 28. Relative Level vs. Frequency, Figure 29. Relative Level vs. Frequency, Figure 30. Relative Level vs. Frequency, Fs = 48kHz Except Figure 31. FFT, No Signal, Fs = 48kHz Except FDSP = Figure 32. FFT, No Signal, Fs = 48kHz Except FDSP = Figure 33. FFT, -1dBFS, Fs = 48kHz Except FDSP =

0.8 ASRC DISABLED

1. SAI_0 IS THE SERIAL AUDIO INTERFACE 0.
2. SAI_1 IS THE SERIAL AUDIO INTERFACE 1.
3. DMIC IS THE DIGITAL MICROPHONE.
4. ASRCI IS THE INPUT ASYNCHRONOUS SAMPLE RATE CONVERTER.
5. ASRCO IS THE OUTPUT ASYNCHRONOUS SAMPLE RATE CONVERTER.

0201 PACKAGE SIZE FOR

1. PDM_OUT CAN BE ROUTED TO ANY OF MPx PINS
2. I3C PORT CAN BE CONFIGURED AS LEGACY I2C TARGET OR CONTROLLER

Figure 48. System Block Diagram (Analog Microphones, Self-Boot Mode)

analog.com Rev. 0 35 of 86 THEORY OF OPERATION The device is a low power, high-performance audio codec with dual audio processing cores. The device features both a low power HiFi 3z audio DSP core and a low latency optimized FastDSP core. The dual audio DSP cores paired with the low power, high-performance data converters make the device ideal for applications such as noise cancellation, transparency, personal sound amplification, and voice processing. The device provides three low power, lo w-noise analog input channels each with a high -performance ADC. The flexible analog inputs accept both line -level and analog microphone input sources. Each analog input can be configured as a single -ended, differential, or pseudo -differential input with or without a programmable gain amplifier (PGA). In addition, the device also supports up to ten digital microphone input channels with two independent digital microphone output clock sources. The analog output channel includes a high-performance DAC and a low-noise, high-efficiency differential headphone amplifier. The driver is an ultra -low power, pulse density, closed-loop, filter-less, sigma-delta Class-D amplifier that is capable of driving speakers with a 6Ω impedance or higher. The input ADCs and output DAC are high-performance, 24-bit Σ-Δ converters that operate at a selectable 8 kHz to 768 kHz sampling rate. Each data converter channel includes a high resolution, digital soft volume control, and an optional high-pass filter with a configurable cutoff frequency. The device provides two independent serial audio data ports. Each can be configured as either a master or slave interface, and they support I2S, left justified, right justified, and up to 16 channel TDM compatible data formats. The data port supports either 1.2V or 1.8V logic levels (as set by IOVDD voltage). The device also provides an I 2C/SPI compatible control port that supports both slave mode and master mode (with a software driver running in the HiFi 3z core) operation. In I2C mode, the control port can be assigned one of 4 possible addresses and supports up to fast mode plus timing. The Tensilica HiFi 3z core is optimized for low power audio processing. This core can either be directly programmed in C/C++ or graphically programmed using the SigmaStudio®+ software from Analog Devices, Inc. It includes a library of configurable audio processing blocks such as filters, dynamics processors, mixers, and low-level DSP functions for fast, graphical development of custom signal flows. Software running on the core also enables access to additional hardware interface ports and operating modes including the I 3C, QSPI, and UART interface ports, master m ode control for the I2C/SPI port, and debug access through the JTAG interface port. The FastDSP core has a reduced instruction set optimized for latency-critical applications such as noise cancellation and ambient transparency. The program and parameter random access memory (RAM) can be loaded with a custom audio processing signal flow built using SigmaStudio+. The device also has a self -boot function that can load the program and data/parameter RAMs of both cores along with the register settings for the device on power -up using an external electronically erasable programmable read - only memory (EEPROM) or flash memory over a master quad SPI int erface. The external flash memory is fully memory-mapped to the HiFi 3z bus fabric. The flexible SigmaStudio+ software connects to the device control port and can both configure the device registers, as well as program and control the cores. The graphical user interface (GUI) provides the flexibility and programmability needed by an experienced DSP programmer. However, the GUI is also designed to be user-friendly to enable even less experienced users with baseline digital or analog audio processing knowledge to design the DSP signal flow and export the flow to a target application. A full description of the device register map and memory maps is available in the companion programming guide.

port. If the input source clock frequency is within the 900kHz to 2.1MHz range it can be directly accepted by the PLL. using the on-board crystal oscillator. for operation over the extended -40°C to +85°C temperature range.

128 INSTRUCTIONS

Figure 49. Device Input and Output Signal Routing

analog.com Rev. 0 37 of 86 Power Supplies and Sequencing Requirements The device requires four primary power supplies. Three of these supplies must be provided externally to the device. These are the primary analog supply (AVDD), the headphone amplifier and internal linear regulator/charge pump supply (HPVDD), and the digita l interface logic level supply (IOVDD). The core digital supply (DVDD) can either be provided externally or generated internally from the HPVDD supply. The analog supply (AVDD) and headphone/internal regulator supply (HPVDD) support operation from a 1.8V nominal level. The digital interface logic supply (IOVDD) supports operation from either a 1.8V or 1.2V nominal level. The required digital core supply level (DVDD) is dependent on the required core processing load of the implemented use case. In low power /light processing load cases, a 0.9V nominal DVDD supply level is acceptable (HIFI_SPEED = 0), while high performance/heavy processing load cases require a 1.1V nominal DVDD supply level (HIFI_SPEED = 1). This applies both for an internally generated or an externally provided DVDD source. Power Supply Sequencing During the initial system power-up supply sequencing, the AVDD and HPVDD supplies must be powered up and within their operating range before or at the same time that IOVDD is powered up into its operating range. Do not power up the IOVDD supply when the AVDD and HPVDD supplies are outside of their normal operating ranges. If the DVDD supply is to be generated by the internal linear regulator or charge pump, then the REG_EN input should be externally connected to the HPVDD supply. Otherwise, the REG_EN input must be connected to ground and the DVDD supply must be externally supplied to the device before power-up. Before powering down the device supplies, all signal input and output channels should be muted or powered down. Audible glitches may be recorded or played back if any supply is removed while audio channels are active. Hardware Full Chip Power-Down States The device is placed into the hardware full chip power-down (or hardware shutdown) state when the PD input pin is asserted low. This is the lowest power device state, and in this state, external supplies can either be present or fully powered down (with proper sequencing). In this state, the internal regulators for DVDD (if used) are also disabled and powered down. The device is fully reset in this state and retains no state memory (all registers and blocks return to their PoR states/configurations). No interface communication with the device is possible in this state. As with the supply sequencing, before entering the hardware power -down state (asserting the PD input low), all signal input and output channels should be muted or already powered down. Otherwise, audible glitches may be recorded or played back before the hardware shutdown sequence is completed. When the device transitions out of reset and the hardware power -down state (supply sequencing is complete and the PD input is asserted high), the device enters the software full chip power-down (software shutdown) state. Software Full Chip Power-Down State The software power-down state is the lowest power state where software/driver control is possible, and the control register map retains any programmed settings. In this s tate, the I 2C/SPI control ports operate as slave interfaces. Most other blocks are powered down except for internal DVDD regulators (if the REG_EN input is high), and both the common mode voltage generator and the crystal oscillator (by default). In this state the device power enable bit (POWER_EN) defaults to 0. To transition out of the software power -down state set POWER_EN = 1. Conversely, from a power -up state, setting POWER_EN = 0 transitions the device back into the software power -down state. As with previous power-down scenarios, to avoid audible glitches all signal input and output channels should be muted or powered down before setting POWER_EN = 0.

analog.com Rev. 0 38 of 86 By default, in the software power -down state the common -mode output voltage (and CM output pin) is a ctive (CM_KEEP_ALIVE = 1). To reduce power consumption, this can be disabled by setting CM_KEEP_ALIVE = 0. However, as a result, the device will have a longer power -up time as this adds a wait time of up to 35ms (maximum) for the common mode voltage to cha rge before any analog blocks (such as the PLL or converters) can be enabled. Conversely, with CM_KEEP_ALIVE = 1, the software power-down current is increased but the power-up time is faster as this wait time can be omitted. Similarly, the internal digital clocks can be gated to reduce power consumption when idle in the software power - down state by setting XTAL_EN = 0. To idle the device in the lowest possible power configuration for the software power-down state (POWER_EN = 0), set both CM_KEEP_ALIVE = 0 and XTAL_EN bit = 0. The digital portion of the chip has several power domains. By default, in the software power -down state, only the domain that powers the control ports and their associated registers are powered on. The remainder of the digital domain has its power supplies gated resulting in the loss of the internal states. In addition, to retain core (FDSP/HIFI 3z) state memory in the software power-down state set the KEEP_MEM bit to 1. Device Power-Up Sequencing The device transitions out of the software power-down state when POWER_EN is set to 1. The power supplies on the rest of the digital portion of the chip are not enabled until this occurs, so this must be set first during the power -up sequence. After the internal digital power supplies are powered up, the PLL is locked, and other needed sequencing is complete, the POWER_UP_COMPLETE bit sets to 1 and the DSP memories can be programmed or accessed. Interrupt requests (IRQs) can also be sent when the power-up is completed. If the IRQs are used to indicate power up is complete, then the appropriate IRQs must be unmasked. For the power -up sequence, these are the IRQ1_POWER_UP_COMPLETE and IRQ2_POWER_UP_COMPLETE bits. The associated mask bits that must be cleared (they are set by default) are the IRQ1_POWER_ UP_COMPLETE_MASK and IRQ2_POWER_UP_COMPLETE bits. The device has highly flexible block -level power controls. Each channel of each block can be power ed on or off separately. There is a control bit, MASTER_BLOCK_EN, that by default is 0 and that overrides all block level enables except for PLL_EN, XTAL_EN, HIFI_EN, and FDSP_EN. The PLL, HiFi 3z DSP, and FastDSP can be enabled even when MASTER_ BLOCK_EN = 0. All other blocks are always in power-down in this state, allowing the PLL to be enabled and locked and the DSP memories to be initialized before all other signal path blocks are enabled. When configuring the device, it is recommended to fully set up all control registers and block level power controls to their desired state before setting MASTER_BLOCK_EN = 1. This allows the PLL to lock and initialize the DSP memories to be ready to be used before MASTER_BLOCK_EN is set. Block-level power controls and other settings can be changed on the fly while the chip is active. However, care must be taken when enabling or disabling blocks other than the DAC and/or headphone mode blocks that are actively routed out to the DAC and/or headphone mode as audible glitches may occur. To power down the chip, disable or mute any active audio channels, set MASTER_BLOCK_EN low, and then set POWER_EN low. This allows the device to power down all blocks with any required power-down sequencing.

Table 8. General Power-Up Sequencing Overview I2C/SPI ports, and enables the common mode voltage generator and crystal oscillator. 2 Wait 15ms if the REG_EN input pin was asserted high in step 1. initiates the power-up sequence. The POWER_UP_COMPLETE bit sets when this is complete. Note: XTAL_EN is set to 1 by default in this sequence and must be set this way to complete this step. 4 Configure the PLL using CLK_CTRLx registers and set the XTAL_MODE and PLL_EN bits. other time after PD = 1 but should be completed before step 8. verified when the POWER_UP_COMPLETE bit is 1. Wait until both bits are set. 8 Set MASTER_BLOCK_EN = 1 to power up the blocks that are enabled for the use case. 9 Set FDSP_RUN = 1 and HIFI_RUN = 1 to instruct the DSPs to operate. configuring the input and output audio data converter channels. is shown first, and the first byte (bits[32:25]) is shown last. The bits are ordered from MSB first to LSB last. Table 9. Use Case Power-Up Sequencing Example

1 Power-Up External

first, then power up the external IOVDD supply to its operating range.

2 Power-Up DVDD Verify that the REG_EN input pin is pulled high (HPVDD) and wait 15ms for DVDD

3 Verify CM Fast

(located in Register Address 0xF000002C). 4 Set Power Enable Set POWER_EN = 1 by writing 0x01000000 to Register Address 0xF000003C. 5 Wait for CM Voltage If CM_KEEP_ALIVE = 0 and REG_EN = 0, wait 35ms. 6 Disable CM Fast Charge Set CM_STARTUP_OVER = 1 by writing 0x02000000 to address 0xF000002C. 7 Apply Clocks Apply the necessary clocks to source the PLL (MCLK or BCLK0/1).

analog.com Rev. 0 40 of 86 8 Disable Clock Gating Set XTAL_EN = 1 by writing 0x02000000 to Address 0xF0000030. XTAL_EN must = 1 to ungate the clock tree, even if the crystal oscillator is not used.

9 Clock Configuration Configure XTAL_MODE (crystal oscillator used), set the PLL for Integer Mode and

set MCLK as the PLL input source by writing 0x08070000 to Address 0xF0000040. 10 Set Clock Ratio Set PLL_INPUT_PRESCALER = 16 by writing 0x10000000 to Address 0xF0000044. 11 Set Clock Ratio Set PLL_INTEGER_DIVIDER = 128 by writing 0x80000000 to Address 0xF0000048. Note these PLL settings configure the PLL output for 196.608MHz.

12 Update PLL Settings Set PLL_UPDATE = 1 to ensure these changes take effect in the PLL by writing

0x03000000 to Address 0xF0000030. 13 Verify PLL Lock Check PLL_LOCK (read 0xF0000408). If PLL_LOCK = 0, wait until PLL_LOCK = 1.

14 Verify Successful

Check POWER_UP_COMPLETE = 1 (read 0xF000040C). If POWER_UP_COMPLETE = 0, wait until POWER_UP_COMPLETE = 1. If POWER_UP_COMPLETE = 1 and PLL_LOCK = 1, continue configuring the device.

15 Enable Boot Loader

Set PROC_EN = 1 by writing 0x10000000 to Address 0xF0000034. Note that an app pack is not loaded into the L2 memory in this example, but the boot loader must still be enabled to ensure access to the HiFi 3z memory, FDSP memory, or Main Map registers. PROC_EN can be cleared at any subsequent point in the sequence once the boot loader is enabled.

15 Enable Switched

Enable the switched-cap regulator to switch over from the LDO regulator, and set the generated DVDD level to 0.9V. Set CP_EN = 1 and SEL_0V9 = 1 by writing 0x32000000 to Address 0xF000002C. 16 Set ADC Sample Rate Set the ADCs to fS = 48kHz by writing 0x04040000 to Address 0xF0000058.

17 Set Differential Analog

Input Mode Set the ADCs to differential mode by writing 0x07000000 to Address 0xF000005C. 18 Set DAC Sample Rate Set the DAC_FS = 48kHz by writing 0x44000000 to Address 0xF00000F4. 19 Route ADC to DAC Set DAC_ROUTE0 = ADC0 by writing 0x38000000 to Address 0xF0000108. 20 Enable Converters Power up ADCs and playback path (write 0x17000000 to Address 0xF000000C).

21 Serial Port Setup

Ensure all necessary clocks are now present on the serial port(s) if needed for a different concurrent signal channel use case.

22 Core Configuration

Set PROC_BYPASS = 0, PROC_ EN = 0 and FDSP_EN = 1 by writing 0x01000000 to Address 0xF0000034. (Note: Insert other core configuration if needed)

23 Set Master

Block Enable Set MASTER_BLOCK_EN = 1 by writing 0x33000000 to Address 0xF000002C.

24 Set HiFi 3z Core

Enable (If Used) If using VDVDD = 0.9V, set HIFI_SPEED = 0 (write 0x01000000 to address 0xF00001FC), then set PROC_EN = 1 (write 0x10000000 to Address 0xF0000034).

25 Set FDSP Core

Run Bit (If Used) Set FDSP_RUN by writing 0x01000000 to Address 0xF00001B8. If both HiFi 3z and FDSP are used write 0x11000000 instead. 26 Verify data Input Ensure that audio data is now present if using the serial audio data port input.

27 Enable ADC Soft

Volume Ramping Set ADC_HARD_VOL = 0 by writing 0x40000000 to Address 0xF000006C.

28 Enable DAC Soft

Volume Ramping Set DAC_HARD_VOL = 0 by writing 0x44000000 to Address 0xF00000F8. 29 Unmute ADCs Unmute ADCs by writing 0x00000000 to Address 0xF0000074. 30 Unmute DAC Unmute the DAC and playback amp (write 0x04000000 to Address 0xF00000F8). 31 Check Amp Output Verify audio signal output from the headphone amplifier.

analog.com Rev. 0 41 of 86 Internal DVDD Linear Regulator (LDO) and Switched-Cap Regulator The device features both a fully integrated linear regulator and an internal switched -cap regulator. These can be used to internally generate the required 0.9V or 1.1V nominal DVDD voltage from the HPVDD input (nominal 1.8V). If the REG_EN input pin is ti ed to ground when the device enters the software power -down state, the internal regulators are disabled, and an appropriate DVDD voltage must be supplied externally to the DVDD pin. If the REG_EN pin is instead tied to HPVDD, then when the device enters the software power-down state the internal LDO regulator automatically enables and generates the required DVDD voltage (maximum settling time of 20ms). Once the device is in the software power -down state (if the internal DVDD regulator is enabled), the inte grated switched-cap regulator (charge pump) can be enabled instead of the LDO by setting the CP_EN bit to 1. To utilize this integrated regulator mode, two additional external caps are required and must be populated. The switched -cap regulator provides a m ore efficient power structure than the LDO for DVDD voltage regulation, however, two additional external caps are required (and must be populated) and line regulation is slightly degraded. When using internal DVDD regulator mode, the SEL_0V9 bit determines the DVDD voltage output level and by default, the output is set to 1.1V. It can also be configured to 0.9V (SEL_0V9 = 1), however, this should only be selected when the HiFi 3z core is running at 50MHz (HIFI_SPEED = 0). The internal DVDD voltage regulation level should be selected during device initialization before activating any configured signal channels. If the DVDD regulation level also needs to be changed for different use cases, to avoid any potentially audible glitches it is recommended that all active audio channels should first be muted (or disabled if not used in the new use case). Next, if the HiFi 3z core or FDSP is active, then PROC_EN and FDSP_RUN should be cleared before changing the DVDD voltage. Once this is done, the new DVDD regulation level can be selected (with the SEL_0V9 bit). The system should then wait for the DVDD regulation settling time to elapse (maximum of 15ms). During this time, the software should not read from the device's memory. Once the new DVDD regulation level is st able, the new use case and applicable processors can be fully enabled, and all audio channels for the new use case can be unmuted and/or enabled. The internal regulators require the CM voltage to be powered up to operate. Therefore, when CM_KEEP_ALIVE = 1, both the CM output and internal DVDD regulators remain powered up in the software power-down state. To minimize device power-down state power consumption when using the internal regulator, either disable common mode keep alive (CM_KEEP_ALIVE = 0) or place the device into the hardware power-down state.

(XTALI/MCLKIN) or from either of the bit clock input pins (BCLK_x). amplifier can be disabled by setting XTAL_MODE to 0. cases (bit clock, master clock, or crystal clock input), XTAL_EN must be set high for device power-up to be possible. PLL_SOURCE bits) to generate all required internal reference clocks and any master mode interface output clocks. PLL_INPUT_PRESCALER bits) to divide down the input source clock frequency to within this range (see below). output frequency, which is a 48kHz sample rate x 4096. The clock and PLL structure are illustrated in Figure 50. Figure 50. Clock Input and PLL Block Diagram

analog.com Rev. 0 43 of 86 PLL Integer Clock Ratio Mode Integer clock ratio mode (PLL_TYPE = 0) can be used when the target PLL output frequency of 196.608MHz is an integer multiple of the PLL input clock frequency (after prescaler divide). The integer feedback clock divider calculation is shown below, and the divider ratio value R is set with the PLL_INTEGER_DIVIDER bits. 𝑓𝑃𝐿𝐿_𝑂𝑈𝑇𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 𝑓𝑃𝐿𝐿_𝐼𝑁𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 = 𝑅⁄ For example, if the selected external reference clock input frequency is 24.576MHz, and the integer clock prescaler divider ratio is set to 16 (PLL_INPUT_PRESCALER = 16), the PLL input clock frequency will then be: 𝑓𝑃𝐿𝐿_𝐼𝑁𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 = 𝑓𝐸𝑋𝑇𝐸𝑅𝑁𝐴𝐿_𝐼𝑁𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 (𝑃𝐿𝐿_𝐼𝑁𝑃𝑈𝑇_𝑃𝑅𝐸𝑆𝐶𝐴𝐿𝐸𝑅)⁄ 1.536𝑀𝐻𝑧 = 24.576𝑀𝐻𝑧 16⁄ The required PLL output frequency is 196.608MHz, so the integer feedback clock ratio R must be 128 (set with the PLL_INTEGER_DIVIDE bits). In integer clock ratio mode, the fractional mode numerator and denominator settings have no effect (M and N as set by the PLL_DENOMINATOR and PLL_NUMERATOR bits respectively) 𝑓𝑃𝐿𝐿_𝑂𝑈𝑇𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 𝑓𝑃𝐿𝐿_𝐼𝑁𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 = 𝑅⁄ 196.608𝑀𝐻𝑧 1.536𝑀𝐻𝑧⁄ = 128 By default, the power on reset states of the prescaler and integer divider bits are configured for a typical use case with a 24.576MHz input reference clock source to the PLL. PLL Fractional Clock Ratio Mode Fractional clock ratio mode (PLL_TYPE = 1) must be used when the target PLL output frequency of 196.608MHz is NOT a simple integer multiple of the PLL input clock frequency (after prescaler divide). Instead, a mixed clock ratio calculation is used (as shown below). The integer ratio portion R is still set with PLL_INTEGER_DIVIDER, and the fractional clock denominator M and numerator N are set with the PLL_DENOMINATOR and PLL_NUMERATOR bits. 𝑓𝑃𝐿𝐿_𝑂𝑈𝑇𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 𝑓𝑃𝐿𝐿_𝐼𝑁𝑃𝑈𝑇_𝐶𝐿𝑂𝐶𝐾 = 𝑅 + 𝑁 𝑀⁄⁄ For example, if the selected external reference clock input frequency is 13MHz then one possible integer clock prescaler divider ratio is 10 (PLL_INPUT_PRESCALER + 1 = 10) resulting in a PLL input clock frequency of 1.3MHz. 196.608𝑀𝐻𝑧 1.3𝑀𝐻𝑧 = 151.2369 = 151 + 77 325⁄⁄ Taking the ratio of the PLL output clock to the input clock results in a value of ~151.2369. Splitting this into whole numbers and fractional portions results in 151 + 77/325 or R = 151, N = 77, and M = 325. Note that when the PLL is used in fractional mode, it is important that the N/M ratio be kept within the 0.1 ≤ N/M ≤ 0.9 range to ensure correct operation of the PLL. When used in fractional mode, the input to the PLL after the input divider must be ≥1MHz. PLL Reference Clock Output If the selected external PLL clock source is from the XTALI/MCLKIN input (PLL_SOURCE = 0x00), the device can also output this clock or a divided-down version of it to any available multipurpose pin. The input clock (XTALI/MCLKIN input) to output clock ratio (on a multipurpose output) is selected with the MCLKO_RATE bits and can be set to no divider (divide by 1) or to any power of 2 integer divider ratio from 2 to 128. By default, the SELFBOOT/MP31 pin outputs the XTALI/MCLKIN input clock divided by 2. This occurs automatically when the device completes the transition from the hardware power-down state to the software power-down state. If this clock is not needed, to reduce power consumption it can be disabled with the MP31_MODE bits.

external clock source (PLL_SOURCE) is at a fixed 49.152MHz frequency. (HIFI_SPEED = 0), and as a result, the number of instructions it can execute is limited (≤ 50MIPs). Table 10. PLL Bypass Mode Power Reduction

1 Bypassed —

the HiFi 3z DSP core processing limitation. bit, and it must be set to select the same clock source on each device (to be synchronized). external clock source (to the PLL), then an internal PLL-derived sync source can be used instead. recommended. To avoid potentially audible glitches, the PLL should not be reconfigured while it is active.

1. Ensure that POWER_EN = 1.
2. Configure (or reconfigure) the PLL control bits.
3. Write 1 to PLL_UPDATE to propagate the PLL settings.
4. Enable (or re-enable) the PLL by setting PLL_EN = 1.

all other circuitry waits until the PLL is locked to begin the power-up sequences. FDSP_EN = 1 respectively), and the PLL (if not bypassed) must be locked.

also accepts up to ten digital microphone input sources. without a programmable gain amplifier (PGA). simplified block diagram is shown in Figure 51. Figure 51. Analog Input Channel Simplified Block Diagram on or reset) is single-ended mode with PGA disabled. be corrected by setting the ADCx_INVERT bits. negative (AINx-) analog input pins. input, the polarity is inverted and can be corrected by setting the ADCx_INVERT bits. Table 11 shows the settings required for each of the supported analog input channel configurations.

analog.com Rev. 0 48 of 86 The PGA can also be configured for coarse attenuation settings (PGAx_MODE). In this mode, the PGA attenuation settings are used instead of the gain settings, and they can be adjusted from 0dB to -9dB in 3dB steps (PGAx_ATTEN). The internal resistors used for these settings are precisely matched to each other to minimize gain and attenuation errors. However, the exact nominal value of the resistors depends on various conditions in the silicon manufacturing process and can vary by as much as ±20%. The PGA gain of each analog input channel by default is set individually by the respective PGAx_GAIN bits. To enable synchronous PGA gain changes across all three channels, set the PGA_GAIN_LINK bit to 1. When set, the PGA gain of all three channels matches the channel 0 setting (PGA0_GAIN). The analog input channel PGA has four power modes: lowest power, low power, normal, and high -performance modes. By default, the PGA operates in normal mode, and the mode is changed with the PGAx_IBIAS bits. Analog Input Coupling Capacitor Precharge By default, precharge amplifiers are enabled to quickly charge the large AC coupling capacitors in series with the analog inputs. Precharging these capacitors before enabling the channels can prevent audible signals. The precharge amplifiers are powered up by default when an analog input ADC channel is enabled (ADCx_EN set to 1) and remain active for the selected precharge time (as set by the ADC_AIN_CHRG_TIME bits). The Precharge time can be disabled or set to one of the available times ranging from 5ms to 400ms. Longer precharge times are needed for larger input coupling capacitors, but this does increase the analog input channel startup times as well. The internal impedance for the AINx pins is 750Ω during Precharge. However, at startup, the internal impedance is governed by the time constant of the common mode reference voltage (CM pin) because the precharge amplifiers use the CM voltage as a reference. Analog Input Channel ADCs Each of the three analog input channels features a high-performance 24-bit, Σ-Δ ADC. Each analog input channel and ADC is enabled with the respective ADCx_EN bit and provides a selectable sample rate, configurable digital filters, and digital volume control. Analog Input Channel ADC Full-Scale Level The full-scale analog input (for a 0dBFS output code with 0dB of PGA gain) is nominally 1.08V RMS for a differential input. For a single-ended or pseudo-differential input, the full-scale input depends on whether the PGA is enabled. It is 0.64VRMS with the PGA disabled and 0.54VRMS with it enabled. Input signals that exceed the full-scale level (including PGA gain) cause the channel to clip. Analog Input Channel ADC Configuration The output sample rate for the ADC decimation filters can be configured from 8kHz to 768kHz. The sample rate for analog input channels 0 and 1 is linked (ADC01_FS), while the sample rate of channel 2 is individually selected (ADC2_FS). Both high-order (higher delay) and low -order (reduced delay) decimation filters are available. As before the setting for channel 0 and channel 1 is linked (ADC01_DEC_ORDER), while channel 2 i s configured separately (ADC2_DEC_ORDER). The output of each channel can be inverted with the ADCx_INVERT bits. To remove DC offsets, each channel provides a digital high-pass filter (enabled with the ADCx_HPF_EN bits). The HPF cutoff frequency can be configured from 0.25Hz to 241Hz. The setting for channels 0 and 1 is linked (ADC01_HPF_FC), while channel 2 is configured separately (ADC2_HPF_FC).

analog.com Rev. 0 49 of 86 Compensation filters for the high-frequency roll-off of the ADC decimation filters are provided. These are enabled for channels 0 and 1 with the ADC01_FCOMP bit and for channel 2 with the ADC2_FCOMP bit. Disabling the compensation filters (default) provides the lowest propagation delay, but results in a slight signal attenuation in the passband at higher frequencies. Analog Input Channel ADC Digital Volume Control The digital volume of each channel can be set from -71.25dB to +24dB in 0.375dB steps with the ADCx_VOL bits. Each analog input channel can be independently placed into digital mute by setting the cor responding ADCx_MUTE bit high. The channels can also be digitally muted by configuring the digital volume control (ADCx_VOL) to the lowest setting (code 0xFF). By default, fine-step volume ramping based on zero cross -detection is used for all digital volum e changes. Volume change zero cross detection can be disabled with the ADC_VOL_ZC bit, and when disabled each volume step occurs without regard to signal level every 4.5dB/ms. Volume ramping can be bypassed entirely to allow for instantaneous (hard) single-step volume changes by setting the ADC_ HARD_VOL bit. By default, volume control is independent for each channel. If the ADC_VOL_LINK bit is set, the volume level and any changes for all channels are linked to the channel 0 settings. When a channel is enabled, it powers up at the volume set by the respective ADCx_VOL bits. When disabled, it powers down immediately without ramping down the volume. Analog Input Channel ADC Bias and Power Modes By default, all analog input channel ADCs are configured to operate with a normal bias current in the standard power mode. The ADC bias current can be set to (in order of increasing power consumption and overall performance) extreme power saving, power saving, normal operation, and enhanced performance modes. The overall power mode of all channels is set with the ADC_LP_MODE bit. In low -power mode, a +6dB gain is applied to any channel where the PGA is disabled. Digital Microphone Input Channels The device provides two independent digital microphone (DMIC) cloc k outputs (DMIC_CLK0 and DMIC_CLK1), and five separate digital microphone data input interfaces (DMIC0_1, DMIC2_3, DMIC4_5, DMIC6_7 or DMIC8_9). Each of the DMIC pins shares functionality with a multipurpose pin (MP9 to MP14). Digital Microphone Input Channel Interface Each input interface (DMICx_x) can accept two DMIC input channels, allowing for up to ten total digital microphone input channels. Each DMIC data input and signal channel is enabled with the corresponding enable bit (DMICx_EN). The decimation ratio and resulting output sample rate of each digital microphone input channel pair are set by the corresponding DMICxx_FS bit. The output sample rate of each pair can be set from 8kHz to 768kHz. Each digital microphone data input channel pair (DMICx_x) is mapped to one of the two DMIC clock outputs (DMIC_CLK0 or DMIC_CLK1). The DMIC clock source is mapped independently for each DMIC data input with the respective DMICxx_MAP bit. The DMIC data inputs only support the two DMIC clock outputs and c annot be clocked from another source (such as an external host or audio device).

analog.com Rev. 0 50 of 86 Each input interface accepts pulse density modulation (PDM) input data. PDM input data is channel interleaved with data for one channel on rising clock edges and the data for the second channel on falling clock edges. The PDM data is mapped directly to the relative pulse code modulation (PCM) data full -scale. For example, data with a 50% PDM density results in a -6dBFS output amplitude (when set to the default DMIC volume setting of 0dB). By default, the lower channel number of each DMIC input channel pair is clocked on the DMIC clock rising edge while the higher channel is on the falling edge (often denoted as the left channel on the rising edge and the right channel on the fal ling edge for two microphone systems). The polarity of the active edges for each channel pair can be swapped by setting the corresponding DMICxx_EDGE bit high. Digital Microphone Input Channel Clocking Each of the two DMIC clock outputs is independently enabled with the respective DMIC_CLKx_EN bit. The frequency of each clock output is also set individually with the corresponding DMIC_CLKx_RATE bits. The clock output supports a wide range of output frequencies from a maximum of 6.144MHz down to a minimum of 256kHz. The available DMIC clock frequencies are restricted by the selected output sample rate (set by DMICxx_FS). DMIC clock rates from 256kHz to 4.096MHz (in integer ratios of 2) are only valid with 8/16kHz output sample rates (common voice sample rates). DMIC clock rates from 384kHz to 6.144MHz (also in integer ratios of 2) are only valid with 12/24/48/96/192/384/768kHz output sample rates. Digital Microphone Input Channel Filters The DMIC input decimation filter provides both a fourth -order and a fifth -order option. This is selected for each channel pair with the corresponding DMICxx_DEC_ORDER bits. The fourth -order filter provides the lowest propagation delay, while the fifth -order filter improves in -band noise shaping and may be needed to maximize performance with some very high dynamic range digital microphones. The device provides compensation filters for the high -frequency roll-off of the input decimation filters. These are enabled for each channel pair with the appropriate DMICxx_FCOMP bits. Disabling these filters (default) provides the lowest propagation delay but results in a slight signal attenuation in the passband at higher frequencies. To remove DC offsets, each DMIC input channel pair also provides a digital high -pass filter (enabled with the corresponding DMICxx_HPF_EN bits). The HPF cutoff frequency can be configured from 0.25Hz to 241Hz. The cutoff frequency setting for each channel pair is selected with the appropriate DMICxx_HPF_FC bits. The digital microphone input channels and the analog input channel ADCs are completely independent and do not share the same digital decimation filter chains.

digital volume control (DMICx_VOL) to the lowest setting (code 0xFF). By default, fine -step volume ramping based on zero cross -detection is used for all DMIC chan nel volume changes. for instantaneous (hard) single-step volume changes by setting the DMIC_ HARD_VOL bit. level and any changes for all channels are linked to the DMIC input channel 0 volume settings. powers down immediately without ramping down the volume. (DMIC_CLKx) should be mapped (with DMICxx_MAP) to the selected DMIC input channel pair. DMICxx_EDGE). Figure 55 illustrates the typical connections in an example stereo DMIC use case. Figure 55. Digital Microphone Stereo Use Case Example

analog.com Rev. 0 52 of 86 Output Signal Channels The device provides a single amplifier output channel that includes a high -performance DAC and a low-noise, high- efficiency differential Class-D headphone amplifier. The device also provides two low latency, high -performance 1 -bit PDM output channels suitable for driving an external amplifier or transmitting data to a peripheral device. Audio data can be routed into any combination of the output signal channels from the outputs of most internal audio subsystem blocks including the serial data ports, serial data input ASRCs, analog input ADC channels, DMIC input interfaces, interpolator filter channels, audio bus map, audio output DMA, FastDSP core, and the HiFi 3z core. Output Channel DAC The analog output audio playback channel features a high -performance, low latency, 24 -bit resolution Σ -Δ digital- to-analog converter (DAC). The channel is enabled with the PB0_EN bit and provides a selectable input sample rate, configurable digital filters, and digital volume control. Output Channel DAC Full-Scale Level The full-scale output (corresponding to a 0dBFS input code with 0dB of digital volume) is nominally 1.15V RMS from the DAC to the differential Class-D amplifier output. Output signals that exceed the full-scale input code (with digital volume applied) cause the channel to clip. The signal level where the channel digitally clips can be reduced (from 0dBFS) to a selected lower level using the DAC_HF_CLIP bits. This setting reduces the full -scale level in increments of 1/256 (single -bit decrement at 8 -bit resolution per setting). By default, it is set for no clipping level reduction relative to full scale. The control allows the clipping level to be set from 255/256 (-0.034dBFS) down to 1/256 (-48.165dBFS). Output Channel DAC Configuration The analog output channel DAC can accept audio data from other blocks at a range of input sampling rates from 8kHz to 768kHz. The DAC input data sample rate is selected with the DAC_FS bits, and the output of any audio channel routed to the DAC must be configured to the same sample rate. The input data source is selected with the DAC0_ROUTE bits. The input signal to the channel can be inverted with the DAC_INVERT bit. Both high -order (higher delay) and low - order (reduced delay) input interpolation filters are provided, and this is selected with the DAC_MORE_FILT bit. To remove DC offsets a digital high-pass filter (HPF) is available and can be enabled with the DAC0_HPF_EN bit. The cutoff frequency can be configured from 0.25Hz to 241Hz and is selected with the DAC_HPF_FC bits. The device provides optional compensation filters for the high -frequency roll-off of the analog output channel DAC that is enabled with the DAC_FCOMP bit. Disabling the compensation filters (default) provides the lowest propagation delay, but results in a slight signal attenuation in the passband at higher frequencies.

analog.com Rev. 0 53 of 86 Output Channel DAC Volume Control The digital volume can be set from -71.25dB to +24dB in 0.375dB steps with the DAC0_VOL bits. The channel can be placed into digital mute by setting the DAC0_MUTE bit high. The channel can also be muted by setting the digital volume control (DAC0_VOL) to the lowest setting (code 0xFF). By default, fine-step volume ramping based on zero cross -detection is used for all digital volume changes. Volume change zero cross detection can be disabled with the DAC_VOL_ZC bit, and when disabled each volume step occurs without regard to si gnal level at 4.5dB/ms. Volume ramping can be bypassed entirely to allow for instantaneous (hard) single-step volume changes by setting the DAC_ HARD_VOL bit. When the channel is enabled, it powers up at the volume set by the DAC0_VOL bits. When disabled, it powers down immediately without ramping down the volume. Output Channel DAC Power Modes Three power mode options trade off varying degrees of performance with power consumption. The DAC power mode bits (DAC_PWR_MODE) can be set to normal, low-power saving, and high-power saving modes. The low -power modes offer a similar level of performance at reduced power, however, the lowest -power mode increases channel latency by about 1µs. The DAC can also be placed into a high -performance mode by setting the DAC_PERF_MODE bit high. In this mode, THD+N is improved at high signal amplitudes at the cost of slightly increased power consumption. The DAC bias current can be adjusted with the DAC_IBIAS bits and can be set to normal operation, power saving, or enhanced-performance modes. The lower power settings result in slightly increased distortion. Output Channel Class-D Amplifier The device features a Sigma-Delta Pulse Density Modulation differential Class-D amplifier with very low output noise and distortion. The amplifier has very low quiescent power, enabling very high active power efficiency over the full output power range. The differential headphone amplifier output (HPOUTP and HPOUTN) can drive a minimum load of 6Ω. The common mode stable output does not typically require any output filter to directly drive the speaker load, saving board space and reducing component count. In addition, the modulation scheme reduces the amplitude of spectral components at high frequencies, reducing EMI emissions that can otherwise be radiated by speakers and cable traces. Class-D Amplifier Operation The Class-D amplifier is automatically enabled when the analog output channel is enabled with the PB0_EN bit. The amplifier does not provide any direct analog gain or an analog mute control. The overall volume (or gain) of the analog output channel should be set with the digital volume control (DAC0_VOL) and if output mute is needed the digital mute control must be used (DAC0_MUTE). The differential load between HPOUTP and HPOUTN must exceed the specified minimum load resistance and inductance to ensure that power and performance specifications are met. To optimize the amplifier output power stage performance, the output resistive load bits (HP_RLOAD) should be set to the c losest matching value to the attached load resistance. The amplifier defaults to high-performance mode but can be placed in low-power mode by setting HP_LPM = 1. This reduces the Class-D modulator power consumption at the expense of increased THD+N and output noise.

analog.com Rev. 0 54 of 86 Class-D Amplifier Pop-and-Click Suppression The analog output channel and amplifier architecture provides advanced pop-and-click suppression that minimizes any potentially audible transients during channel power -up (activation) and power -down (deactivation). To minimize pop-and-click, the proper sequencing should be followed. Before the amplifier output power up, the audio clocks should be active and stable, and the input data should either be silent (zero code) or the channel should be muted (DAC0_MUTE). Once the power -up sequence is complete, the channel can be unmuted and playback can begin. If the internal digital volume control is used for soft ramping, then the channel should be unmuted once audio data is present. Alternatively, if the host is ramping up the audio data, then the channel can be unmuted first before sending ramped audio data. Before power-down, the input data to the channel should be muted (for soft ramp -down) or ramped down by the host to silent input data. The audio clocks must not be disabled until the power -down sequence is completed. Changing any output channel settings (outside of volume and mute) while playback is active may result in audible transients. These changes should only occur when the channel is either muted or powered down (disabled). Class-D Amplifier EMI Management The amplifier uses a proprietary common -mode stable output switching, modulation, and spread -spectrum technology to minimize EMI emissions. This results in lower emission levels than other filterless Class -D topologies. The distance from the amplifier outputs to the speaker load impacts the radiated emissions from the board and/or cables. For some applications with longer trace or cable lengths, a small ferrite bead filter may be required for EMC compliance. Typically for trace or cable lengths less than 4" no extra filter components are needed. For additional EMI emissions reduction, the device provides a Class-D output slew rate control (HP_EDGE) that when set, places the outputs into low EMI mode. This mode significantly reduces the output radiated emissions (particularly above 30MHz) at the expense of reduced output power efficiency. If an output filter is required (or for extended trace lengths), amplifier output feedback connections (FB_HPOUTP and FB_HPOUTN) should be connected post-filter to correct for any non-linearities of the filtering components. If no filter is used, they can either be connected directly to the appropriate headphone output pins (HPOUTP and HPOUTN) or to a point in the trace or wiring that is closer to the speaker load. Class-D Amplifier Fault Protection The analog output headphone amplifier includes fault detection, protection, and status reporting for amplifier over current (short circuit) and over -temperature faults. Headphone amplifier output over current protection is enabled by default but can be disabled by setting HP_OCP_EN = 0 (not recommended). Output over current protection can detect an output short to GND or supply (which reports the status and disables the analog output channel amplifier). However, if HPOUTP and HPOUTN are shorted together, there can be instances where the overcurrent protection is not triggered resulting in significant HPVDD current. If it is necessary to protect against an output short, then system-level protection is recommended. Both over -current and over -temperature faults are by default set to auto -recovery mode. In auto mode, the headphone amplifier automatically attempts to recover and re-enable after being shut down during a fault event. To place over -current and over -temperature protection in to the manual -recovery mode, set the HP_ARCV_SC and HP_ARCV_OT bits high (respectively). In manual mode, after a fault occurs and is detected (with the status bits and/or interrupts), the amplifier output is disabled and requires driver action to re-enable it. To manually attempt to restart the amplifier, the system software can either toggle the playback enable bit (set PB0_EN to disabled, then back to enabled) or switch the device into auto mode (until recovery occurs, then it can be placed back into manual mode).

analog.com Rev. 0 55 of 86 PDM Output Channels The device provides two low latency, high -performance 1-bit PDM output channels suitable for driving an external amplifier or data to a peripheral device. The outputs are enabled with the corresponding PDMx_EN bits. The two PDM output channels share a single output clock and data interface. PDM channel 0 data is clocked on rising edges, and PDM channel 1 data is clocked on falling edges. The shared PDM clock and data outputs can each be individually routed to one or more multipurpose pins (MP0 to MP31) with the respective MPx_MODE bits. PDM Output Channel Full-Scale Level Full-scale input data (corresponding to a 0dBFS input code with 0dB of digital volume) results in full -scale output PDM data. The performance of the PDM modulator is degraded for PDM output amplitudes greater than -7.5dBFS. PDM Output Channel Configuration The PDM output channels can accept audio data from other blocks at a range of input sampling rates from 12kHz to 768kHz. The input data sample rate for both channels is selected with the PDM_FS bits, and the internal audio data routed to each channel must be configured to the same sample rate. The input data source for each PDM output channel is selected with the respective PDMx_ROUTE bits. The PDM output channel modulators can operate at sample rates of 3.072MHz, 6.144MHz, or 12.2888MHz. The PDM data sample rate is always equal to the PDM output clock frequency and is selected with the PDM_RATE bits. The input signal to the PDM channels can be inverted with the respective PDMx_INVERT bits. Both high-order (higher delay) and low -order (reduced delay) input interpolation filters are provided, and this is selected with the PDM_MORE_FILT bit. To remove DC offsets digital high -pass filters are available for each PDM channel and can be enabled with the respective PDMx_HPF_EN bits. The cutoff frequency can be set from 0.25Hz to 241Hz and is selected with the DAC_HPF_FC bits. Optional compensation filters for the high -frequency roll-off of the channels are enabled with the PDM_FCOMP bit. Disabling the compensation filters (default) provides the lowest propagation delay but results in a slight signal attenuation in the passband at higher frequencies. PDM Output Channel Digital Volume Control The digital volume of each channel can be set individually from -71.25dB to +24dB in 0.375dB steps with the appropriate PDMx_VOL bits. Each channel can be placed into digital mute by setting the respective PDM0_MUTE bit high. They can also be muted by setting the digital volume control (PDMx_VOL) to the lowest setting (code 0xFF). By default, fine-step volume ramping based on zero cross -detection is used for all digital volume changes. Volume change zero cross detection can be disabled with the PDM_VOL_ZC bit, and when disabled each volume step occurs without regard to signal level at 4.5dB/ms. Volume ramping can be bypassed entirely to allow for instantaneous (hard) single-step volume changes by setting the PDM_ HARD_VOL bit. By default, volume control is independent for each PDM output channel. If the PDM_VOL_LINK bit is set, the digital volume level and any changes for both channels are linked to the PDM output channel 0 volume settings (PDM0_VOL). When a channel is enabled, it powers up at the volume set by the respective PDMx_VOL bits. When disabled, it powers down immediately without ramping down the volume.

analog.com Rev. 0 56 of 86 Interpolation and Decimation Filters In addition to the decimation and interpolation filters that are attached to specific channels, the device provides an additional standalone set of eight decimation filters and eight interpolation filters. These filters can accept output data routed from and provide input data to most internal audio subsystem blocks. The eight decimation filter channels convert higher sample rate input data (fast) to lower sample rate output data (slow) and can each be enabled individually with the FDECx_EN bits. The input data source is selected individually for each channel and is routed with the corresponding FDECx_ROUTE bits. The input and output sample rate settings for the eight decimation channels are grouped in pairs (channel pairs 0/1, 2/3, 4/5, and 7/8). The input and output sample rate for each pair is set with the respective FDECxx_IN_FS bits (input) and FDECxx_OUT_FS bits (output). The selected input sample rate must be higher than the output sample rate. The eight interpolation filter channels convert lower sample rate input data (slow) to higher sample rate output data (fast) and are each enabled individually with the FINTx_EN bits. The input data source is selected individually for each channel and is routed with the corresponding FINTx_ROUTE bits. The input and output sample rate settings for the eight interpolation channels are grouped in pairs (channel pairs 0/1, 2/3, 4/5, and 7/8). The input sample rate for each pair is set with the respective FINTxx_IN_FS bits and the output sample rate is set with the re spective FINTxx_OUT_FS bits. The selected input sample rate must be higher than the output sample rate. The interpolation and decimation filter channels support input and output sample rate settings ranging from 8kHz to 768kHz, however, only input-to-output sample rate ratios that do not have a fractional component are supported. For example, a decimation filter with an input sample rate of 16kHz and an output sample rate of 24kHz is not supported since the ratio (24kHz/16kHz) has a fractional component. Asynchronous Sample Rate Converters The device provides two full-duplex (input and output) asynchronous sample rate converters (ASRCs) that can each be paired with either of the two serial audio data ports. Each ASRC (ASRC 0 and ASRC 1) provides four dig ital input and four digital output channels (for a total of eight digital input and eight digital output ASRC channels). Each ASRC input and output channel is individually enabled. For ASRC 0 the output channels are enabled with the ASRCO0_x_EN bits and t he input channels are enabled with the ASRCI1_x_EN bits. For ASRC 1 the output channels are enabled with the ASRCO1_x_EN bits and the input channels are enabled with the ASRCI1_x_EN bits. ASRC Configuration The ASRCs convert input and output audio data to or from the sample rate of the paired serial audio data port to or from the selected internal synchronous audio data sample rate. The serial port paired with each of the two ASRCs is selected with the ASRCOx_SAI_SEL and ASRCIx_SOURCE bits for the output and input channels respectively. When paired with the ASRCs, the serial audio data ports can support external asynchronous input and output audio data at sample rates from 7kHz to 224kHz. All intermediate frequencies and clock ratios are supported. For v oice bandwidth external sample rates (typically nominal sample rates from 8kHz to 32kHz), additional low pass filtering can be enabled with the ASRCIx_VFILT (for input channels) and ASRCOx_VFILT (for output channels) bits. For each ASRC, the sample rate for the input and output channels is individually selected from a discrete set of values ranging from 8kHz to 192khz. The internal sample rate accepted (ASRCOx input rate) by the four output channels is linked and is set for the four output channels with the ASRCOx_IN_FS bits. The sample rate provided (ASRCIx output rate) by the four input channels is also linked and is set with the ASRCIx_OUT_FS bits.

as interrupt sources for the two interrupt controllers. respective ASRCIx_x_ROUTE bits. configured to the same sample rate as the ASRC output channel. output channels, they are enabled with the ASRCOx_LPM (low power) and ASRCOx_LPM_II (lowest power) bits. Table 13. Input ASRC Power and Performance Options for 44.1kHz to 48kHz Conversion Table 14. Output ASRC Power and Performance Options for 48kHz to 44.1kHz Conversion

analog.com Rev. 0 58 of 86 Boot Loader The device employs a boot loader for loading an app pack into system memory. This boot loader is used both in self- boot mode and host-boot mode. To access the HiFi 3z memory, FDSP memory, or Main Map registers, the boot loader needs to be enabled. This is true even if an app pack is not present in the system memory. Boot Loader in Host-Boot Mode In host-boot mode (SELFBOOT pin = GND), an application pack can be written externally via I 2C or SPI into the L2 memory. Once the memory is configured, t he PROC_EN bit must be asserted. This enables the boot loader, which then in turn enables the HiFi 3z core. If the application pack is not successfully loaded or the L2 memory is left blank, then the PROC_EN bit must still be asserted to enable the boot loader. Once the boot loader has been enabled, access to the memories and main control registers is open. When operating in host-boot mode, make sure to perform the following steps before writing to the L2 memory:  Assert DVDD_EN  Set all clock configuration registers  Update and enable the PLL  Assert MASTER_BLOCK_EN Once these steps are completed, write the app pack to the L2 memory and then assert PROC_EN. If nothing is written to the L2 memory, PROC_EN still needs to be asserted to gain access to memories and main control registers. Boot Loader in Self-Boot Mode In self-boot mode (SELFBOOT pin = VIOVDD), an application pack can be loaded via external QSPI Flash. If the self-boot is unsuccessful or the external flash is empty, the boot l oader is enabled during the attempted self - boot. As a result, access to the memories and main control registers is open. In self-boot mode, the internal DVDD defaults to a value of 1.1V. The boot loader needs 1.1V to attempt the boot and enable the HiFi 3z core. Once the boot loader has finished the attempted boot, then DVDD can be switched to 0.9V. Likewise, if using an external DVDD in self-boot mode, the DVDD voltage provided must be 1.1V. In self-boot mode, the default clock configuration values assume an MCLK frequency of 24.576MHz. Hence the MCLK must be 24.576MHz during the attempted boot. Once the boot loader is finished, the MCLK frequency can be changed and the clock configuration register can be set with new values.

instructions that can be run in each frame (Table 15). Interpolators, ADMA, AMAP, HiFi 3z TIE, serial audio data ports, and ASRC inputs. adjustment between any instruction or block. (FDSP_EN = 1) and set to run (FDSP_RUN = 1). maximum number of FastDSP instructions per frame based on the selected configuration is shown in Table 15. Table 15. Maximum FastDSP Instructions per Frame audio output DMA channel, or any other FastDSP instruction output (routed through a data or accumulator register).

analog.com Rev. 0 60 of 86 FastDSP Data Channels and Memory The FastDSP core internal data channels are 28-bits (5.23 format), and provide sufficient headroom for up to 24dBFS of signal swing before clipping occurs. All input sources to and output channels from the FastDSP are limited to 24 bits (1.23 format). The FastDSP provides 16 output channels each of which is truncat ed to 24 bits. If any output channel data exceeds full scale, it clips symmetrically to 0dBFS. The FastDSP provides output clip detectors on each channel that can be read as status bits or used as an IRQ source. FastDSP Supported Instructions The function of each instruction is individually configured, and a complete list of supported instructions is provided in the SigmaStudio+ software. The available instructions include the following:  Single precision (27-bit fractional precision) biquad/second-order filters  Double precision (54-bit fractional precision) biquad/second-order filters  Lower precision (19-bit fractional precision) biquad/second-order filters  Limiter with/without external detector loop or side chain input  Expander with/without external detector loop or side chain input  Ramped volume slider  Mute function  Sample-based time delay function  Two input multiply function  Linear gain function  Two to four input weighted mixer  Two to four input addition  Symmetrical clipper  Absolute value function  Two input min and max value functions  Bit shift function  Bitwise and, or, xor, and invert functions  Memory read or write  Input to output equivalence function  T connection for signal routing in SigmaStudio+ FastDSP Conditional Execution Each instruction can be set to either always ex ecute, or to only execute conditionally based on a specific flag result or upon certain state conditions. When an instruction does not execute (based on a condition), it can be set to either do nothing or pass its input to its output. Each instruction can generate flags for conditional execution that are based on the output of that instruction. Instruction output flag set conditions include the following:  Output equals zero  Output is not equal to zero  Output is greater than zero  Output is less than zero  Output is greater than or equal to zero  Output is less than or equal to zero  Accumulator overflow

analog.com Rev. 0 61 of 86 Each instruction can also conditionally execute based on the current value of certain state conditions. Instruction conditional execution states include the following: The logic state of any multipurpose pin (MP0 to MP31) when used as a GPIO input (for a given MPxx input when configured with the corresponding MPxx_MODE bits set to 0x01). In addition, the state of any multipurpose pin configured as a GPIO output (MPxx_MODE bits set to 0x02) can be set in with the GPIOxx_OUT bits. The state of the FastDSP generic conditional execution register bits (FDSP_REG_COND0 to FDSP_REG_COND7). Each of these bits is read/write, and to control FastDSP execution they can be co nfigured with the control interfaces (I 2C or SPI) or directly by the HiFi 3z DSP. The Modulo N counter equals zero. The Modulo N counter increments once for every FastDSP frame. The counter is reset to 0 after the number of frames completed is equal to the setting of the FDSP_MOD_N bit. Conditional instructions can then execute every N frame (as set by the FDSP_MOD_N bit), and this results in these instructions running at a lower rate than the configured FastDSP core frame rate. FastDSP Filter Precision FastDSP core instructions can be configured as biquad filters and second -order filters with a selectable level of fractional precision. These filters can be either single precision (27-bit), double precision (54-bit), or lower precision (19-bit), where using reduced fractional precision results in lower power consumption. However, care must be taken to ensure that filters have enough precision to maintain stability and create the desired filter response. FastDSP Parameters Each FastDSP instruction (up to a maximum of 128 instructions) has 5 associated parameters (for a maximum total of 640 parameters in a single bank). Each parameter is stored in memory as a 32 -bit number, and the format of a parameter depends upon the associated instruction. Parameters contain instruction configuration information such as filter coefficients, limiter threshold and ballistic settings, and volume control settings. For example, the 5 parameters for a biquad filter instruction contain the biquad filter coefficients (B0, B1, B2, A1, A2) in a 5.27 format. Reference the SigmaStudio+ software for the full list of supported instructions and the associated configuration settings and parameters for each. When instantiating FastDSP instructions with the SigmaStudio+ software, the assembler automatically maps the instruction configuration settings to the associated parameters in memory. Individual sets of 5 parameters in the parameter memory space are sequentially assigned to instructions in the order in which they are instantiated in the FastDSP code. FastDSP Parameter Bank Switching The FastDSP provides three separate banks of parameters designated as parameter bank A, bank B, and bank C. Each FastDSP parameter bank supports a maximum total of 128 instructions (each of which has 5 parameters for a total of 640 parameters per bank). The three banks each support the same single set of instructions but allow for instruction parameters such as filter coefficients, settings, and variables to easily be switched between for different use cases and processing scenarios. At any given time, the FastDSP actively uses only one of the three -parameter banks. The FastDSP can be switched between Bank A, Bank B, and Bank C on the fly while the core is running. The active parameter bank for the FastDSP is selected with the FDSP_BANK_SEL bits. Instruction parameters in the inactive banks can be updated at any time, however, audible glitches may occur if parameters in the active bank are directly updated while the core is running. Parameters in the active bank can only be safely updated with a FastDSP safeload.

analog.com Rev. 0 62 of 86 The bank change transition method is determined by the FDSP_RAMP_MODE bit setting. When the active parameter bank is changed (with the FDSP_BANK_SEL bits), the parameter values used for instruction processing can either be instantly changed at the start of the next frame or they can be ramped via linear interpolation between the previously selected bank and the new selected bank. When the linear ramp mode is selected, the rate at which the ramp between the two banks occurs is selectable via the FDSP_RAMP_RATE bits. Only the parameters associated with the three biquad filter instructions are ramped. All other parameters associated with other in structions change at the beginning of the frame where the bank switch occurs and ramping begins, and parameters in banks that are actively ramping do not change during a bank switch. The FDSP_ZERO_STATE bit can be set to clear the state of the FASTDSP memory during a bank switch. During a bank switch, this prevents the new filter settings (of the new bank) from using old data (from the previous bank) that can be recirculating in the filters and may prevent potential filter instability or audible glitches. It is possible to stop the linear ramp of biquad filter parameters between the values in the previous and the values in the current target bank. The 6 -bit FDSP_LAMBDA setting selects the point along the linear interpolation curve between the two banks at which the bank switch ramp pauses (with 0 being the beginning and 63 being the end of the ramp). To complete a bank switch without pausing set a value of 63 (default), and to pause midway set a value of 31. The lambda value can be updated actively with th e control interfaces, however once a ramped bank switch is in progress it can only be increased. The progress of the current active ramp (from 0 to 63) can be read at any time with the FDSP_CURRENT_LAMBDA bits. When this value reaches 63, the bank switch i s complete, and all current parameters in use match those of the target bank. Parameters in the two banks being ramped between cannot be modified while a ramped bank switch is occurring. An interrupt for either interrupt controller can be triggered via th e IRQx_PRAMP interrupt source bits. This triggers on the first frame when a ramped bank switch is active and FDSP_CURRENT_LAMBDA equals FDSP_LAMBDA. FastDSP Parameter Bank Copying The instruction parameters of any given bank (source) can be copied to any other bank (target) with a single-bit write command. There are six FDSP_COPY_xy bits (where x is the source bank and y is the target bank), one for each of the six possible bank copy operations. Writing a 1 to one of these bits initiates a bank copy. Once initiated, the bank copy operation waits until the start of the next FastDSP frame and then copies the parameter content of the source bank to the destination bank while the instructions are executed. The bank copy completes at the start of the subsequent frame and takes at most two frames to complete from the initiation. Copying to the active bank (copy target) is not permitted and results in no action being taken. FastDSP Parameter Memory Access If the FastDSP core is enabled but not run ning, then reads from any parameter memory bank through the I 2C interface, SPI interface, or HiFi 3z DSP are unrestricted. However, when the core is enabled and running, only reads from the inactive parameter banks are unrestricted. While the FastDSP core is running, if multiple sources try to read the same memory location on the same cycle, the HiFi 3z DSP has priority over the I 2C and SPI interfaces, and the read attempt from the I 2C interface or the SPI interface returns all 0s. Direct reads from the mem ory of the active bank by any source (I2C interface, SPI interface, HiFI 3z DSP, or mREAD instructions) are not allowed and return 0s. Similarly, writes to all parameter banks are possible when the FastDSP core is enabled but not running, and are still permitted to inactive banks while the FastDSP is running. While the core is running, if multiple sources try to write to the same location on the same cycle, the HiFi 3z DSP has priority and the other writes do not occur.

Table 16. Memory Addressing for FastDSP Core same time at the beginning of the next frame. least one instruction must be unused (out of the maximum support instructions for a given use case, see Table 15). allows the HiFi 3z DSP to have word-addressable access.

audio enhancement software packages. www.analog.com/SigmaStudio+. Figure 56. LX7/HiFi 3z IO, Bus, and Memory Structure

analog.com Rev. 0 65 of 86 Clock Speed Control By default, HIFI_SPEED is set to 0, the HiFi 3z DSP receives a 49.152MHz clock, and a DVDD nominally of 0.9V is applied. If the PLL is used and is set to 1 then a nominal DVDD of 1.1V must be used, the HiFi 3z DSP core receives a 196.608MHz clock and can run four times as many instructions. If the extra processing power is not needed, then operating with HIFI_SPEED = 0 reduces overall power consumption. HIFI_SPEED can be changed during operation, but if this is done then the PLL must always be operating wi th a 196.608 MHz output. PLL_BYPASS cannot be selected if HIFI_SPEED is changed while the part is operating. Interrupts The HiFi core has several internal core interrupts.  Three timer interrupts  Bus write error  Profiling interrupt  5 Software interrupts (1 at each priority level)  Non-Maskable Interrupt (NMI) In addition to the core interrupts, there are three additional external interrupt types comprising a total of 20 external interrupts. Nine system interrupts aggregate interrupts from various syst em events and peripherals. The system interrupt controller can individually mask each interrupt source to every system interrupt. System interrupts can interrupt the core and/or also signal an interrupt on an MP pin. MP interrupt controls are described in the Multipurpose Pins as Interrupt Outputs section. The interrupt sources for system interrupts include.  QSPI port and its Rx and Tx DDEs  UART Rx and Tx DDEs  Audio DMA engine, which has separate internal interrupt sources.  FastDSP memory read and write access errors  Memory copy read and write DMA/DDEs  Watchdog counter  Power-up complete signal (only useful for pin interrupts)  PLL locking and unlocking  Headphone amplifier protections and faults  AVDD undervoltage detection  ASRCs locking and unlocking  ADC, DAC, and FastDSP output clipping detection  Generic HiFi interrupts that the core can set through registers to aggregate interrupts from the core and other sources to an MP pin interrupt. Which interrupt source triggered each system interrupt can be determined by the IRQx_STATUS registers in the READ_ONLY register map. All sources of each interrupt are cleared via a write of 1 to the IRQx_CLEAR bits. The interrupt status bits are sticky, such that if an interrupt source becomes true, the status reads 1 until a clear occurs, even if that interrupt source is no longer true. Pin interrupts can either be edge or level -sensitive, there are three of each type. Each pin interrupt can map any single pin to its source. The routing of the pins to the interrupt source is set via the HIFI_EDGE_IRQx_SRC and HIFI_LEVEL_IRQx_SRC registers. Each of these interrupt pin sources can also be inverted if desired.

analog.com Rev. 0 66 of 86 Audio interrupts are generated by the various audio source peripherals when a new sample is ready. Each audio interrupt can map to any single audio source via its HIFI_AUD_IRQx_SRC setting. Additionally, these can be set to block mode by setting HIFI_AUD_IRQx_TYPE to 1 to inte rrupt after a number of samples determined by HIFI_AUD_IRQx_CNTR are received. If HIFI_AUD_IRQx_TYPE is set to 0 and counter is selected as the source then an interrupt occurs every number of 24.576MHz (40.69ns) clock cycles determined by the HIFI_AUD_IRQx _CNTR, effectively acting as a timer interrupt. Audio DMA The three audio DMA blocks support moving up to 8-channels of audio into and out of the processor memory space. The audio data is stored and retrieved as interleaved data. The DMA block supports a read and a write circular buffer pointer. The circular buffer pointer consists of an index -, start-, and end -address. The index address always points to the start of the current sample. The start - and end - address are the beginning and end of the circular buffer. For non -circular buffer mode, the end address is set to 0 [default]. All addresses are byte addresses. Each DMA supports up to 8 -channels. The channels are configured independently, such that we have up to 8 input channels and up to 8 out put channels. The channel enable configuration is a simple 7 -bit value. Which audio peripheral source channels are routed into the Audio DMA are selectable via routing registers. Outputs from the Audio DMA to Audio sink peripherals are selected through the peripherals routing controls. The actual number of channels copied in, and out, is configured in a channel count register. This register defines the stride the DMA uses when moving through its circular buffer. The channel count is limited to a power of 2 numbers, such that 1, 2, 4, or 8 channels can be selected. The format of the data can be configured as 32 -bit, 24-bit, 24-bit packed, 16-bit packed, floating, and raw formats. This format is configured independently in the input and output direction. The DMA initiates when an Fs pulse is seen from the selected audio source. The DMA copies data from the audio source towards the DSP first and issues a done when this task is completed, followed by copying data from the DSP memory towards the audio peripherals. Because of this behavior using the DMA introduces an extra sample of latency compared to the time domain path.

can also be read over the system bus. sources need to select “System Bus” in their routing controls as their input to enable this. A JTAG interface port is included for ease of development and debugging. of the FastDSP. Table 17 lists the HiFi 3z DSP assembler names for the functions used for safeload. Table 17. HiFi 3z DSP Safeload to the FastDSP Current Bank executes, without needing to write a trigger bit.

analog.com Rev. 0 68 of 86 Audio Data Handling The device has two subsystems for processing audio data —a low -latency audio subsystem and a processor subsystem. The device relies on the effici ent movement of audio samples within and between these subsystems to enable processing and building applications. The Low -Latency Subsystem is centered on the FDSP and an audio fabric that sends individual samples between blocks with minimal latency. The processor subsystem supports applications run on the HiFi 3z processor where blocks of samples are located in system memories and/or where individual samples can be inserted or pulled directly from the audio fabric. Low-Latency Audio Subsystem Within the audio subsystem, the functional blocks that act as sources broadcast their audio samples. The functional blocks that are syncs select from the available sources and match the source’s frame rate. This system facilitates the construction of chains of blo cks moving data between inputs, through the FDSP for filtering and mixing, and to output interfaces, potentially utilizing sample rate converters between major blocks. From the audio subsystem perspective, the connections to the processor subsystem function the same as any other source or sync by providing or consuming individual samples at their selected frame rate. Processor Subsystem The applications running on the HiFi 3z access audio data from either blocks of samples storied in memories, memory-mapped sample FIFOs, or specialty processor instructions that read and write sample registers directly attached to the audio subsystem routing matrix. Processing of the data is triggered by interrupts from the audio subsystem based on when data is available or n eeded. The choice of access method is driven by application needs for sample granularity and latency requirements. Data Movement Between Subsystems  With the Audio DMA’s ability to source and sync up to 8 channels on 3 separate engines and access system memories, blocks of data can be stored in memories with limited supervision of the processor. These blocks can comprise interleaved or contiguous blocks connected to a single engine. The engines are independent, so they can vary the sample rate, data organization, and block sizes. This is an ideal choice for applications that process data in blocks. It reduces processor overhead, particularly in the number of interrupts required to send a receive data.  The Direct IO (TIE) gives the most granular access to audio samples by utilizing processor instructions to give direct access to sample registers within the Audio subsystem. At any point, the processor can set a source register or read the most recent sample generated by any other source. Sample rate sy nchronization is handled by configuring interrupts to trigger based on an audio component’s sample rate or a multiple of the sample rate. The Direct IO is targeted to applications that require the lowest latency and those that require working on individual samples. Using the direct IO for high sample rates or multiple sample rates incurs a larger interrupt latency penalty and therefore must be balanced with the ease of use and sample access latency.  The Audio Bus Map is indented as a middle ground between the other two access methods. A set of 16 input and output FIFOs act as sources and syncs in the audio subsystem. The Audio Bus Map will collect or transmit multiple samples and multiple samples can be pushed or popped within a single sample period. By having the FIFOs mapped to system memory, the method of writing and reading is simple. The application can either use interrupts generated by the audio bus map FIFO status or use the sample interrupts. The Audio Bus Map should be considered by applications that are interested in small numbers of samples from a given source with some latency tolerance or potentially an application interested in multi -rate processing where the latency of the lower rate is strict and the higher rate can be stored in the FIFO.

analog.com Rev. 0 69 of 86 Example—Simple ANC with Bluetooth Playback In this example system, the inputs to the audio subsystem are feedforward and feedback microphones generating 192khz samples and 44.1kHz serial audio data from a Bluetooth SoC (BT). The serial audio data is then sent to the ASRC which up-samples and synchronously outputs a 192kHz stream. These three sources are then used by the FDSP to generate anti-noise and mix in the BT. The output of the FDSP is then routed to the DAC. At this point, an additional path c an utilize the existing sample streams for applications running on the processor subsystem. In this case, there could be two independent threads running on the processor that need access to data from the audio subsystem. The first thread would conduct scene detection by taking individual samples from the FF mic and comparing the BT audio to what is seen at the FB mic. Utilizing a HIFI_INT_CTRL0 to select the ADC and HIFI_INT_CTRL3 to select every nth sample to generate processor interrupts, the corresponding thread could read the current ADC value, converted to floating point format, via the DirectIO instruction in the HiFi core. The second thread would select the output of the ASRC and FDSP, using them as inputs to an FDEC pair down - sampling both to 48kHz. The output of the FDEC is then used as the source for the ADMA that stores the set of samples in System memory in a 1.31 format. The ADMA then generates interrupts based on the programmed block size. Distributed DMA Engines (DDE) The device uses severa l distributed DMA engines to automate copying between memories and between the UART, QSPI, and I3C interfaces and memory. The processor uses Direct Memory Access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processor can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of processor activity. The DMA controllers are dispersed throughout the infrastructure, as Distributed DMA Engines (DDE) and connected to the AXI Fabric. The DDEs can perform transfers between a memory and a peripheral or between one memory and another memory. Two DDEs are used for Memory to Memory DMA (MemDMA). One channel is the source channel, and the second is the destination channel. The CONFIG register is used to set up DMA parameters and operation modes. Writing CONFIG while DMA is already running causes a DMA error, except for when the EN bit is being written to 0. Additional documentation on the DDEs can be found in the respective DDE register description section.

software running on the HiFi 3z Core. Table 18 provides an overview of each supported interface port. Table 18. Supported Control and Data Interface Ports by default operate as slave mode interfaces. Both slave interfaces require an external clock source from the host. running on the HiFi 3z core. A secondary I2C master interface can also be implemented using the I3C interface. shared control port pin functions based on the selected control interface operating mode. Table 19. Multifunction Pin Operation by Control Interface Mode and bits marked as reserved in the register map/programming guide always read back as 0.

single word write unless the transaction is stopped (with a stop condition for I 2C, or with SS brought high for SPI). knows the mapping between sub-addresses and the word length of the destination register or memory location. loading a new program into memory. Table 20. I2C/SPI Control Data Word Sizes and Address Ranges

lowest memory address, however, all 4 bytes of a data word need not be read before ending the transaction. single-byte mode if the write and read requirements are met. capacitances the SDA_MISO_DRIVE bit must be set to 1 to support these operating speeds. bit I2C addresses are shown in Table 21. Table 21. Device I2C Interface Address Selection terminated by a stop condition. Table 22. Device I2C Interface Address Format pins. The pull-up voltage on these signal lines cannot be higher than VIOVDD.

 Sr is the repeated start bit. Figure 57. Single-Word I2C Write Format Figure 58. Burst Mode I2C Write Format Figure 59. Single-Word I2C Read Format

0 A P1S

Figure 60. Burst Mode I2C Read Format mode, the SS pin must be pulled low three times by issuing three SPI writes (which are in turn ignored by the device). The SPI slave interface is then active, and the device is ready to respond to the next SPI transaction (fourth). read operation is requested, allowing other SPI-compatible peripherals to share the same MISO readback bus. control mode by pulling the PD pin low (hardware power down) or by powering down the supplies.

least 10 bytes in length. A timing diagram for SPI transactions is also illustrated in Figure 5. a logic level 1 setting a read transaction and a logic level 0 setting a write transaction. effectively extends the sub-address to 40 bits, with the actual sub-address being placed in the 32 MSBs. a read transaction data bytes are transmitted on the MISO line (which is tristated before and after data transmission). The transaction (single or burst mode) is ended when the master pulls the SS line high. Table 23. Generic SPI Interface Transaction Format Figure 61. SPI Write Format (Single-Write Mode)

Figure 62. SPI Read Format (Single-Read Mode) shared pins restrict the device to either an I2C or an SPI interface configured to either master or slave mode). transfers must be configured to match the address length and word length of the target slave device. specification (refer to this documentation for additional details). legacy slave devices. All data rates are supported except for the I3C HDR ternary options. Table 24. Supported I2C/I3C Modes

analog.com Rev. 0 77 of 86 Quad SPI (QSPI) Master Control Interface Port The device contains a QSPI master control interface port that is capable of single, dual, or quad data line communication. This port is also used to configure the device from an external memory when in self-boot mode. The QSPI port can either operate in legacy mode where access and control of the port are through a software driver running on the HiFi 3z core or in memory -mapped mode where the access is automated and external memory can be directly accessed by the host. The host interface contains support f or pre-fetch and catching. The QSPI control interface port also has a dedicated DMA channel to automate transfers of data from the port to processor memory. QSPI Self-Boot Mode Configuration During initial power-up, the device can either be directly co nfigured by the system host through the I 2C or SPI slave interfaces (referred to as host -boot mode) or it can automatically load the configuration from an EEPROM or Flash through the QSPI master interface (called self -boot mode). The boot mode is selected based on the state of the SELFBOOT input pin, and this is checked internally when the device comes out of reset (exits the hardware full chip power-down state when the supplies are powered up and the PD pin is asserted high). If the SELFB OOT input pin is asserted to logic low state then the host-boot mode is selected, while a logic-high state selects self-boot mode. To place the device into self -boot mode during the initial power -up, the SELFBOOT pin must be asserted to a logic high level either concurrently with or before both the PD input pin being asserted high and all supplies being powered up. Likewise, for host-boot mode, the SELFBOOT pin should instead be asserted to a logic -low level. If the use case does not require the SELFBOOT pin to be reconfigured to a multipurpose pin function (MP31 function), the pin can be tied to either IOVDD (for self-boot mode) or DGND (for host-boot mode) through a resistor (typically 10kΩ). Once the device powers up into self-boot mode an external master clock (MCLK) source must be present to proceed. The default clock settings are configured to accept a master clock frequency of 24.576MHz. If a master clock signal of the correct frequency is not provided, the self-boot operation cannot start (or continue). Once the self-boot operation begins loading the settings, DVDD must remain stable and within its normal operating range (whether it is internally generated or externally provided). The PD input pin must also remai n stable and asserted high and the external master clock signal cannot be removed during the self-boot operation. QSPI Self-Boot Mode Operation The device's self-boot mode is compatible with an EEPROM or Flash memory that supports a QSPI interface with a 12MHz clock frequency and has a 3-byte address. An example compatible Flash memory (used also on the evaluation board) is the Macronix MX25U3232FM2I02. During self-boot, if an app pack boot image error is detected and no valid image is found, the self -boot is stopped. The HiFi 3z is then released and ready for operation (see the Boot Loader section). The time to self-boot the device from an EEPROM or Flash memory can be estimated based on the size of the program being loaded (at 12MHz), however, there are some fixed delays to account for as well. The self-boot operation starts after a delay of 16,568 input master clock cycles (from when power-up completes if the master clock is present). With the 24.576MHz master clock, this corresponds to a 0.675ms wait time. If the internal regulator is used ( REG_EN is pulled high), then an additional fixed delay of 10ms is added to allow DVDD regulation to come up and settle.

analog.com Rev. 0 78 of 86 Universal Asynchronous Receiver/Transmitter (UART) Data Interface Port The UART data interface port is a full-duplex peripheral compatible with PC-style industry-standard UART interfaces. The UART interface converts data between serial and parallel formats. The serial communication follows an asynchronous protocol that supports various word lengths, stop bits, and parity generation op tions. The UART interface includes interrupt-handling hardware, and interrupts can be generated from multiple events. In addition to a basic UART operation mode, UART4 supports the half -duplex IrDA® (Infrared Data Association) SIR (9.6/115.2 Kbps rate) protocol and full-duplex Multi-Drop Bus (MDB/ICP v2.0) protocol. The UART interface operating mode is selectable. Partial modem status and control functionality are supported by the UART module to allow for hardware flow control. The UARTs are DMA-capable peripherals. The UART interface supports:  5 to 8 data bits  Programmable extra stop bit and programmable extra half stop bit.  Even, odd, and sticky parity bit options  8-stage receive FIFO with programmable threshold interrupt  Flexible transmit and receive interrupt timings  Three interrupt outputs for reception, transmission, and status  Programmable automatic RTS/CTS hardware flow control  False start bit detection The UART interface has dedicated DMA channels with support for separate transmitter and receiver DMA master channels. They can be used in either DMA or programmed non-DMA modes of operation. The non-DMA mode requires software management of the data flow using either interrupts or polling. The DMA method requires minimal software intervention as the DMA engine itself moves the data. The UART interface has separate transmit and receive DMA channels, though they may be mixed with other peripherals at the syste m level. The external peripheral timers can be used to provide a hardware-assisted auto-baud detection mechanism for use with the UART.

transmitted and received in twos complement (MSB first) format. slots (or channels) can be configured to be 16-bit, 24-bit, or 32-bit wide. or slot 0, and the right audio data channel is typically mapped to channel or slot 1. by the external input (slave mode) or configured output (master mode) bit clock to frame sync clock ratio. output) sequentially from slot 0 up to a maximum of slot 15 based on the channel (or slot) width. Table 25. Serial Audio Data Interface Port Supported Data Format Settings trailing padding bits in an input channel do not cause an error, but extra bits beyond this are ignored (truncated off). The serial port can operate with an arbitrary number of bit clock periods in each frame.

(allowing it to be driven by another device sharing the bus), the SPTx_OUT_ROUTEn bits must be set to 0x7F. stated (high-Z). This is configured by setting the SPTx_TRI_STATE bit (disabled by default). Figure 63, Figure 64, and Figure 65 illustrate two channel use cases (I2S, left-justified, and right-justified modes).

0123 N PAD BITS

Figure 63. I2S Mode (1-Bit Clock of Delay, 24-Bit Slot Width, Any Number of Pad Bits Allowed) Figure 64. Left-Justified Mode (No Delay, 24-Bit Slot Width, Any Number of Pad Bits Allowed) Figure 65. Right-Justified Mode (8-/12-/24-Bit Clocks of Delay, 24-Bit Slot Width) Figure 66 illustrates a use case where the interface is in TDM mode with timing for 8 channels (or slots). Figure 66. TDM Mode with 4 Audio Data Channels (No Delay, 16-Bit Slot Width, No Padding)

analog.com Rev. 0 81 of 86 Serial Audio Data Interface Port Clock Configuration For each of the two serial audio data interfaces, the corresponding FSYNC_x and BCLK_x pins are used to clock both the serial audio data input (SDATAI_x) and output (SDATAO_x) pins. Each port can be configured to operate either in master mode or slave mode. In master mode, the output bit clock frequency is selected with the SPTx_BCLK_SRC bits, and the frame sync clock frequency is selected with the SPTx_LRCLK_SRC. If the frame sync clock frequency is set to 8kHz or 16kHz, then the selected bit clock frequency is scaled down by 2/3’s (Example: a bit clock setting of 3.072MHz becomes 2.048MHz). To instead place the device in slave mode, both the bit clock frequency setting (SPTx_BCLK_SRC) and the frame sync clock frequency (SPTx_LRCLK_SRC) should be set to the external source setting (0x0 default setting for both). In this mode, an external device or system host must provide both the bit clock and frame sync clock to the configured serial audio data inte rface. In slave mode, the clocks do not need to be synchronous with the external crystal or master clock input, but the external bit clock and frame sync clock must be synchronous with each other. The input bit clock from either port can also be used as the input clock reference source to the PLL to generate the internal device clocks (instead of a crystal or master clock input). The active edge polarity of both the bit clock and frame sync clock can be inverted with the SPTx_BCLK_POL and SPTx_LRCLK_POL bits respectively. For example, while serial data and the frame sync clock are by default sampled on the rising edge of the bit clock, setting SPTx_BCLK_POL = 1 inverts this to the falling edge of the bit clock. When configured for a high bit clock frequency (12.288MHz or higher) in slave mode (clock is an output), it is recommended to increase the drive strength settings for the high-speed output signal pins (in particular the bit clock output and the data output). The high drive strength effectively speeds up the transition times of the waveforms, thereby improving the signal integrity of the clock and data lines. The timing for serial audio data port outputs also changes based on the IOVDD voltage. While the ports can work for inputting a signal on SDATAI_x for any IOVDD and bit clock rate, the drive strength on SDATAO_x at 1.1V excludes operating at higher bit clock rates.

data or clock output, or a system interrupt output. which must still be followed even if the pin is later reprogrammed to another multipurpose function. to conditionally execute instructions or trigger the compressor. the corresponding GPIOx_OUT bit. multiple pins can be assigned to this same function if required by the use case. multipurpose pin can be used to route the PDM data and clock to an external amplifier or upstream host device. (IRQ1 through IRQ9). This is described in more detail in the Multipurpose Pins as Interrupt Outputs section. significant increase in IOVDD current. Table 26. Multipurpose Pin Functions 1 These functions are selected instead of the pins default function with the MPx_MODE bits.

analog.com Rev. 0 83 of 86 Multipurpose Pins as Interrupt Outputs Each multipurpose pin can be used to output one of the nine system interrupt bus channels (from IRQ1 to IRQ9), and each of these channels can have a different combination of unmasked individual interrupt sources. The output of each system interrupt bus channel can be individually inverted in polarity with the corresponding IRQx_INVERT bit. Refer to the device main register map programming guide for a full list of the individual interrupt sources. Each interrupt source has its own individual status bit (IRQ_x) and a clear bit (IRQ_x_CLR). The status of each interrupt source is read with the corresponding IRQ status bit (IRQ_x). Once an interrupt status bit is set (IRQ_x) it latches and will remain set (even if that interrupt source is no longer asserted/true) until cleared by setting with the corresponding interrupt clear bit (IRQ_x_CLR). Each interrupt source has nine mask bits (IRQn_x_MASK) where n is the system interrupt channel (from IRQ1 to IRQ9) and where x is the individual interrupt source. Each system interrupt channel (IRQn) then represents one combined interrupt signal (comprised of all IRQn unmasked individual interrup t sources) that can be assigned to a multipurpose pin. These system interrupt channels are shared by the cores as interrupt options. Multipurpose Pin Level Control Options Each digital pin that has both a default function and multipurpose functions has a corresponding control register (x_CTRL where x describes the default function, for example, BCLK0_CTRL for the BCLK_0/MP2 pin). The bits within these registers are used to set pin -level parameters such as weak pull -up/down, slew rate, and drive strength . The pin control settings affect the operation in both default function mode and when used in multipurpose pin modes. When a multipurpose pin is used as an output, the drive strength can be set to 2mA, 4mA, 8mA, or 12mA with the corresponding x_DRIVE bits. In addition, when used as an output the slew rate can be set to either fast mode or slow mode with the corresponding x_SLEW bit. If a weak pull -up or pull -down is required for a multipurpose pin (when used as either an input or output), this function is selected with the corresponding x_PULL_SEL bit. The selected pull-up or pull-down function can then be toggled (enabled or disabled) with the corresponding x_PULL_EN bit.

Bypass each analog and digital power supply pin to its nearest appropriate ground pin with a single 0.1μF capacitor. made on the far side of the capacitor. Each supply signal on the board must also be bypassed with a single bulk capacitor (2.2µF). Figure 67. Recommended Power Supply Bypass Capacitor Layout

Figure 68. 77-Ball Wafer Level Chip Scale Package [WLCSP] Table 27. Ordering Guide

ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. analog.com Rev. 0 86 of 86