ADAU1777

ADAU1777 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 108

Technical content

Four-ADC, Two-DAC, Low Power Codec with Audio Processor Data Sheet ADAU1777 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Programmable audio processing engine Fast (up to 768 kHz) and slow processing paths Biquad filters, limiters, volume controls, and mixing Low latency, 24-bit ADCs and DACs 102 dB SNR (through PGA and ADC with A weighted filter) 108 dB combined SNR (through DAC and headphone with A weighted filter) Serial port sampling rate from 8 kHz to 192 kHz 5 μs analog-to-analog latency 4 single-ended analog inputs, configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output, single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital input/output of 1.8 V to 3.3 V Digital signal processing (DSP) core of 1.1 V to 1.8 V Low power I2C and SPI control interfaces, self boot from I2C EEPROM 7 multipurpose (MPx) pins for digital controls and outputs

APPLICATIONS

Noise canceling handsets, headsets, and headphones Bluetooth® active noise canceling (ANC) handsets, headsets, and headphones Personal navigation devices Digital still and video cameras GENERAL DESCRIPTION The ADAU1777 is a codec with four inputs and two outputs that incorporates a digital processing engine to perform filtering, level control, signal level monitoring, and mixing. The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise canceling headsets. With the addition of just a few passive components, a crystal, and an EEPROM for booting, the ADAU1777 provides a complete headset solution. Note that throughout this data sheet, multifunction pins, such as SCL/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. FUNCTIONAL BLOCK DIAGRAM MICROPHONE BIAS GENERATORS MICBIAS0 MICBIAS1 CM DMIC0_1/MP4 DMIC2_3/MP5 DIGITAL MICROPHONE INPUTS INPUT/OUTPUT SIGNAL ROUTING DSP CORE: BIQUAD FILTERS, LIMITERS, VOLUME CONTROLS, MIXING I2C/SPI CONTROL INTERFACE AND SELF BOOT BIDIRECTIONAL ASRCS SERIAL INPUT/ OUTPUT PORT LDO REGULATORREG_OUT AVDD AVDD AVDD IOVDD DVDD POWER MANAGEMENT PD PLL CLOCK OSCILLATOR SELFBOOT DGND AGND AGND AGND ADDR0/SS ADDR1/MOSI SCL/SCLK SDA/MISO DAC_SDATA/MP0 ADC_SDATA1/CLKOUT/MP6 XTALI/MCLKIN XTALO ADC_SDATA0/PDMOUT/MP1 BCLK/MP2 LRCLK/MP3 DAC HPOUTLP/LOUTLP DAC ADC ADC STEREO PDM MODULATOR ADAU1777 ADC PGAAIN2 PGAAIN0 PGAAIN1 AIN3 PGA ADC HPOUTLN/LOUTLN HPOUTRP/LOUTRP HPOUTRN/LOUTRN 14796-001 Figure 1.

Rev. 0 | Page 2 of 108 TABLE OF CONTENTS

Rev. 0 | Page 3 of 108 Serial Data Output 0/Serial Data Output 1 Input Select Serial Data Output 2/Serial Data Output 3 Input Select Serial Data Output 4/Serial Data Output 5 Input Select Serial Data Output 6/Serial Data Output 7 Input Select ASRC Interpolator and DAC Modulator Power Control

REVISION HISTORY

12/2016—Revision 0: Initial Version

Rev. 0 | Page 4 of 108 SPECIFICATIONS Master clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, TA = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS AVDD = IOVDD = 1.8 V , DVDD = 1.1 V , unless otherwise noted. Phase-locked loop (PLL) disabled, direct master clock. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Gain settings do not include 10 dB gain from PGA_x_BOOST settings; this additional gain does not affect input impedance; PGA_POP_DISx = 1 Single-Ended Line Input 0 dB gain 14.3 kΩ Programmable Gain Amplifier (PGA) Inputs −12 dB gain 32.0 kΩ 0 dB gain 20 kΩ +35.25 dB gain 0.68 kΩ LINE INPUT PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1 Full-Scale Input Voltage Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 V rms AVDD = 1.8 V 1.54 V p-p AVDD = 3.3 V 1.00 V rms AVDD = 3.3 V 2.83 V p-p Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 95 97 dB AVDD = 3.3 V 99 102 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 92 94 dB AVDD = 3.3 V 96 99 dB Signal-to-Noise Ratio (SNR)2 With A-Weighted Filter (RMS) AVDD = 1.8 V 96 98 dB AVDD = 3.3 V 100 103 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 92 96 dB AVDD = 3.3 V 96 100 dB Interchannel Gain Mismatch 0 40 200 mdB Total Harmonic Distortion + Noise (THD + N) 20 Hz to 20 kHz, −1 dB from full-scale input AVDD = 1.8 V −90 −83 dB AVDD = 3.3 V −94 −87 dB Offset Error −0.11 +0.12 mV Gain Error −0.4 +0.2 dB Interchannel Isolation CM capacitor = 22 μF 95 dB Power Supply Rejection Ratio (PSRR) CM capacitor = 22 μF, 100 mV p-p at 1 kHz 55 dB PGA INPUT PGA_ENx = 1, PGA_x_BOOST = 0 Full-Scale Input Voltage Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 V rms AVDD = 1.8 V 1.54 V p-p AVDD = 3.3 V 1.00 V rms AVDD = 3.3 V 2.83 V p-p Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 102 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB

Rev. 0 | Page 5 of 108 Parameter Test Conditions/Comments Min Typ Max Unit THD + N 20 Hz to 20 kHz, −1 dB from full-scale input AVDD = 1.8 V −88 dB AVDD = 3.3 V −90 dB SNR2 With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 102 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 93 dB AVDD = 3.3 V 98 dB PGA Gain Variation Standard deviation With −12 dB Setting 0.05 dB With +35.25 dB Setting 0.15 dB PGA Boost PGA_x_BOOST 10 dB PGA Mute Attenuation PGA_MUTEx −63 dB Interchannel Gain Mismatch 0.04 dB Offset Error −0.12 +0.12 mV Gain Error −0.05 dB Interchannel Isolation 100 dB PSRR CM capacitor = 20 μF, 100 mV p-p at 1 kHz 63 dB MICROPHONE BIAS MIC_ENx = 1 Bias Voltage AVDD = 3.3 V, MIC_GAINx = 1 2.10 2.12 2.14 V AVDD = 3.3 V, MIC_GAINx = 0 2.95 2.97 2.99 V Bias Current Source 3 mA Output Impedance 1 Ω MICBIASx Isolation MIC_GAINx = 0 95 dB MIC_GAINx = 1 99 dB Noise in the Signal Bandwidth 20 Hz to 20 kHz, 4.7 µF decoupling capacitor, 5.0 kΩ load on the MICBIASx pins AVDD = 1.8 V MIC_GAINx = 0 27 nV/√Hz MIC_GAINx = 1 16 nV/√Hz AVDD = 3.3 V MIC_GAINx = 0 35 nV/√Hz MIC_GAINx = 1 19 nV/√Hz DIGITAL-TO-ANALOG CONVERTERS (DACs) Resolution All DACs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB DAC SINGLE-ENDED OUTPUT Single-ended operation, HPOUTLP/LOUTLP and HPOUTRP/LOUTRP pins Full-Scale Output Voltage Scales linearly with AVDD AVDD/3.4 V rms AVDD = 1.8 V 0.53 V rms AVDD = 1.8 V 1.5 V p-p AVDD = 3.3 V 0.97 V rms AVDD = 3.3 V 2.74 V p-p Mute Attenuation −72 dB Line Output Mode Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 97 100 dB AVDD = 3.3 V 102 104 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 95 97 dB AVDD = 3.3 V 99 101 dB

Rev. 0 | Page 6 of 108 Parameter Test Conditions/Comments Min Typ Max Unit SNR2 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 98 100 dB AVDD = 3.3 V 102 104 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 96 98 dB AVDD = 3.3 V 99 102 dB Interchannel Gain Mismatch 0 50 200 mdB THD + N 20 Hz to 20 kHz, −1 dBFS input dB AVDD = 1.8 V −93 −89 dB AVDD = 3.3 V −94 −90 dB Gain Error −0.13 +0.13 dB Headphone Mode Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 97 100 dB AVDD = 3.3 V 102 104 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 95 97 dB AVDD = 3.3 V 99 101 dB SNR2 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 98 100 dB AVDD = 3.3 V 102 104 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 96 98 dB AVDD = 3.3 V 100 102 dB Interchannel Gain Mismatch 0 50 230 mdB THD + N 20 Hz to 20 kHz, −1 dBFS input 32 Ω Load AVDD = 1.8 V, output power = 6.3 mW −79 −67 dB AVDD = 3.3 V, output power = 20.5 mW −84 −67 dB 24 Ω Load AVDD = 1.8 V, output power = 8.4 mW −79 −65 dB AVDD = 3.3 V, output power = 27 mW −80 −64 dB 16 Ω Load AVDD = 1.8 V, output power = 13 mW −74 −61 dB AVDD = 3.3 V, output power = 30 mW −77 −67 dB Gain Error −0.13 +0.13 dB Headphone Output Power 32 Ω Load AVDD = 1.8 V, <0.1% THD + N 8.0 mW AVDD = 3.3 V, <0.1% THD + N 28.1 mW 24 Ω Load AVDD = 1.8 V, <0.1% THD + N 11.1 mW AVDD = 3.3 V, <0.1% THD + N 30.5 mW 16 Ω Load AVDD = 1.8 V, <0.1% THD + N 16.5 mW AVDD = 3.3 V, <0.1% THD + N 32.7 mW Offset Error −0.11 +0.09 mV Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB PSRR CM capacitor = 22 µF, 100 mV p-p at 1 kHz 70 dB DAC DIFFERENTIAL OUTPUT Differential operation Full-Scale Output Voltage Scales linearly with AVDD AVDD/1.7 V rms AVDD = 1.8 V 1.06 V rms AVDD = 1.8 V 3.00 V p-p AVDD = 3.3 V 1.94 V rms AVDD = 3.3 V 5.49 V p-p Mute Attenuation −72 dB Line Output Mode Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 102 105 dB AVDD = 3.3 V 105 107 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 100 102 dB AVDD = 3.3 V 102 105 dB

Rev. 0 | Page 7 of 108 Parameter Test Conditions/Comments Min Typ Max Unit SNR2 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 103 105 dB AVDD = 3.3 V 106 108 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 100 102 dB AVDD = 3.3 V 103 105 dB Interchannel Gain Mismatch 0 50 200 mdB THD + N 20 Hz to 20 kHz, −1 dBFS input dB AVDD = 1.8 V −96 −90 dB AVDD = 3.3 V −96 −90 dB Gain Error −0.1 +0.16 dB Headphone Mode Dynamic Range1 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 102 105 dB AVDD = 3.3 V 105 107 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 100 102 dB AVDD = 3.3 V 102 104 dB SNR2 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 103 106 dB AVDD = 3.3 V 106 108 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 101 103 dB AVDD = 3.3 V 104 106 dB Interchannel Gain Mismatch 0 75 370 mdB THD + N 32 Ω Load −1 dBFS, AVDD = 1.8 V, output power = 26 mW −75 −64 dB −1 dBFS, AVDD = 3.3 V, output power = 87 mW −83 −75 dB 24 Ω Load −2 dBFS, AVDD = 1.8 V, output power = 27 mW −75 −64 dB −1 dBFS, AVDD = 3.3 V, output power = 115 mW −82 −75 dB 16 Ω Load −3 dBFS, AVDD = 1.8 V, output power = 32 mW −75 −65 dB −1 dBFS, AVDD = 3.3 V, output power = 168 mW −77 −68 dB Gain Error Headphone mode −0.25 +0.25 dB Headphone Output Power 32 Ω Load AVDD = 1.8 V, <0.1% THD + N 29.1 mW AVDD = 3.3 V, <0.1% THD + N 111.8 mW 24 Ω Load AVDD = 1.8 V, <0.1% THD + N 31.8 mW AVDD = 3.3 V, <0.1% THD + N 148.3 mW 16 Ω Load AVDD = 1.8 V, <0.1% THD + N 32.3 mW AVDD = 3.3 V, <0.1% THD + N 193.0 mW Offset Error −0.12 0 +0.08 mV Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB PSRR CM capacitor = 22 μF, 100 mV p-p at 1 kHz 73 dB ANALOG-TO-ANALOG LATENCY fS = 768 kHz 5 µs fS = 192 kHz 38 µs CM REFERENCE CM pin Common-Mode Reference Output AVDD/2 V Common-Mode Source Impedance 5 kΩ REGULATOR Line Regulation 1 mV/V Load Regulation 6 mV/mA 1 Dynamic range is the ratio of the sum of the noise and harmonic power in the band of interest with a − 60 dBFS signal present vs. the full-scale power level in decibels. 2 SNR is the ratio of the sum of all noise power in the band of interest with no signal present vs. the full -scale power level in decibels.

Rev. 0 | Page 8 of 108 CRYSTAL AMPLIFIER SPECIFICATIONS AVDD = IOVDD = 1.8 V , DVDD = 1.1 V , unless otherwise noted. Table 2. Parameter Min Typ Max Unit CRYSTAL AMPLIFIER Jitter 270 500 ps rms Frequency Range 8 27 MHz Load Capacitance 20 pF DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 3.3 V ± 10% and 1.8 V − 5% to 1.8 V + 10%, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit INPUT/OUTPUT Input Voltage High (VIH) IOVDD = 3.3 V 2.0 V IOVDD = 1.8 V 1.1 V Low (VIL) IOVDD = 3.3 V 0.8 V IOVDD = 1.8 V 0.45 V Input Leakage IOVDD = 3.3 V, IIH1 at VIH = 2.0 V 10 µA IIL1 at VIL = 0.8 V 10 µA IOVDD = 1.8 V, IIH1 at VIH = 1.1 V 10 µA IIL1 at VIL = 0.45 V 10 µA Output Voltage High (VOH) Low Drive Strength IOH1 = 1 mA IOVDD − 0.6 V High Drive Strength IOH1 = 3 mA IOVDD − 0.6 V Output Voltage Low (VOL) Low Drive Strength IOL1 = 1 mA 0.4 V High Drive Strength IOL1 = 3 mA 0.4 V Input Capacitance 5 pF 1 IIH is the current when the input is high; IIL is the current when the input is low; IOH is the current when the output is high; and IOL is the current when the output is low. POWER SUPPLY SPECIFICATIONS AVDD = IOVDD = 1.8 V , DVDD = 1.1 V , unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit SUPPLIES AVDD Voltage 1.71 1.8 3.63 V DVDD Voltage 1.045 1.1 1.98 V IOVDD Voltage 1.71 1.8 3.63 V Analog Current (IAVDD) Normal Operation See Table 5 Power-Down 1.6 µA Digital Input/Output Current (IIOVDD) Normal Operation See Table 5 Power-Down 1.3 µA POWER CONSUMPTION All Supplies See Table 5 Power-Down, All Supplies 1 µW

Rev. 0 | Page 9 of 108 TYPICAL POWER MANAGEMENT SETTINGS Typical ANC settings, master clock = 12.288 MHz, PLL disabled, crystal oscillator enabled, core fS = DAC = ADC = 768 kHz. On-board regulator enabled. Two ADCs with PGA enabled and two ADCs configured for line input, no input signal. Two DACs are configured for differential headphone (HP) operation; DAC outputs are unloaded. Both MICBIAS0 and MICBIAS1 enabled at 0.9 × AVDD. ASRCs and pulse density modulation (PDM) modulator disabled. Core running 26 out of 32 possible instructions. Serial port set to slave. See Register 0x46 and Register 0x47 for settings. Table 5. Operating Voltage Power Management Setting Typical AVDD Current Consumption (mA) Typical IOVDD Current Consumption (mA) Typical ADC THD + N (dB) Typical HP Output THD + N (dB) Total Power Consumption (mW) AVDD = IOVDD = 3.3 V Normal 9.71 2.58 −91 −97 40.56 Extreme power saving 7.55 2.57 −86 −96 33.40 Power saving 7.99 2.57 −87 −96 34.85 Enhanced performance 10.97 2.58 −91 −98 44.72 AVDD = IOVDD = 1.8 V Normal 7.29 0.37 −87 −95 13.79 Extreme power saving 5.38 0.37 −81 −89 10.35 Power saving 5.73 0.37 −81 −90 10.98 Enhanced Performance 8.62 0.37 −87 −95 16.18 DIGITAL FILTERS SPECIFICATIONS Table 6. Parameter Test Conditions/Comments Min Typ Max Unit ADC INPUT TO DAC OUTPUT PATH Pass-Band Ripple DC to 20 kHz, fS = 768 kHz −0.03 +0.01 dB DC to 20 kHz, fS = 192 kHz ±0.02 dB SAMPLE RATE CONVERTER Pass Band LRCLK < 63 kHz 0 0.475 × fS kHz 63 kHz < LRCLK <130 kHz 0 0.4286 × fS kHz LRCLK > 130 kHz 0 0.4286 × fS kHz Pass-Band Ripple Upsampling, 96 kHz −0.27 +0.05 dB Upsampling, 192 kHz −0.06 +0.05 dB Downsampling, 96 kHz 0 0.07 dB Downsampling, 192 kHz 0 0.07 dB Input/Output Frequency Range 8 192 kHz Dynamic Range 100 dB THD + N −90 dB Start-Up Time 15 ms PDM MODULATOR Dynamic Range (A-Weighted) 112 dB THD + N −92 dB

Table 7. Digital Timing

Figure 2. Serial Input Port Timing

Table 9. Thermal Resistance

1 Thermal impedance simulated values are based on a 4-layer PCB with two

Figure 9. Pin Configuration Table 10. Pin Function Descriptions A2 BCLK/MP2 D_IO Serial Data Port Bit Clock (BCLK). A3 ADC_SDATA0/PDMOUT/MP1 D_IO ADC Serial Data Output 0 (ADC_SDATA0). Stereo PDM Output to Drive a High Efficiency Class-D Amplifier (PDMOUT). A4 ADC_SDATA1/CLKOUT/MP6 D_IO Serial Data Output 1 (ADC_SDATA1). Master Clock Output/Clock for the Digital Microphone Input and PDM Output (CLKOUT). A6 XTALI/MCLKIN D_IN Crystal Clock Input (XTALI). Master Clock Input (MCLKIN). loads of the digital outputs. Decouple IOVDD to DGND with a 0.1 μF capacitor. B2 LRCLK/MP3 D_IO Serial Data Port Frame Clock (LRCLK). B3 DAC_SDATA/MP0 D_IO DAC Serial Input Data (DAC_SDATA). B4 DMIC2_3/MP5 D_IN Digital Microphone Stereo Input 2 and Digital Microphone Stereo Input 3 (DMIC2_3).

Rev. 0 | Page 16 of 108 Pin No. Mnemonic Type1 Description B5 DMIC0_1/MP4 D_IN Digital Microphone Stereo Input 0 and Digital Microphone Stereo Input 1 (DMIC0_1). Multipurpose Pin (MP4). B6 SDA/MISO D_IO I2C Data (SDA). This pin is a bidirectional open-collector. The line connected to this pin must have a 2.0 kΩ pull-up resistor. SPI Data Output (MISO). This SPI data output reads back registers and memory locations. It is tristated when an SPI read is not active. B7 SCL/SCLK D_IN I2C Clock (SCL). This pin is always an open-collector input when the device is in I2C control mode. When the device is in self boot mode, this pin is an open-collector output (I2C master). The line connected to this pin must have a 2.0 kΩ pull-up resistor. SPI Clock (SCLK). This pin either can run continuously or be gated off between SPI transactions. C1 HPOUTRP/LOUTRP A_OUT Right Headphone Output Noninverted (HPOUTRP). Line Output Noninverted, Single-Ended Line Output (LOUTRP). C2 REG_OUT A_OUT Regulator Output Voltage. Connect this pin to DVDD if the internal voltage regulator is being used to generate the DVDD voltage. C6 ADDR0/SS D_IN I2C Address 0 (ADDR0). SPI Latch Signal (SS). This pin must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction can take a different number of SCLK cycles to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. C7 MICBIAS0 A_OUT Bias Voltage for Electret Microphone. Decouple this pin with a 1 µF capacitor. D1 AVDD PWR Headphone Amplifier Power, 1.8 V to 3.3 V Analog Supply. Decouple this pin to AGND with a 0.1 μF capacitor. The PCB trace to this pin must have the capacity to supply the higher current necessary for driving the headphone outputs. D2 HPOUTRN/LOUTRN A_OUT Right Headphone Output Inverted (HPOUTRN). Line Output Inverted (LOUTRN). D6 ADDR1/MOSI D_IN I2C Address 1 (ADDR1). SPI Data Input (MOSI). D7 MICBIAS1 A_OUT Bias Voltage for Electret Microphone. Decouple this pin with a 1 µF capacitor. E1 AGND PWR Headphone Amplifier Ground. E2 HPOUTLP/LOUTLP A_OUT Left Headphone Output Noninverted (HPOUTLP). Line Output Noninverted, Single-Ended Line Output (LOUTLP). E3 PD D_IN Active Low Power-Down. All digital and analog circuits are powered down. An internal pull-down resistor is on this pin; therefore, the ADAU1777 is held in power-down mode if its input signal is floating while power is applied to the supply pins. E4 AIN3 A_IN ADC3 Input. E5 AIN0 A_IN ADC0 Input. E6 SELFBOOT D_IN Self Boot Enable. Pull this pin up to IOVDD at power-up to enable the self boot mode. F1 HPOUTLN/LOUTLN A_OUT Left Headphone Output Inverted (HPOUTLN). Line Output Inverted (LOUTLN). F3 AGND PWR Analog Ground. F4 AIN2 A_IN ADC2 Input. F5 AIN1 A_IN ADC1 Input. F6 CM A_OUT AVDD/2 V Common-Mode Reference. Connect a 10 μF to 47 μF decoupling capacitor between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not critical. This pin can bias external analog circuits, as long as they are not drawing current from CM (for example, the noninverting input of an op amp). F7 AGND PWR Analog Ground. The AGND and DGND pins can be tied directly together in a common ground plane. Decouple AGND to AVDD with a 0.1 μF capacitor. 1 PWR is power; D_IO is digital input/output; A_OUT is analog output; D_IN is digital input; and A_IN is analog input.

Rev. 0 | Page 24 of 108 THEORY OF OPERATION The ADAU1777 is a low power audio codec with a streamlined audio processing core, making it ideal for noise canceling applications that require high quality audio, low power, small size, and low latency. The operating voltage range is 1.71 V to

3.63 V , with an on-board regulator optionally generating the

internal digital supply voltage. By enabling low latency settings, the ADAU1777 can reach latencies as low as 5 μs. The ADCs and DACs are high quality, 24-bit, Σ-Δ converters that operate at a selectable 768 kHz, 192 kHz, or 96 kHz sampling rate. The ADCs have an optional high-pass filter with a cutoff frequency of 1 Hz, 4 Hz, or 8 Hz. The ADCs and DACs also include fine step digital volume controls. The stereo DAC output can differentially drive a headphone earpiece speaker with 16 Ω or higher impedance. One side of the differential output can be powered down if single-ended operation is required. There is also the option to change to line output mode when the output has a low load. The input signal path is flexible and can accept single-ended analog microphone inputs, serial audio inputs, and digital microphone inputs. Two microphone bias pins provide seamless interfacing to electret microphones. Each analog input has an independent PGA that can be used for volume adjustment. The serial data port is compatible with I 2S, left justified, right justified, and TDM modes, with tristating for interfacing to digital audio data streams. The core has a reduced instruction set that is optimized for active noise cancellation. The program and parameter RAMs can be loaded with custom audio processing signal flows built using the SigmaStudio™ graphical programming software from Analog Devices, Inc. The values stored in the parameter RAM control individual signal processing blocks. The ADAU1777 also has a self boot function that can load the program RAM, parameter RAM, and register settings on power-up using an external EEPROM. The SigmaStudio software programs and controls the core through the I 2C or SPI control port. Along with aiding in the design and tuning of a signal flow, SigmaStudio can configure all of the ADAU1777 registers. The SigmaStudio graphical interface allows anyone with digital or analog audio processing knowledge to easily design the DSP signal flow and port it to a target application. The interface also provides enough flexibility and programmability for an experienced DSP programmer to have in-depth control of the design. In SigmaStudio, the user can connect graphical blocks (such as biquad filters, volume controls, and arithmetic operations), compile the design, and load the program and parameter files into the ADAU1777 memory through the control port. SigmaStudio also allows the user to download the design to an external EEPROM for self boot operation. Signal processing blocks available in the provided libraries include the following:

• Single-precision biquad filters
• Second-order filters
• Absolute value and two-input adder
• Volume controls
• Limiter The ADAU1777 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 8 MHz to 27 MHz. For standalone operation, the clock can be generated using the on-board crystal oscillator.

12.288 MHz crystal, and the crystal oscillator function must be

in the system. Bypassing the PLL saves system power. PLL, it is necessary to use the internal divide by 2 (see Table 11). Table 11. Clock Configuration Settings 1 1 Divide the PLL/external clock by 1. input clock source or if using the PLL. On power-up, the ADAU1777 exits an internal reset after 15 ms. the CC_MDIV bit in the clock control register (Address 0x00). of the ADAU1777 is disabled until the COREN bit is asserted. enables the core clock for all the internal blocks of the ADAU1777.

1. Ensure that PLL_EN (Bit 7, Address 0x00) is set low.
2. Set or reset the PLL control registers (Address 0x01 to
3. Enable the PLL using the PLL_EN bit.
4. Poll the PLL lock bit in Register 0x06.
5. Set the COREN bit in Register 0x00 after the PLL lock is

the CORE_RUN bit first must be disabled. accept input frequencies in the range of 8 MHz to 27 MHz. Figure 51. PLL Block Diagram (Address 0x05, Bits[2:1]) set the PLL input clock divide ratio.

to ensure correct operation of the PLL.

27 MHz, which must be taken into account when calculating PLL

values and MCLK frequencies. between 1.1 V and 1.2 V if using the on-board regulator. Enabling the PD pin powers down all analog and digital circuits. PD directly to IOVDD for normal operation. Table 12. Integer PLL Parameter Settings for PLL Output = 24.576 MHz Table 13. Fractional PLL Parameter Settings for PLL Output = 24.576 MHz

routing is specified by Register 0x0F through Register 0x1A. 1THE ADC_SDATA0 AND PDMOUT FUNCTIONS SHARE A PHYSICAL PIN; THEREFORE ONLY ONE OF THESE FUNCTIONS CAN BE USED AT A TIME. Figure 52. Input and Output Signal Routing

Table 14. SSM2517 PDM Control Pattern Descriptions interface. Normal start-up time. 0xD1 f S set to opposite value determined by GAIN_FS pin. 0xE1 Ultralow electromagneti c interference (EMI) mode. 0xE2 Half clock cycle pulse mode for power savings. 0xE4 Special 32 kHz,128 × f S operation mode. for the digital input signals. intermediate frequencies and ratios are also supported. the DACs or output ASRCs, are scaled by 1.33, or about 2.5 dB. This scaling is shown in Figure 57. Figure 57. Signal Level Diagram DACs and ASRCs from clipping.

program word, with a maximum of 32 instructions per frame.

• Single precision biquad/second-order filters
• Absolute value
• Two-input addition
• T connection in SigmaStudio
• Limiter with/without external detector loop
• Linear gain
• Volume slider
• Mute
• DBREG level detection DATA MEMORY The ADAU1777 data path is 26 bits (5.21 format). The data memory is 32 words of 2 × 26 bits. The double length memory enables the core to double precision arithmetic with double length data and single length coefficients. PARAMETERS Parameters, such as filter coefficients, limiter settings, and volume control settings, are saved in parameter registers. Each parameter is a 32-bit number. The format of this number depends on whether it is controlling a filter or a limiter. The number formats of different parameters are shown in Table 15. When the parameter formats use less than the full 32-bit memory space, as with the limiter parameters, the data is LSB aligned.

Table 15. Parameter Number Formats types that use parameters are the biquad filters and limiters. addresses of the LSB aligned, 10-bit program words. Table 16. Program Addresses

Table 17. Parameter Addresses, Bank A Table 18. Parameter Addresses, Bank B

Rev. 0 | Page 34 of 108 Assignment Order B0/Maximum Gain B1/Minimum Gain B2/Attack A1/Decay A2/Threshold 16 0x0190 0x01B0 0x01D0 0x01F0 0x0210 17 0x0191 0x01B1 0x01D1 0x01F1 0x0211 18 0x0192 0x01B2 0x01D2 0x01F2 0x0212 19 0x0193 0x01B3 0x01D3 0x01F3 0x0213 20 0x0194 0x01B4 0x01D4 0x01F4 0x0214 21 0x0195 0x01B5 0x01D5 0x01F5 0x0215 22 0x0196 0x01B6 0x01D6 0x01F6 0x0216 23 0x0197 0x01B7 0x01D7 0x01F7 0x0217 24 0x0198 0x01B8 0x01D8 0x01F8 0x0218 25 0x0199 0x01B9 0x01D9 0x01F9 0x0219 26 0x019A 0x01BA 0x01DA 0x01FA 0x021A 27 0x019B 0x01BB 0x01DB 0x01FB 0x021B 28 0x019C 0x01BC 0x01DC 0x01FC 0x021C 29 0x019D 0x01BD 0x01DD 0x01FD 0x021D 30 0x019E 0x01BE 0x01DE 0x01FE 0x021E 31 0x019F 0x01BF 0x01DF 0x01FF 0x021F

SPI control mode by pulling the SS pin low three times. Table 19. Data-Word Sizes in a register with other used bits, write 0s. Table 20. Control Port Pin Functions register (or memory location). between the ADAU1777 and the system I2C master controller. about using the ADAU1777 in self boot mode. Logic Level 0 corresponds to a write operation. addresses are shown in Table 22. An I2C data transfer is always terminated by a stop condition. Table 21. I2C Address Format Table 22. I2C Addresses

shows the timing of an I2C read. by the ADAU1777, and the device returns to the idle condition.

111 ADDR0ADDR11

Figure 58. I2C Write to ADAU1777 Clocking Figure 59. I2C Read from ADAU1777 Clocking

clock that is no faster than 25.6 MHz. load the register, program, and parameter settings. include the Atmel® AT24C32D and STMicroelectronics M24C32-F. to control the self boot procedure. Table 24. Maximum EEPROM Size strong enough to detect single error bursts of up to eight bits in size. and restarted after a 250 ms delay (for a 12.288 MHz input clock). matically when a configuration is downloaded to the EEPROM. 16-bit setting × 2048 clock cycles. Table 25. EEPROM Self Boot Instructions Figure 66. Example Self Boot EEPROM Instructions

bank switching, DSP bypass mode, and muting the outputs. Register 0x3E. By default, each pin is configured as an input. Table 26. Multipurpose Pin Functions push-buttons: one to increase volume and one to decrease volume. the button goes from low to high. longer allow control of the volume from the control port. effect on the codec volume level. compress the incoming signal by the minimum gain setting. of 0x00 before enabling MPx pin control over bank switching. and MPx pin selection is not possible. The MPx pins can be put into a mode to mute the ADCs or DACs. When in this mode, mute is enabled when an MPx pin is set low. using the MPx pins are set in Register 0x38 to Register 0x3E.

Address 0x13 to Address 0x16). can be set to be either the master or the slave in a system. output ports must always both be either master or slave. cause an error, but they are truncated internally. PAD_CONTROL4 register (Address 0x4C). Table 27. Serial Input/Output Port Master/Slave Mode channels in the SOUT_CONTROL0 register (Address 0x34). are tristated. Inactive channels are also tristated for the full frame. Table 28. Serial Port Data Format Settings Figure 69. I2S Mode, 16 Bits to 24 Bits per Channel

Figure 70. Left Justified (LJ) Mode, 16 Bits to 24 Bits per Channel Figure 71. Right Justified (RJ) Mode, 24 Bits per Channel Figure 72. Right Justified (RJ) Mode, 16 Bits per Channel

256 BCLKs

32 BCLKs

Figure 73. 8-Channel TDM Mode Figure 74. 8-Channel TDM Mode, Pulse LRCLK

Table 29. Core Control Register (Register 0x0009) CORE_RUN bit must be set to 0 for this setting to be updated. Table 30. Sleep on Program Address Count Register (Register 0x000A) 00000 No sleep, all instructions are executed. Table 31. ADC0/ADC1 Control 0 Register (Register 0x001B) while the core is running. The CORE_RUN bit must be set to 0 for this setting to be updated. that the frequency selected must match the CORE_FS selected via Bits[2:1] of Register 0x0009.

Table 32. ADC2/ADC31 Control 0 Register (Register 0x001C) while the core is running. The CORE_RUN bit must be set to 0 for this setting to be updated. [1:0] ADC_2_3_FS These bits set the ADC sample rate. The ADAU1777 supports the option of 768 kHz as well. Table 33. Fast Rate Control Register (Register 0x004E) (6.144 MHz) when CORE_FS = 11. This setting must not be changed while the core is running. Table 34. DAC Interpolation Control Register (Register 0x004F) [7:6] DAC_RATE These bits set the DAC_RATE value, which sets the sample rate for the DAC only. [5:3] DAC_INTP These bits set the DAC_INTP value, which sets the interpolation mode for the DAC. 000 Both DAC0 and DAC1 set to compensated interpolation. 001 DAC0 set to zero-order hold (ZOH), DAC1 set to compensated interpolation. 010 DAC0 set to compensated interpolation, DAC1 set to ZOH. 011 Both DAC0 and DAC1 set to ZOH. 100 DAC0 set to linear interpolation, DAC1 set to compensated interpolation. 101 DAC0 set to compensated interpolation, DAC1 set to linear interpolation. 110 Both DAC0 and DAC1 set to linear interpolation.

Table 35. Volume Control Bypass Register (Register 0x0054) 5 DAC1VOL_BY DAC1 volume control bypass. 4 DAC0VOL_BY DAC0 volume control bypass. 3 ADC3VOL_BY ADC3 volume control bypass. 2 ADC2VOL_BY ADC2 volume control bypass. 1 ADC1VOL_BY ADC1 volume control bypass. 0 ADC0VOL_BY ADC0 volume control bypass.

Table 36. Register Summary

Rev. 0 | Page 50 of 108 Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x23 PGA_CONTROL_ [7:0] PGA_EN0 PGA_ MUTE0 PGA_GAIN0 0x40 R/W 0x24 PGA_CONTROL_ [7:0] PGA_EN1 PGA_ MUTE1 PGA_GAIN1 0x40 R/W 0x25 PGA_CONTROL_ [7:0] PGA_EN2 PGA_ MUTE2 PGA_GAIN2 0x40 R/W 0x26 PGA_CONTROL_ [7:0] PGA_EN3 PGA_ MUTE3 PGA_GAIN3 0x40 R/W 0x27 PGA_STEP_ CONTROL [7:0] RESERVED SLEW_RATE SLEW_PD3 SLEW_PD2 SLEW_PD1 SLEW_PD0 0x00 R/W 0x28 PGA_10DB_ BOOST [7:0] RESERVED PGA_3_ BOOST PGA_2_BOOST PGA_1_BOOST PGA_0_ BOOST 0x00 R/W 0x29 POP_SUPPRESS [7:0] RESERVED HP_POP_ DIS1 HP_POP_ DIS0 PGA_POP_ DIS3 PGA_POP_DIS2 PGA_POP_DIS1 PGA_POP_ DIS0 0x3F R/W 0x2A TALKTHRU [7:0] RESERVED TALKTHRU_PATH 0x00 R/W 0x2B TALKTHRU_ GAIN0 [7:0] TALKTHRU_GAIN0_VAL 0x00 R/W 0x2C TALKTHRU_ GAIN1 [7:0] TALKTHRU_GAIN1_VAL 0x00 R/W 0x2D MIC_BIAS [7:0] RESERVED MIC_EN1 MIC_EN0 RESERVED RESERVED MIC_GAIN1 MIC_ GAIN0 0x00 R/W 0x2E DAC_ CONTROL1 [7:0] RESERVED DAC_POL DAC1_MUTE DAC0_MUTE RESERVED DAC1_EN DAC0_EN 0x18 R/W 0x2F DAC0_VOLUME [7:0] DAC_0_VOL 0x00 R/W 0x30 DAC1_VOLUME [7:0] DAC_1_VOL 0x00 R/W 0x31 OP_STAGE_ MUTES [7:0] RESERVED HP_MUTE_R HP_MUTE_L 0x0F R/W 0x32 SAI_0 [7:0] SDATA_FMT SAI SER_PORT_FS 0x00 R/W 0x33 SAI_1 [7:0] TDM_TS BCLK_ TDMC LR_MODE LR_POL SAI_MSB BCLKRATE BCLKEDGE SAI_MS 0x00 R/W 0x34 SOUT_ CONTROL0 [7:0] TDM7_DIS TDM6_DIS TDM5_DIS TDM4_DIS TDM3_DIS TDM2_DIS TDM1_DIS TDM0_DIS 0x00 R/W 0x36 PDM_OUT [7:0] RESERVED PDM_CTRL PDM_CH PDM_EN 0x00 R/W 0x37 PDM_PATTERN [7:0] PATTERN 0x00 R/W 0x38 MODE_MP0 [7:0] RESERVED MODE_MP0_VAL 0x00 R/W 0x39 MODE_MP1 [7:0] RESERVED MODE_MP1_VAL 0x10 R/W 0x3A MODE_MP2 [7:0] RESERVED MODE_MP2_VAL 0x00 R/W 0x3B MODE_MP3 [7:0] RESERVED MODE_MP3_VAL 0x00 R/W 0x3C MODE_MP4 [7:0] RESERVED MODE_MP4_VAL 0x00 R/W 0x3D MODE_MP5 [7:0] RESERVED MODE_MP5_VAL 0x00 R/W 0x3E MODE_MP6 [7:0] RESERVED MODE_MP6_VAL 0x11 R/W 0x3F PB_VOL_SET [7:0] PB_VOL_INIT_VAL HOLD 0x00 R/W 0x40 PB_VOL_CONV [7:0] GAINSTEP RAMPSPEED PB_VOL_CONV_VAL 0x87 R/W 0x41 DEBOUNCE_ MODE [7:0] RESERVED DEBOUNCE 0x05 R/W 0x43 OP_STAGE_ CTRL [7:0] RESERVED HP_EN_R HP_EN_L HP_PDN_R HP_PDN_L 0x0F R/W 0x44 DECIM_PWR_ MODES [7:0] DEC_3_EN DEC_2_EN DEC_1_EN DEC_0_EN SINC_3_EN SINC_2_EN SINC_1_EN SINC_0_EN 0x00 R/W 0x45 INTERP_PWR_ MODES [7:0] RESERVED MOD_1_EN MOD_0_EN INT_1_EN INT_0_EN 0x00 R/W 0x46 BIAS_ CONTROL0 [7:0] HP_IBIAS AFE_IBIAS01 ADC_IBIAS23 ADC_IBIAS01 0x00 R/W 0x47 BIAS_ CONTROL1 [7:0] RESERVED CBIAS_DIS AFE_IBIAS23 MIC_IBIAS DAC_IBIAS 0x00 R/W 0x48 PAD_ CONTROL0 [7:0] RESERVED DMIC2_3_ PU DMIC0_1_PU LRCLK_PU BCLK_PU ADC_SDATA1_ PU ADC_SDATA0_ PU DAC_ SDATA_PU 0x7F R/W 0x49 PAD_ CONTROL1 [7:0] RESERVED SELFBOOT_ PU SCL_PU SDA_PU ADDR1_PU ADDR0_PU 0x1F R/W

Rev. 0 | Page 51 of 108 Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x4A PAD_ CONTROL2 [7:0] RESERVED DMIC2_3_ PD DMIC0_1_PD LRCLK_PD BCLK_PD ADC_SDATA1_ PD ADC_SDATA0_ PD DAC_ SDATA_PD 0x00 R/W 0x4B PAD_ CONTROL3 [7:0] RESERVED SELFBOOT_ PD SCL_PD SDA_PD ADDR1_PD ADDR0_ PD 0x00 R/W 0x4C PAD_ CONTROL4 [7:0] RESERVED RESERVED RESERVED LRCLK_DRV BCLK_DRV ADC_SDATA1_ DRV ADC_SDATA0_ DRV RESERVED 0x00 R/W 0x4D PAD_ CONTROL5 [7:0] RESERVED RESERVED SCL_DRV SDA_DRV RESERVED RESERVED 0x00 R/W 0x4E FAST_RATE [7:0] RESERVED RATE_DIV 0x00 R/W 0x4F DAC_ CONTROL0 [7:0] DAC_RATE DAC_INTP RESERVED 0x00 R/W 0x54 VOL_BYPASS [7:0] RESERVED DAC1VOL_BY DAC0VOL_ BY ADC3VOL_BY ADC2VOL_BY ADC1VOL_BY ADC0VOL_ BY 0x00 R/W

This register enables the internal clocks. Table 37. Bit Descriptions for CLK_CONTROL when both PLL_EN = 1 and COREN = 1. 1 I2C spike filter disabled. 0 Crystal oscillator enabled. 1 Crystal oscillator disabled. 0 External pin drives main clock. 0 Div 2: divide PLL/external clock by 2. 1 Div 1: divide PLL/external clock by 1.

logic except the core. It must run at 12.288 MHz. 0 Div 2: divide PLL/external clock by 2. 1 Div 1: divide PLL/external clock by 1. clock. If using the PLL, do not set COREN = 1 until LOCK in Register PLL_CTRL5 is 1. DSP_CLK_EN in the CORE_ENABLE register. Only write to this register when PLL_EN = 0 in Register CLK_CONTROL. Table 38. Bit Descriptions for PLL_CTRL0 Only write to this register when PLL_EN = 0 in Register CLK_CONTROL. Table 39. Bit Descriptions for PLL_CTRL1 Only write to this register when PLL_EN = 0 in Register CLK_CONTROL. Table 40. Bit Descriptions for PLL_CTRL2

Only write to this register when PLL_EN = 0 in Register CLK_CONTROL. Table 41. Bit Descriptions for PLL_CTRL3 Only write to this register when PLL_EN = 0 in Register CLK_CONTROL. Table 42. Bit Descriptions for PLL_CTRL4

Table 43. Bit Descriptions for PLL_CTRL5 When the ADC_SDATA1/CLKOUT/MP6 pin is set to clock output mode, the frequency of the output clock is set in this register. CLKOUT can be used to provide a master clock to another IC, the clock for digital microphones, or as the clock for the PDM output stream. Table 44. Bit Descriptions for CLKOUT_SEL 001 Master clock (12.288 MHz). 010 Master clock/2 (6.144 MHz). 011 Master clock/4 (3.072 MHz). 100 Master clock/8 (1.536 MHz).

Table 45. Bit Descriptions for REGULATOR 1: Zero state during back switch. 0: Do not zero state during bank switch. 10: slow rate = fast rate/8. 01: slow rate = fast rate/4. Table 46. Bit Descriptions for CORE_CONTROL 0 Do not zero state during bank switch. 1 Zero state during back switch.

Rev. 0 | Page 57 of 108 Bits Bit Name Settings Description Reset Access [6:5] BANK_SL Selects active filter bank. 0x0 R/W 00 Bank A active. 01 Bank B active. 10 Reserved. 11 Reserved. [4:3] FAST_SLOW_RATE Selects the speed of the slow rate relative to the fast rate. Do not change this setting while the core is running. CORE_RUN must be set to 0 for this setting to be updated. 0x0 R/W 00 Slow rate = fast rate. 01 Slow rate = fast rate/4. 10 Slow rate = fast rate/8. [2:1] CORE_FS This bit sets the core sample rate. Do not change this setting while the core is running. CORE_RUN must be set to 0 for this setting to be updated. 0x2 R/W 00 Reserved. 01 96 kHz. 10 192 kHz. 11 768 kHz. When this mode is set, the fast rate of the core is set in Bits RATE_DIV in the fast rate control register. 0 CORE_RUN Run bit for the core. Enable this bit only when the program and parameters are loaded and the sample rate settings are set. CORE_RUN starts and stops the core at the beginning of the program. 0x0 R/W 0 Core off. 1 Core on. SLEEP ON PROGRAM ADDRESS COUNT REGISTER Address: 0x0A, Reset: 0x00, Name: SLEEP_INST The SLEEP bits control which registers are sleeping. For example, if SLEEP = 7, only instructions at Address 0x00 to Address 0x05 are executed. SLEEP = 0 disables sleeping.

Table 47. Bit Descriptions for SLEEP_INST example, if SLEEP = 7, only instructions at Address 0x00 to Address 0x05 are executed. 00000 No sleep, all instructions are executed.

while the decay operation performs gain adjustments. Table 48. Bit Descriptions for CORE_ENABLE applied to instructions using the limiters. CORE_RUN in the CORE_CONTROL register to start or stop the core. the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG0 register. Table 49. Bit Descriptions for DBREG0

mine the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG1 register. Table 50. Bit Descriptions for DBREG1 mine the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG2 register. Table 51. Bit Descriptions for DBREG2

Table 52. Bit Descriptions for CORE_IN_MUX_0_1

Table 53. Bit Descriptions for CORE_IN_MUX_2_3

Table 54. Bit Descriptions for DAC_SOURCE_0_1 [7:4] DAC_SOURCE1 DAC1 input source. Do not change this setting while the core is running. CORE_RUN must be set to 0 for this setting to be updated. [3:0] DAC_SOURCE0 DAC0 input source. Do not change this setting while the core is running. CORE_RUN must be set to 0 for this setting to be updated.

Table 55. Bit Descriptions for PDM_SOURCE_0_1

Table 56. Bit Descriptions for SOUT_SOURCE_0_1

Table 57. Bit Descriptions for SOUT_SOURCE_2_3

Table 58. Bit Descriptions for SOUT_SOURCE_4_5

Table 59. Bit Descriptions for SOUT_SOURCE_6_7

Table 60. Bit Descriptions for ADC_SDATA_CH data following this start channel according to the setting of Bit SAI. data following this start channel according to the setting of Bit SAI. Table 61. Bit Descriptions for ASRCO_SOURCE_0_1

Table 62. Bit Descriptions for ASRCO_SOURCE_2_3

Rev. 0 | Page 71 of 108 Bits Bit Name Settings Description Reset Access 0101 ADC1. 0110 ADC2. 0111 ADC3. 1000 Serial Input 0. 1001 Serial Input 1. 1010 Serial Input 2. 1011 Serial Input 3. 1100 Serial Input 4. 1101 Serial Input 5. 1110 Serial Input 6. 1111 Serial Input 7. [3:0] ASRC_OUT_SOURCE2 Output ASRC Channel 2 source select. 0x2 R/W 0000 Core Output 0. 0001 Core Output 1. 0010 Core Output 2. 0011 Core Output 3. 0100 ADC0. 0101 ADC1. 0110 ADC2. 0111 ADC3. 1000 Serial Input 0. 1001 Serial Input 1. 1010 Serial Input 2. 1011 Serial Input 3. 1100 Serial Input 4. 1101 Serial Input 5. 1110 Serial Input 6. 1111 Serial Input 7. INPUT ASRC CHANNEL SELECT REGISTER Address: 0x1A, Reset: 0x00, Name: ASRC_MODE

Table 63. Bit Descriptions for ASRC_MODE 00 Serial Input Port Channel 0/Serial Input Port Channel 1. 01 Serial Input Port Channel 2/Serial Input Port Channel 3. 10 Serial Input Port Channel 4/Serial Input Port Channel 5. 11 Serial Input Port Channel 6/Serial Input Port Channel 7. Table 64. Bit Descriptions for ADC_CONTROL0 running. CORE_RUN must be set to 0 for this setting to be updated. attenuation. This bit has no effect if volume control is bypassed. attenuation. This bit has no effect if volume control is bypassed.

Table 65. Bit Descriptions for ADC_CONTROL1 running. CORE_RUN must be set to 0 for this setting to be updated. attenuation. This bit has no effect if volume control is bypassed.

Table 66. Bit Descriptions for ADC_CONTROL2 0 Channel swap off (left channel on rising edge, right channel on falling edge). 0 Decimator source set to ADC. 1 Decimator source set to digital microphones. DECIM_PWR_MODES register to fully enable or disable the ADC. DECIM_PWR_MODES register to fully enable or disable the ADC.

Table 67. Bit Descriptions for ADC_CONTROL3 0 Channel swap off (left channel on rising edge, right channel on falling edge). 0 Decimator source set to ADC. 1 Decimator source set to digital microphone. DECIM_PWR_MODES register to fully enable or disable the ADC. DECIM_PWR_MODES register to fully enable or disable the ADC.

Table 68. Bit Descriptions for ADC0_VOLUME Table 69. Bit Descriptions for ADC1_VOLUME Table 70. Bit Descriptions for ADC2_VOLUME

Table 71. Bit Descriptions for ADC3_VOLUME This register controls the PGA connected to AIN0. Table 72. Bit Descriptions for PGA_CONTROL_0 0 AIN0 used as a single-ended line input. PGA powered down. 1 AIN0 used as a single-ended microphone input. PGA powered up with slewing.

This register controls the PGA connected to AIN1. Table 73. Bit Descriptions for PGA_CONTROL_1 0 AIN1 used as a single-ended line input. PGA powered down. 1 AIN1 used as a single-ended microphone input. PGA powered up with slewing. This register controls the PGA connected to AIN2. Table 74. Bit Descriptions for PGA_CONTROL_2 0 AIN2 used as a single-ended line input. PGA powered down. 1 AIN2 used as a single-ended microphone input. PGA powered up with slewing.

This register controls the PGA connected to AIN3. Table 75. Bit Descriptions for PGA_CONTROL_3 0 AIN3 used as a single-ended line input. PGA powered down. 1 AIN3 used as a single-ended microphone input. PGA powered up with slewing.

If PGA slew is disabled with the SLEW_PDx controls, the SLEW_RATE parameter is ignored for that PGA block. Table 76. Bit Descriptions for PGA_STEP_CONTROL Each PGA can have an additional +10 dB gain added, making the PGA gain range −2 dB to +46 dB.

Table 77. Bit Descriptions for PGA_10DB_BOOST 0 Default PGA gain set in Register PGA_CONTROL_3. 1 Additional 10 dB gain above setting in Register PGA_CONTROL_3. 0 Default PGA gain set in Register PGA_CONTROL_2. 1 Additional 10 dB gain above setting in Register PGA_CONTROL_2. 0 Default PGA gain set in Register PGA_CONTROL_1. 1 Additional 10 dB gain above setting in Register PGA_CONTROL_1. 0 Default PGA gain set in Register PGA_CONTROL_0. 1 Additional 10 dB gain above setting in Register PGA_CONTROL_0. Table 78. Bit Descriptions for POP_SUPPRESS

Table 79. Bit Descriptions for TALKTHRU 11 ADC0 and ADC1 to DAC0 and DAC1. Table 80. Bit Descriptions for TALKTHRU_GAIN0 Table 81. Bit Descriptions for TALKTHRU_GAIN1

Table 82. Bit Descriptions for MIC_BIAS Table 83. Bit Descriptions for DAC_CONTROL1

Table 84. Bit Descriptions for DAC0_VOLUME

Table 85. Bit Descriptions for DAC1_VOLUME Table 86. Bit Descriptions for OP_STAGE_MUTES 01 HPOUTRP/LOUTRP muted, HPOUTRN/LOUTRN unmuted. 10 HPOUTRP/LOUTRP unmuted, HPOUTRN/LOUTRN muted. 01 HPOUTLP/LOUTLP muted, HPOUTLN/LOUTLN unmuted. 10 HPOUTLP/LOUTLP unmuted, HPOUTLN/LOUTLN muted. Using 16-bit serial input/output limits device performance.

Table 87. Bit Descriptions for SAI_0 00 TDM, I2S—data delayed from edge of LRCLK by 1 BCLK cycle. 01 TDM, left justified—data synchronized to edge of LRCLK. 10 Right justified, 24-bit data. 11 Right justified, 16-bit data. 00 Stereo (I2S, left justified, right justified). Using 16-bit serial input/output limits device performance. Table 88. Bit Descriptions for SAI_1

0 24-bit data in each TDM channel. 1 16-bit data in each TDM channel. 1 Pulse—LRCLK is a single BCLK cycle wide pulse. 0 50%: when LRCLK goes low and then high, pulse mode is short positive pulse. 1 50%: when LRCLK goes high and then low, pulse mode is short negative pulse. 0 Data changes on falling edge. 1 Data changes on rising edge. This register is for use only in TDM mode. Table 89. Bit Descriptions for SOUT_CONTROL0

Table 90. Bit Descriptions for PDM_OUT

control bits while the PDM channel is operating and transmitting audio. 01 PDM left signal in both PDM channels. 10 PDM right signal in both PDM channels. Table 91. Bit Descriptions for PDM_PATTERN is operating and transmitting the pattern. Table 92. Bit Descriptions for MODE_MP0

10000 Push-button volume up. 10001 Push-button volume down. Table 93. Bit Descriptions for MODE_MP1 10000 Push-button volume up. 10001 Push-button volume down.

10001: Push-button volume down. 10000: Push-button volume up. Table 94. Bit Descriptions for MODE_MP2 10000 Push-button volume up. 10001 Push-button volume down. 10001: Push-button volume down. 10000: Push-button volume up. Table 95. Bit Descriptions for MODE_MP3

10000 Push-button volume up. 10001 Push-button volume down. 10001: Push-button volume down. 10000: Push-button volume up. 0/Digital Microphone Input Channel 1. Table 96. Bit Descriptions for MODE_MP4 00000 Digital Microphone Input Channel 0/Digital Microphone Input Channel 1.

10000 Push-button volume up. 10001 Push-button volume down. Table 97. Bit Descriptions for MODE_MP5 00000 Digital Microphone Input Channel 2/Digital Microphone Input Channel 3. 10000 Push-button volume up. 10001 Push-button volume down.

Table 98. Bit Descriptions for MODE_MP6 10000 Push-button volume up. 10001 Push-button volume down. button volume control is initialized to −96 dB.

Table 99. Bit Descriptions for PB_VOL_SET this register attenuates the level by 1.5 dB, from 0 dB to −46.5 dB. Table 100. Bit Descriptions for PB_VOL_CONV

Table 101. Bit Descriptions for DEBOUNCE_MODE

Table 102. Bit Descriptions for OP_STAGE_CTRL 0 Right output in line output mode. 1 Right output in headphone mode.

4 HP_EN_L Sets the left channel in line output or headphone mode 0x0 R/W

0 Left output in line output mode. 1 Left output in headphone output mode. setting HP_MUTE_R in the OP_STAGE_MUTES register to 00. 00 HPOUTRN/LOUTRN and HPOUTRP/LOUTRP outputs enabled. 01 HPOUTRN/LOUTRN enabled, HPOUTRP/LOUTRP disabled. 10 HPOUTRN/LOUTRN disabled, HPOUTRP/LOUTRP enabled. 11 Right output stages powered down. setting HP_MUTE_L in the OP_STAGE_MUTES register to 00. 00 HPOUTLN/LOUTLN and HPOUTLP/LOUTLP outputs enabled. 01 HPOUTLN/LOUTLN enabled, HPOUTLP/LOUTLP disabled. 10 HPOUTLN/LOUTLN disabled, HPOUTLP/LOUTLP enabled. 11 Left output stages powered down.

Table 103. Bit Descriptions for DECIM_PWR_MODES

Table 104. Bit Descriptions for INTERP_PWR_MODES Table 105. Bit Descriptions for BIAS_CONTROL0 00 Normal operation (default).

currents result in higher performance. 00 Normal operation (default). 00 Normal operation (default). 00 Normal operation (default). Table 106. Bit Descriptions for BIAS_CONTROL1 currents result in higher performance. 00 Normal operation (default).

00 Normal operation (default). 00 Normal operation (default). Enable pull-up resistors for each digital pin. Table 107. Bit Descriptions for PAD_CONTROL0

Enable pull-up resistors for each digital pin. Table 108. Bit Descriptions for PAD_CONTROL1

Enable pull-down resistors for each digital pin. Table 109. Bit Descriptions for PAD_CONTROL2 Enable pull-down resistors for each digital pin.

Table 110. Bit Descriptions for PAD_CONTROL3 Table 111. Bit Descriptions for PAD_CONTROL4

Table 112. Bit Descriptions for PAD_CONTROL5

Table 113. Bit Descriptions for FAST_RATE (6.144 MHz) when CORE_FS = 11. Do not change this setting while the core is running. CORE_RUN must be set to 0 for this setting to be updated. The lowest interpolator latency is achieved with a zero-order hold (ZOH) selection. ZOH can be used for both 768 kHz and 192 kHz data. For 96 kHz data, use the linear interpolation to attain the lowest latency. Table 114. Bit Descriptions for DAC_CONTROL0 000 Both DAC0 and DAC1 set to compensated interpolation. 001 DAC0 set to ZOH, DAC1 set to compensated interpolation. 010 DAC0 set to compensated interpolation, DAC1 set to ZOH. 011 Both DAC0 and DAC1 set to ZOH. 100 DAC0 set to linear interpolation, DAC1 set to compensated interpolation. 101 DAC0 set to compensated interpolation, DAC1 set to linear interpolation. 110 Both DAC0 and DAC1 set to linear interpolation.

Table 115. Bit Descriptions for VOL_BYPASS

3.00 REF

Figure 79. 36-Ball Wafer Level Chip Scale Package [WLCSP] I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). registered trademarks are the property of their respective owners.