ADAU1761BCPZ

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SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL ADAU1761 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.

FEATURES

SigmaDSP 28-/56-bit, 50 MIPS digital audio processor Fully programmable with SigmaStudio graphical tool 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V 6 analog input pins, configurable for single-ended or differential inputs Flexible analog input/output mixers Stereo digital microphone input Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone output driver PLL supporting input clocks from 8 MHz to 27 MHz Analog automatic level control (ALC) Microphone bias reference voltage Analog and digital I/O: 1.8 V to 3.65 V I 2C and SPI control interfaces Digital audio serial data I/O: stereo and time-division multiplexing (TDM) modes Software-controllable clickless mute Software power-down GPIO pins for digital controls and outputs 32-lead, 5 mm × 5 mm LFCSP −40°C to +85°C operating temperature range

APPLICATIONS

Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products GENERAL DESCRIPTION The ADAU1761 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The SigmaDSP® core features 28-bit processing (56-bit double precision). The processor allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in the perceived audio quality through equalization, multiband compression, limiting, and third-party branded algorithms. The SigmaStudio™ graphical development tool is used to program the ADAU1761. This software includes audio processing blocks such as filters, dynamics processors, mixers, and low level DSP functions for fast development of custom signal flows. The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1761 includes a stereo digital microphone input. The ADAU1761 includes five high power output drivers (two differential and three single-ended), supporting stereo head- phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio. FUNCTIONAL BLOCK DIAGRAM HP JACK DETECTION REGULATOR INPUT MIXERS ALC MICROPHONE BIAS PLL LINN LINP LAUX JACKDET/MICIN RINP RINN RAUX MICBIAS LHP LOUTN LOUTP ADAU1761 RHP MONOOUT ROUTP ROUTN CM IOVDD DGND DVDDOUT AGND AVDD AVDD AGND OUTPUT MIXERS DAC DIGITAL FILTERS ADC DIGITAL FILTERS DAC DACADC ADC SDA/ COUT I2C/SPI CONTROL PORT SERIAL DATA INPUT/OUTPUT PORTS MCLK ADC_SDATA/ GPIO1 BCLK/ GPIO2 SCL/ CCLK ADDR1/ CDATA ADDR0/ CLATCH LRCLK/ GPIO3 DAC_SDATA/ GPIO0 07680-001 Figure 1.

Rev. C | Page 2 of 92 TABLE OF CONTENTS

Rev. C | Page 3 of 92

REVISION HISTORY

9/10—Rev. B to Rev. C 5/10—Rev. A to Rev. B 12/09—Rev. 0 to Rev. A Changes to Captions of Figure 15, Figure 16, Figure 18, and Changes to Power Reduction Modes Section and Changes to Jack Detection Section, Pop-and-Click Changes to Control Ports Section and I Changes to Serial Data Input/Output Ports Section Changes to Parameter RAM Section and Data RAM Section ..47 Changes to R2: Digital Microphone/Jack Detection Control, Changes to R15: Serial Port Control 0, 16,405 (0x4015) Changes to Table 51, R18: Converter Control 1, 16,408 Changes to Table 60, R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) Section, and Table 61...71 Changes to Table 62, R29: Playback Headphone Left Volume Changes to R42: Jack Detect Pin Control, 16,433 (0x4031) Changes to R57: DSP Sampling Rate Setting, 16,619 (0x40EB) Changes to R66: Clock Enable 1, 16,634 (0x40FA) Section 1/09—Revision 0: Initial Version

Rev. C | Page 4 of 92 SPECIFICATIONS Supply voltage (AVDD) = 3.3 V , TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V , VIL = 0.8 V , unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC performance excludes mixers and PGA ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Single-Ended Line Input −12 dB gain 83 kΩ 0 dB gain 21 kΩ 6 dB gain 10.5 kΩ PGA Inverting Inputs −12 dB gain 84.5 kΩ 0 dB gain 53 kΩ 35.25 dB gain 2 kΩ PGA Noninverting Inputs All gains 105 kΩ SINGLE-ENDED LINE INPUT Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 99 dB No Filter (RMS) AVDD = 1.8 V 91 dB AVDD = 3.3 V 96 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −90 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 99 dB No Filter (RMS) AVDD = 1.8 V 91 dB AVDD = 3.3 V 96 dB Gain per Step 3 dB Total Gain Range −12 +6 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −12 % Interchannel Isolation 68 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 65 dB 100 mV p-p @ 1 kHz 67 dB

Rev. C | Page 5 of 92 Parameter Test Conditions/Comments Min Typ Max Unit PSEUDO-DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −89 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Volume Control Step PGA gain 0.75 dB Volume Control Range PGA gain −12 +35.25 dB PGA Boost 20 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −14 % Interchannel Isolation 83 dB Common-Mode Rejection Ratio 100 mV rms, 1 kHz 65 dB 100 mV rms, 20 kHz 65 dB FULL DIFFERENTIAL PGA INPUT Differential PGA inputs Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −70 dB AVDD = 3.3 V −78 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Volume Control Step PGA gain 0.75 dB Volume Control Range PGA gain −12 +35.25 dB PGA Boost 20 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −14 %

Rev. C | Page 6 of 92 Parameter Test Conditions/Comments Min Typ Max Unit Interchannel Isolation 83 dB Common-Mode Rejection Ratio 100 mV rms, 1 kHz 65 dB 100 mV rms, 20 kHz 65 dB MICROPHONE BIAS MBIEN = 1 Bias Voltage 0.65 × AVDD AVDD = 1.8 V, MBI = 1 1.17 V AVDD = 3.3 V, MBI = 1 2.145 V 0.90 × AVDD AVDD = 1.8 V, MBI = 0 1.62 V AVDD = 3.3 V, MBI = 0 2.97 V Bias Current Source AVDD = 3.3 V, MBI = 0, MPERF = 1 3 mA Noise in the Signal Bandwidth AVDD = 3.3 V, 1 kHz to 20 kHz MBI = 0, MPERF = 0 42 nV/√Hz MBI = 0, MPERF = 1 85 nV/√Hz MBI = 1, MPERF = 0 25 nV/√Hz MBI = 1, MPERF = 1 37 nV/√Hz DIGITAL-TO-ANALOG CONVERTERS DAC performance excludes mixers and headphone amplifier DAC Resolution All DACs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB DAC TO LINE OUTPUT Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.50 (1.41) V rms (V p-p) AVDD = 3.3 V 0.92 (2.60) V rms (V p-p) Analog Volume Control Step Line output volume control 0.75 dB Analog Volume Control Range Line output volume control −57 1 +6 dB Mute Attenuation −87 dB Dynamic Range 20 Hz to 20 kHz, −60 dB input, line output mode With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 101 dB No Filter (RMS) AVDD = 1.8 V 93.5 dB AVDD = 3.3 V 98 dB Total Harmonic Distortion + Noise −1 dBFS, line output mode dB AVDD = 1.8 V −90 dB AVDD = 3.3 V −92 dB Signal-to-Noise Ratio Line output mode With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 101 dB No Filter (RMS) AVDD = 1.8 V 93.5 dB AVDD = 3.3 V 98 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 56 dB 100 mV p-p @ 1 kHz 70 dB Gain Error 3 % Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB

Rev. C | Page 7 of 92 Parameter Test Conditions/Comments Min Typ Max Unit DAC TO HEADPHONE/EARPIECE OUTPUT PO = output power per channel Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.50 (1.41) V rms (V p-p) AVDD = 3.3 V 0.92 (2.60) V rms (V p-p) Total Harmonic Distortion + Noise −4 dBFS 16 Ω load AVDD = 1.8 V, PO = 6.4 mW −76 dB AVDD = 3.3 V, PO = 21.1 mW −82 dB 32 Ω load AVDD = 1.8 V, PO = 3.8 mW −82 dB AVDD = 3.3 V, PO = 10.6 mW −82 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 56 dB 100 mV p-p @ 1 kHz 67 dB Interchannel Isolation 1 kHz, 0 dBFS input signal, 32 Ω load, AVDD = 3.3 V Referred to GND 73 dB Referred to CM (capless headphone mode) 50 dB REFERENCE Common-Mode Reference Output CM pin AVDD/2 V POWER SUPPLY SPECIFICATIONS Table 2. Parameter Test Conditions/Comments Min Typ Max Unit SUPPLIES Voltage DVDDOUT 1.56 V AVDD 1.8 3.3 3.65 V IOVDD 1.63 3.3 3.65 V Digital I/O Current (IOVDD = 1.8 V) 20 pF capacitive load on all digital pins Slave Mode fS = 48 kHz 0.25 mA f S = 96 kHz 0.48 mA f S = 8 kHz 0.07 mA Master Mode fS = 48 kHz 0.62 mA f S = 96 kHz 1.23 mA f S = 8 kHz 0.11 mA Digital I/O Current (IOVDD = 3.3 V) 20 pF capacitive load on all digital pins Slave Mode fS = 48 kHz 0.48 mA f S = 96 kHz 0.9 mA f S = 8 kHz 0.13 mA Master Mode fS = 48 kHz 1.51 mA f S = 96 kHz 3 mA f S = 8 kHz 0.27 mA Analog Current (AVDD) See Table 3

Rev. C | Page 8 of 92 TYPICAL CURRENT CONSUMPTION Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2. Table 3. Operating Voltage Audio Path Clock Generation Typical AVDD Current Consumption (mA) Direct MCLK 5.24 Record stereo differential to ADC Integer PLL 6.57 Direct MCLK 5.55 AVDD = IOVDD = 3.3 V DAC stereo playback to line output (10 kΩ) Integer PLL 6.90 Direct MCLK 55.5 DAC stereo playback to headphone (16 Ω) Integer PLL 56.8 Direct MCLK 30.9 DAC stereo playback to headphone (32 Ω) Integer PLL 32.25 Direct MCLK 56.75 DAC stereo playback to capless headphone (32 Ω) Integer PLL 58 Direct MCLK 1.9 Record aux stereo bypass to line output (10 kΩ) Integer PLL 3.3 Direct MCLK 4.25 Record stereo differential to ADC Integer PLL 5.55 Direct MCLK 4.7 AVDD = IOVDD = 1.8 V DAC stereo playback to line output (10 kΩ) Integer PLL 5.7 Direct MCLK 30.81 DAC stereo playback to headphone (16 Ω) Integer PLL 32 Direct MCLK 18.3 DAC stereo playback to headphone (32 Ω) Integer PLL 19.5 Direct MCLK 32.6 DAC stereo playback to capless headphone (32 Ω) Integer PLL 33.7 Direct MCLK 1.9 Record aux stereo bypass to line output (10 kΩ) Integer PLL 3.07

Rev. C | Page 9 of 92 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC input @ 0 dBFS. In Table 4, the mixer boost and power management conditions are set for MXBIAS[1:0], ADCBIAS[1:0], HPBIAS[1:0], and DACBIAS[1:0]. RBIAS[1:0] and PBIAS[1:0] do not have an extreme power saving mode and are therefore set for power saving mode in the extreme power saving rows in Table 4. Table 4. Operating Voltage Power Management Setting Mixer Boost Setting Typical AVDD Current Consumption (mA) Typical ADC THD + N (dB) Typical Line Output THD + N (dB) Normal operation 9.6 −91 −92.5 Normal (default) Boost Level 1 9.75 −91.5 −92.5 Boost Level 2 9.92 −91.5 −92.5 Boost Level 3 10.25 −91.5 −92.5 Normal operation 7.09 −84.5 −87 Extreme power saving Boost Level 1 7.19 −84.8 −87.1 Boost Level 2 7.29 −84.8 −87.1 Boost Level 3 7.49 −85 −87.1 Normal operation 7.67 −89.5 −90 Power saving Boost Level 1 7.77 −89.5 −90 Boost Level 2 7.86 −89.8 −90 Boost Level 3 8.07 −89.8 −90 Normal operation 10.55 −91 −93.5 Enhanced performance Boost Level 1 10.74 −91 −93.5 Boost Level 2 10.93 −91 −93.5 AVDD = IOVDD = 3.3 V Boost Level 3 11.33 −91 −93.5 Normal operation 8.1 −88 −91.2 Normal (default) Boost Level 1 8.26 −88 −91.2 Boost Level 2 8.41 −88 −91.2 Boost Level 3 8.73 −88 −91.2 Normal operation 5.73 −85 −86 Extreme power saving Boost Level 1 5.82 −85.4 −86 Boost Level 2 5.91 −85.5 −86 Boost Level 3 6.1 −85.5 −86 Normal operation 6.27 −86 −89.4 Power saving Boost Level 1 6.36 −86.1 −89.5 Boost Level 2 6.46 −86.3 −89.5 Boost Level 3 6.65 −86.3 −89.5 Normal operation 9.01 −88 −91.5 Enhanced performance Boost Level 1 9.2 −88 −91.5 Boost Level 2 9.38 −88 −91.5 AVDD = IOVDD = 1.8 V Boost Level 3 9.76 −88 −91.5

Rev. C | Page 10 of 92 DIGITAL FILTERS Table 5. Parameter Mode Factor Min Typ Max Unit ADC DECIMATION FILTER All modes, typ @ 48 kHz Pass Band 0.4375 fS 21 kHz Pass-Band Ripple ±0.015 dB Transition Band 0.5 fS 24 kHz Stop Band 0.5625 fS 27 kHz Stop-Band Attenuation 67 dB Group Delay 22.9844/fS 479 μs DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 fS 22 kHz 96 kHz mode, typ @ 96 kHz 0.3646 fS 35 kHz Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB 96 kHz mode, typ @ 96 kHz ±0.05 dB Transition Band 48 kHz mode, typ @ 48 kHz 0.5 fS 24 kHz 96 kHz mode, typ @ 96 kHz 0.5 fS 48 kHz Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 fS 26 kHz 96 kHz mode, typ @ 96 kHz 0.6354 fS 61 kHz Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 69 dB 96 kHz mode, typ @ 96 kHz 68 dB Group Delay 48 kHz mode, typ @ 48 kHz 25/fS 521 μs 96 kHz mode, typ @ 96 kHz 11/fS 115 μs DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 3.3 V ± 10%. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit INPUT SPECIFICATIONS Input Voltage High (VIH) 0.7 × IOVDD V Input Voltage Low (VIL) 0.3 × IOVDD V Input Leakage Pull-Ups/Pull-Downs Disabled IIH @ VIH = 3.3 V −0.17 +0.17 μA I IL @ VIL = 0 V −0.17 +0.17 μA I IL @ VIL = 0 V (MCLK pin) −13.5 −0.5 μA Pull-Ups Enabled IIH @ VIH = 3.3 V −0.7 +0.7 μA I IL @ VIL = 0 V −13.5 −0.5 μA Pull-Downs Enabled IIH @ VIH = 3.3 V 2.7 8.3 μA I IL @ VIL = 0 V −0.18 +0.18 μA Input Capacitance 5 pF OUTPUT SPECIFICATIONS Output Voltage High (VOH) I OH = 2 mA @ 3.3 V, 0.85 mA @ 1.8 V 0.8 × IOVDD V Output Voltage Low (VOL) I OL = 2 mA @ 3.3 V, 0.85 mA @ 1.8 V 0.1 × IOVDD V

Table 7. Digital Timing tMP 74 488 ns MCLK period, 256 × fS mode. tMP 37 244 ns MCLK period, 512 × fS mode. tMP 24.7 162.7 ns MCLK period, 768 × fS mode. tMP 18.5 122 ns MCLK period, 1024 × fS mode. tBIL 5 ns BCLK pulse width low. tBIH 5 ns BCLK pulse width high. tLIS 5 ns LRCLK setup. Time to BCLK rising. tLIH 5 ns LRCLK hold. Time from BCLK rising. tSIS 5 ns DAC_SDATA setup. Time to BCLK rising. tSIH 5 ns DAC_SDATA hold. Time from BCLK rising. tSODM 50 ns ADC_SDATA delay. Time from BCLK falling in master mode. fCCLK 10 MHz CCLK frequency. tCCPL 10 ns CCLK pulse width low. tCCPH 10 ns CCLK pulse width high. tCLS 5 ns CLATCH setup. Time to CCLK rising. tCLH 10 ns CLATCH hold. Time from CCLK rising. tCLPH 10 ns CLATCH pulse width high. tCDS 5 ns CDATA setup. Time to CCLK rising. tCDH 5 ns CDATA hold. Time from CCLK rising. tCOD 50 ns COUT three-stated. Time from CLATCH rising. tSCS 0.6 μs Setup time; relevant for repeated start condition. tSCH 0.6 μs Hold time. After this period, the first clock is generated. tBFT 0.6 μs Bus-free time. Time between stop and start. DIGITAL MICROPHONE RLOAD = 1 MΩ, CLOAD = 14 pF. tDCF 10 ns Digital microphone clock fall time. tDCR 10 ns Digital microphone clock rise time. tDDV 22 30 ns Digital microphone delay time for valid data. tDDH 0 12 ns Digital microphone delay time for data three-stated.

Table 9. Thermal Resistance

24 DVDDOUT

23 AVDD

22 AGND

21 MONOOUT

20 LHP

19 RHP

18 LOUTP

17 LOUTN

1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE

Figure 7. Pin Configuration Table 10. Pin Function Descriptions which also sets the highest input voltage that should be seen on the digital input pins. with a 100 nF capacitor and a 10 μF capacitor. 2 MCLK D_IN External Master Clock Input. 3 ADDR0/CLATCH D_IN I 2C Address Bit 0 (ADDR0). 4 JACKDET/MICIN D_IN Detect Insertion/Removal of Headphone Plug (JACKDET). Digital Microphone Stereo Input (MICIN). 5 MICBIAS A_OUT Bias Voltage for Electret Microphone. 6 LAUX A_IN Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2. be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs. from CM (for example, the noninverting input of an op amp). locally to AGND with a 100 nF capacitor. 9 AGND PWR Analog Ground. The AGND and DGND pins can be tied together on a common ground plane. AGND should be decoupled locally to AVDD with a 100 nF capacitor. 10 LINP A_IN Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2. 11 LINN A_IN Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2. 12 RINP A_IN Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2. 13 RINN A_IN Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2. 14 RAUX A_IN Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2. 15 ROUTP A_OUT Right Line Output, Positive. Biased at AVDD/2. 16 ROUTN A_OUT Right Line Output, Negative. Biased at AVDD/2. 17 LOUTN A_OUT Left Line Output, Negative. Biased at AVDD/2. 18 LOUTP A_OUT Left Line Output, Positive. Biased at AVDD/2.

Rev. C | Page 16 of 92 Pin No. Mnemonic Type1 Description 19 RHP A_OUT Right Headphone Output. Biased at AVDD/2. 20 LHP A_OUT Left Headphone Output. Biased at AVDD/2. 21 MONOOUT A_OUT Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono output. 22 AGND PWR Analog Ground. The AGND and DGND pins can be tied together on a common ground plane. AGND should be decoupled locally to AVDD with a 100 nF capacitor. 23 AVDD PWR 1.8 V to 3.3 V Analog Supply for ADC, Output Driver, and Input to Digital Supply Regulator. This pin should be decoupled locally to AGND with a 100 nF capacitor. 24 DVDDOUT PWR Digital Core Supply Decoupling Point. The digital supply is generated from an on-board regulator and does not require an external supply. DVDDOUT should be decoupled to DGND with a 100 nF capacitor and a 10 μF capacitor. 25 DGND PWR Digital Ground. The AGND and DGND pins can be tied together on a common ground plane. DGND should be decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 μF capacitors. 26 ADC_SDATA/GPIO1 D_IO ADC Serial Output Data (ADC_SDATA). General-Purpose Input/Output 1 (GPIO1). 27 DAC_SDATA/GPIO0 D_IO DAC Serial Input Data (DAC_SDATA). General-Purpose Input/Output 0 (GPIO0). 28 BCLK/GPIO2 D_IO Serial Data Port Bit Clock (BCLK). General-Purpose Input/Output 2 (GPIO2). 29 LRCLK/GPIO3 D_IO Serial Data Port Frame Clock (LRCLK). General-Purpose Input/Output 3 (GPIO3). 30 ADDR1/CDATA D_IN I2C Address Bit 1 (ADDR1). SPI Data Input (CDATA). 31 SDA/COUT D_IO I2C Data (SDA). This pin is a bidirectional open-collector input/output. The line connected to this pin should have a 2 kΩ pull-up resistor. SPI Data Output (COUT). This pin is used for reading back registers and memory locations. It is three-state when an SPI read is not active. 32 SCL/CCLK D_IN I2C Clock (SCL). This pin is always an open-collector input when in I2C control mode. The line connected to this pin should have a 2 kΩ pull-up resistor. SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions. EP Exposed Pad Exposed Pad. The exposed pad is connected internally to the ADAU1761 grounds. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. See the Exposed Pad PCB Design section for more information. 1 A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, PWR = power.

Figure 26. System Block Diagram

Figure 27. System Block Diagram with Analog Microphones

Figure 28. System Block Diagram with Digital Microphones and SSM2306 Class-D Speaker Driver

Rev. C | Page 23 of 92 THEORY OF OPERATION The ADAU1761 is a low power audio codec with an integrated stream-oriented DSP core, making it an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo DAC each have an SNR of at least +98 dB and a THD + N of at least −90 dB. The serial data port is compatible with I 2S, left-justified, right- justified, and TDM modes for interfacing to digital audio data. The operating voltage range is 1.8 V to 3.65 V , with an on-board regulator generating the internal digital supply voltage. The record signal path includes very flexible input configurations that can accept differential and single-ended analog microphone inputs as well as a digital microphone input. A microphone bias pin provides seamless interfacing to electret microphones. Input configurations can accept up to six single-ended analog signals or variations of stereo differential or stereo single-ended signals with two additional auxiliary single-ended inputs. Each input signal has its own programmable gain amplifier (PGA) for volume adjustment and can be routed directly to the playback path output mixers, bypassing the ADCs. An automatic level control (ALC) can also be implemented to keep the recording volume constant. The ADCs and DACs are high quality, 24-bit Σ-Δ converters that operate at selectable 64× or 128× oversampling ratios. The base sampling rate of the converters is set by the input clock rate and can be further scaled with the converter control register settings. The converters can operate at sampling frequencies from 8 kHz to 96 kHz. The ADCs and DACs also include very fine-step digital volume controls. The playback path allows input signals and DAC outputs to be mixed into various output configurations. Headphone drivers are available for a stereo headphone output, and the other output pins are capable of differentially driving an earpiece speaker. Capless headphone outputs are possible with the use of the mono output as a virtual ground connection. The stereo line outputs can be used as either single-ended or differential outputs and as an optional mix-down mono output. The DSP core introduces many features that make this codec unique and optimized for audio processing. The program and parameter RAMs can be loaded with custom audio processing signal flow built using the SigmaStudio graphical programming software from Analog Devices, Inc. The values stored in the parameter RAM control individual signal processing blocks, such as equalization filters, dynamics processors, audio delays, and mixer levels. The SigmaStudio software is used to program and control the SigmaDSP through the control port. Along with designing and tuning a signal flow, the tools can be used to configure all of the DSP registers. The SigmaStudio graphical interface allows any- one with digital or analog audio processing knowledge to easily design DSP signal flow and port it to a target application. At the same time, it provides enough flexibility and programmability for an experienced DSP programmer to have in-depth control of the design. In SigmaStudio, the user can connect graphical blocks (such as biquad filters, dynamics processors, mixers, and delays), compile the design, and load the program and parameter files into the ADAU1761 memory through the control port. Signal processing blocks available in the provided libraries include the following:

• Enhanced stereo capture
• Single- and double-precision biquad filters
• FIR filters
• Dynamics processors with peak or rms detection for mono and multichannel dynamics
• Mixers and splitters
• Tone and noise generators
• Fixed and variable gain
• Loudness
• Delay
• Stereo enhancement
• Dynamic bass boost
• Noise and tone sources
• Level detectors Additional processing blocks are always being developed. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices (www.analog.com) for information about licensing these algorithms. The ADAU1761 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 8 MHz to 27 MHz. The ADAU1761 is provided in a small, 32-lead, 5 mm × 5 mm LFCSP with an exposed bottom pad.

approach to the proper initiation of the system.

1. Apply power to the ADAU1761.
2. Lock the PLL to the input clock (if using the PLL).
3. Load the register settings.

AVDD, the POR takes approximately 14 ms. Figure 29. Power-On Reset Sequence immediately after the PLL is locked. Table 11. PLL Lock Times the DACs, the PLL, and the DSP core. section for graphs of these filters. capacitor should be connected between this pin and DGND. capacitor and a 10 μF capacitor. should be adjusted accordingly.

Rev. C | Page 25 of 92 Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisition period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1761 can be started by asserting the core clock enable bit (COREN) in Register R0 (clock control register, Address 0x4000). This bit enables the core clock to all the internal blocks of the ADAU1761. PLL Lock Acquisition During the lock acquisition period, only Register R0 (Address 0x4000) and Register R1 (Address 0x4002) are accessible through the control port. Because all other registers require a valid master clock for reading and writing, do not attempt to access any other register. Any read or write is prohibited until the core clock enable bit (COREN) and the lock bit are both asserted. To program the PLL during initialization or reconfiguration of the clock setting, the following procedure must be followed: 1. Power down the PLL. 2. Reset the PLL control register. 3. Start the PLL. 4. Poll the lock bit. 5. Assert the core clock enable bit after the PLL lock is acquired. The PLL control register (Register R1, Address 0x4002) is a 48-bit register where all bits must be written with a single continuous write to the control port.

Figure 30. Clock Tree Diagram pin clock rate and the desired base sampling frequency. Table 12. Clock Control Register (Register R0, Address 0x4000)

3 CLKSRC 0: Direct from MCLK pin (default)

0 COREN 0: Core clock disabled (default)

register, Address 0x40F8) using the SPSR[2:0] bits. Table 13. 48 kHz Base Sampling Rate Divisions Table 14. 44.1 kHz Base Sampling Rate Divisions accept input frequencies in the range of 8 MHz to 27 MHz. single continuous write to the control port. Figure 31. PLL Block Diagram In integer mode, the values set for N and M are ignored. (R + (N/M)) multiple of the PLL output. 48 kHz sampling rates can be found in Table 16 and Table 17. values and MCLK frequencies. Table 15. PLL Control Register (Register R1, Address 0x4002)

8 Type PLL operation mode

1 Lock PLL lock (read-only bit)

0 PLLEN PLL enable

Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS) Table 17. Fractional PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS) Table 18. Integer PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)

Figure 32. Record Signal Path input pins should be connected to CM. not through the PGA are inverted. The ADCs are noninverting.

this register, the MICBIAS output can be enabled or disabled. digital microphone interface and signal routing. 128× (selected by Bit 3 in Register R17, Address 0x4017). The full-scale input to the ADCs (0 dBFS) depends on AVDD. full-scale analog input will output a digital signal at −1.38 dBFS. This gain offset is built into the ADAU1761 to prevent clipping. The full-scale input level scales linearly with the level of AVDD. value corresponds to the signal level at the pins, 0 dBFS. differential amplifier, which corresponds to −6 dBFS at each pin. Signal levels above the full-scale value cause the ADCs to clip. Figure 36. Digital Microphone Interface Block Diagram corner frequency of this high-pass filter is 2 Hz.

complete, so some small background noise will still exist. Figure 43. Noise Gate Mode 3 (Analog Fade/Digital Mute) Figure 42. Noise Gate Mode 2 (Analog Fade)

Figure 44. Playback Signal Path be put into HP mode to drive headphones or earpiece speakers. The analog output pins are biased at AVDD/2. Signals are inverted through the mixers and volume controls. ended mono output is inverted. The DACs are noninverting.

• Mix signals from the record path and the DACs.
• Mix or swap the left and right channels.
• Mix a mono signal or generate a common-mode output. Mixer 3 and Mixer 4 are dedicated to mixing signals from the record path and the DACs. Each of these two mixers can accept signals from the left and right DACs, the left and right input mixers, and the dedicated channel auxiliary input. Signals coming from the record path can be boosted or cut before the playback mixer. For example, the MX4G2[3:0] bits set the gain from the output of Mixer 2 (right record channel) to the input of Mixer 4, hence the naming convention. Signals coming from the DACs have digital volume attenu- ation controls set in Register R20 (left input digital volume register, Address 0x401A) and Register R21 (right input digital volume register, Address 0x401B).

functionality of the JACKDET/MICIN pin. functions cannot be used simultaneously. LOUTN and ROUTN should be left unconnected. suppression register, Address 0x4028). (Mixer 6) line output control register, Address 0x4021). analog outputs after the changes are made. Figure 48. Differential Line Output Configuration

• I2C control
• SPI control The ADAU1761 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Both ports can be used to set the registers. The part defaults to I2C mode, but it can be put into SPI control mode by pulling the CLATCH pin low three times. The control port is capable of full read/write operation for all addressable registers. The ADAU1761 must have a valid master clock in order to write to all registers except for Register R0 (Address 0x4000) and Register R1 (Address 0x4002). All addresses can be accessed in both a single-address mode or a burst mode. The first byte (Byte 0) of a control port write contains the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) together form the subaddress of the register location within the ADAU1761. This subaddress must be two bytes long because the memory locations within the ADAU1761 are directly addressable and their sizes exceed the range of single-byte addressing. All subsequent bytes (starting with Byte 3) contain the data, such as control port data, program data, or parameter data. The number of bytes per word depends on the type of data that is being written. The ADAU1761 has several mechanisms for updating signal pro- cessing parameters in real time without causing pops or clicks. If large blocks of data need to be downloaded, the output of the DSP core can be halted (using the DSPRUN bit in the DSP run register, Address 0x40F6), new data can be loaded, and the device can be restarted. This is typically done during the booting sequence at start-up or when loading a new program into RAM. The control port pins are multifunctional, depending on the mode in which the part is operating. Table 20 describes these multiple functions.

Table 20. Control Port Pin Functions written immediately without sending its two-byte address. exception of the PLL control register, which is six bytes wide. manually for each address in a burst write. and a read returns a single byte 0x00. between the ADAU1761 and the system I2C master controller. operation, and Logic Level 0 corresponds to a write operation. Table 21. ADAU1761 I2C Address and Read/Write Byte Format should not be higher than IOVDD (1.8 V to 3.3 V).

Figure 58. I2S Mode—16 Bits to 24 Bits per Channel Figure 59. Left-Justified Mode—16 Bits to 24 Bits per Channel Figure 60. Right-Justified Mode—16 Bits to 24 Bits per Channel

32 BCLKs

256 BCLKs

Figure 61. TDM 8 Mode Figure 62. TDM 8 Mode with Pulse Word Clock

Rev. C | Page 45 of 92 DSP CORE SIGNAL PROCESSING The ADAU1761 is designed to provide all audio signal processing functions commonly used in stereo or mono low power record and playback systems. The signal processing flow is designed using the SigmaStudio software, which allows graphical entry and real-time control of all signal processing functions. Many of the signal processing functions are coded using full, 56-bit, double-precision arithmetic data. The input and output word lengths of the DSP core are 24 bits. Four extra headroom bits are used in the processor to allow internal gains of up to 24 dB without clipping. Additional gains can be achieved by initially scaling down the input signal in the DSP signal flow. ARCHITECTURE The DSP core consists of a simple 28-/56-bit multiply-accumulate (MAC) unit with two sources: a data source and a coefficient source. The data source can come from the data RAM, a ROM table of commonly used constant values, or the audio inputs to the core. The coefficient source can come from the parameter RAM or from a ROM table of commonly used constant values. The two sources are multiplied in a 28-bit fixed-point multiplier and then the signal is input to the 56-bit adder; the result is usually stored in one of three 56-bit accumulator registers. The accumu- lators can be output from the core (in 28-bit format) or can optionally be written back into the data or parameter RAMs. COEFFICIENT SOURCE (PARAMETER RAM, ROM CONSTANTS) DATA OPERATIONS (ACCUMULATORS (3), dB CONVERSION, BIT OPERATORS, BIT SHIFTER, ...) DATA SOURCE (DATA RAM, ROM CONSTANTS, AUDIO INPUTS) OUTPUTS TRUNCATOR TRUNCATOR56 2828 07680-067 Figure 67. Simplified DSP Core Architecture waits for the next audio frame to clock into the core. The SigmaDSP core was designed specifically for audio processing and therefore includes several features intended for maximizing efficiency. These include hardware decibel conversion and audio- specific ROM constants. STARTUP Before the DSPRUN bit is set or any settings are written to the parameter RAM, the DSP core must be enabled by setting the DSPEN bit in Register R61 (Address 0x40F5). The following steps should be performed every time that a new program is loaded to the SigmaDSP core, or any time that the DSPRUN bit is disabled and reenabled. 1. Set the DSPSR[3:0] bits in Register R57 (Address 0x40EB) to 1111 (none). 2. Set the DSPRUN bit in Register R62 (Address 0x40F6) to 0. 3. Download the rest of the registers, the program RAM, and the parameter RAM. 4. Set the DSPRUN bit in Register R62 to 1. 5. Set the DSPSR[3:0] bits in Register R57 to the operational setting (default value is 0001). Changing any register setting or RAM can cause pops and clicks on the analog outputs. To avoid these pops and clicks, mute the appropriate outputs using Register R29 to Register R32 (Address 0x4023 to Address 0x4026). Unmute the analog out- puts after the startup procedure is completed.

Table 26. RAM Map and Read/Write Modes per frame based on the sample rate of the signals in the core. no-operation (NOP) commands. data format of the parameter RAM is twos complement, 5.23. writes, resulting in pops and clicks in the audio stream. bit has been set in Register R61 (Address 0x40F5). chip address, a read/write bit, and a 16-bit RAM/register address. on the address given in the first three bytes. even across the boundaries of the different RAMs and registers.

Table 27. Parameter RAM Read/Write Format (Single Address) Table 28. Parameter RAM Block Read/Write Format (Burst Mode) Table 29. Program RAM Read/Write Format (Single Address) Table 30. Program RAM Block Read/Write Format (Burst Mode) a mix of old and new parameters. initialization code, fills the first 39 locations in program RAM. Table 31. Software Safeload Parameter RAM Defaults standard signal processing algorithms have five parameters or less. an offset of −1). This designates the first address to be written. Address 0x000A, the target address is 0x0009. also triggers the safeload write to occur in the next audio frame. is not observed, the downloaded data is corrupted.

register (Register R60, Address 0x40F4). and button press confirmation. many or all of the GPIO pins when designing the application. Address 0x40C6 to Address 0x40C9). settings of the LSB of these 4-byte-wide memory locations. Table 32. GPIOx Pin Memory Settings (Set from Control Port)

Table 33. Register Map

All registers except for the PLL control register are 1-byte write and read registers. Table 34. Clock Control Register 3 CLKSRC Clock source select. 0 = direct from MCLK pin (default). automatically set to 1024 × fS. 0 COREN Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled). 0 = core clock disabled (default).

0 M[15:8]

1 M[7:0]

2 N[15:8]

3 N[7:0]

4 Reserved R[3:0] X[1:0] Type

5 Reserved Lock PLLEN

Table 35. PLL Control Register 0 [7:0] M[15:8] PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number. 1 [7:0] M[7:0] PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number. 2 [7:0] N[15:8] PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number. 3 [7:0] N[7:0] PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number. 4 [6:3] R[3:0] PLL integer setting. 4 [2:1] X[1:0] PLL input clock divider. 4 0 Type Type of PLL. When set to integer mode, the values of M and N are ignored. 5 1 Lock PLL lock. This read-only bit is flagged when the PLL has finished locking.

Table 36. Digital Microphone/Jack Detection Control Register [7:6] JDDB[1:0] Jack detect debounce time.

00 Jack detect off (default)

01 Jack detect on

10 Digital microphone input

0 JDPOL Jack detect polarity. Detects high or low signal. 0 = detect high signal (default). mode offers the highest performance with the trade-off of higher power consumption. Table 37. Record Power Management Register the boost level enhances the THD + N performance.

00 Normal operation (default)

01 Boost Level 1

10 Boost Level 2

11 Boost Level 3

[4:3] ADCBIAS[1:0] ADC bias control. Sets the bias current for the ADCs based on the mode of operation selected.

01 Extreme power saving

10 Enhanced performance

11 Power saving

[2:1] RBIAS[1:0] Record path bias control. Sets the bias current for the PGAs and mixers in the record path.

01 Reserved

This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1. Table 38. Record Mixer Left (Mixer 1) Control 0 Register [6:4] LINPG[2:0] Gain for a left channel single-ended input from the LINP pin, input to Mixer 1.

000 Mute (default)

[3:1] LINNG[2:0] Gain for a left channel single-ended input from the LINN pin, input to Mixer 1. 0 MX1EN Left channel mixer enable in the record path. Referred to as Mixer 1. 0 = mixer disabled (default).

record path. The left channel record mixer is referred to as Mixer 1. Table 39. Record Mixer Left (Mixer 1) Control 1 Register signal) and LINN (negative signal) pins.

00 Mute (default)

11 Reserved

[2:0] MX1AUXG[2:0] Left single-ended auxiliary input gain from the LAUX pin in the record path, input to Mixer 1.

Table 40. Record Mixer Right (Mixer 2) Control 0 Register [6:4] RINPG[2:0] Gain for a right channel single-ended input from the RINP pin, input to Mixer 2. [3:1] RINNG[2:0] Gain for a right channel single-ended input from the RINN pin, input to Mixer 2. 0 MX2EN Right channel mixer enable in the record path. Referred to as Mixer 2. 0 = mixer disabled (default).

record path. The right channel record mixer is referred to as Mixer 2. Table 41. Record Mixer Right (Mixer 2) Control 1 Register (positive signal) and RINN (negative signal) pins. [2:0] MX2AUXG[2:0] Right single-ended auxiliary input gain from the RAUX pin in the record path, input to Mixer 2. This register enables the differential path and sets the volume control for the left differential PGA input. Table 42. Left Differential Input Volume Control Register 1 LDMUTE Left differential input mute control. disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.

This register enables the differential path and sets the volume control for the right differential PGA input. Table 43. Right Differential Input Volume Control Register list of the volume settings. 1 RDMUTE Right differential input mute control. disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA. This register controls the MICBIAS pin settings for biasing electret type analog microphones. Table 44. Record Microphone Bias Control Register more current to the microphone. 0 = normal operation (default). 2 MBI Microphone voltage bias as a fraction of AVDD. 0 MBIEN Enables the MICBIAS output.

Table 45. ALC Control 0 Register and Register R9 (right differential input volume control).

11 Off

protects small signals from excessive amplification. right PGA amplifiers. DSP control allows the PGA gain to be set within the DSP or from external GPIO inputs. These bits must be off if manual control of the volume is desired.

000 Off (default)

001 Right only

010 Left only

011 Stereo

100 DSP control

101 Reserved

110 Reserved

111 Reserved

Table 46. ALC Control 1 Register distortion of low frequency signals. The hold time doubles with every 1-bit increase.

Table 47. ALC Control 2 Register the target. A typical setting for music recording is 384 ms, and a typical setting for voice recording is 24 ms.

Table 48. ALC Control 3 Register PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.

00 Hold PGA constant (default)

01 Mute ADC output (digital mute)

10 Fade to PGA minimum value (analog fade)

11 Fade then mute (analog fade/digital mute)

[4:0] NGTHR[4:0] Noise gate threshold. When the input signal falls below the threshold for 250 ms, the noise gate is activated. A 1 LSB increase corresponds to a −1.5 dB change. See Table 93 for a complete list of the threshold settings. Table 49. Serial Port Control 0 Register 6 SPSRS Serial port sampling rate source. 0 = converter rate set in Register R17 (default). 1 = DSP rate set in Register R57. 5 LRMOD LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide. 0 = 50% duty cycle (default). for the falling or rising edge of the LRCLK. [2:1] CHPF[1:0] Channels per frame sets the number of channels per LRCLK frame.

00 Stereo (default)

01 TDM 4

10 TDM 8

serial port slave in slave mode.

Table 50. Serial Port Control 1 Register [7:5] BPF[2:0] Number of bit clock cycles per LRCLK audio frame.

001 Reserved

4 ADTDM ADC serial audio data channel position in TDM mode. 3 DATDM DAC serial audio data channel position in TDM mode. 2 MSBP MSB position in the LRCLK frame. [1:0] LRDEL[1:0] Data delay from LRCLK edge (in BCLK units).

Table 51. Converter Control 0 Register [6:5] DAPAIR[1:0] On-chip DAC serial data selection in TDM 4 or TDM 8 mode.

00 First pair (default)

01 Second pair

10 Third pair

11 Fourth pair

4 DAOSR DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz. 3 ADOSR ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz. Table 52. Converter Control 1 Register [1:0] ADPAIR[1:0] On-chip ADC serial data selection in TDM 4 or TDM 8 mode.

Table 53. ADC Control Register 6 ADCPOL Invert input polarity. 5 HPF ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz. 4 DMPOL Digital microphone data polarity swap. the right channel on the falling edge of the clock. 1 = swap left and right channels. ADC_SDATA is expected to have left and right channels interleaved. 0 = digital microphone inputs off, ADCs enabled (default). 1 = digital microphone inputs enabled, ADCs off. [1:0] ADCEN[1:0] ADC enable.

00 Both off (default)

01 Left on

10 Right on

11 Both on

Table 54. Left Input Digital Volume Register complete list of the volume settings.

Table 55. Right Input Digital Volume Register complete list of the volume settings. Table 56. Playback Mixer Left (Mixer 3) Control 0 Register 6 MX3RM Mixer input mute. Mutes the right DAC input to the left channel playback mixer (Mixer 3). 5 MX3LM Mixer input mute. Mutes the left DAC input to the left channel playback mixer (Mixer 3). [4:1] MX3AUXG[3:0] Mixer input gain. Controls the left channel auxiliary input gain to the left channel playback mixer (Mixer 3).

0000 Mute (default)

Table 57. Playback Mixer Left (Mixer 3) Control 1 Register can be applied before the left playback mixer (Mixer 3). can be applied before the left playback mixer (Mixer 3).

Table 58. Playback Mixer Right (Mixer 4) Control 0 Register 6 MX4RM Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4). 5 MX4LM Mixer input mute. Mutes the left DAC input to the right channel playback mixer (Mixer 4). [4:1] MX4AUXG[3:0] Mixer input gain. Controls the right channel auxiliary input gain to the right channel playback mixer (Mixer 4).

Table 59. Playback Mixer Right (Mixer 4) Control 1 Register can be applied before the right playback mixer (Mixer 4). can be applied before the right playback mixer (Mixer 4).

Table 60. Playback L/R Mixer Left (Mixer 5) Line Output Control Register in the playback L/R mixer left (Mixer 5). the playback L/R mixer left (Mixer 5). Table 61. Playback L/R Mixer Right (Mixer 6) Line Output Control Register in the playback L/R mixer right (Mixer 6). the playback L/R mixer right (Mixer 6).

Table 62. Playback L/R Mixer Mono Output (Mixer 7) Control Register virtual ground in a capless headphone configuration.

00 Common-mode output (default)

Table 63. Playback Headphone Left Volume Control Register [7:2] LHPVOL[5:0] Headphone volume control for left channel, LHP output. Each 1-bit step corresponds to a 1 dB increase in volume. See Table 95 for a complete list of the volume settings. 1 LHPM Headphone mute for left channel, LHP output (active low). the HPMODE bit is set to 1, the headphone output is enabled.

Table 64. Playback Headphone Right Volume Control Register volume. See Table 95 for a complete list of the volume settings. 1 RHPM Headphone mute for right channel, RHP output (active low). 0 = enable line output (default). 1 = enable headphone output. Table 65. Playback Line Output Left Volume Control Register increase in volume. See Table 95 for a complete list of the volume settings. 1 LOUTM Line output mute for left channel, LOUTN and LOUTP outputs (active low). outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output).

Table 66. Playback Line Output Right Volume Control Register increase in volume. See Table 95 for a complete list of the volume settings. 1 ROUTM Line output mute for right channel, ROUTN and ROUTP outputs (active low). outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output). Table 67. Playback Mono Output Control Register 1 MONOM Mono output mute (active low). configuration, this bit should be set to 1 ( headphone output).

Table 68. Playback Pop/Click Suppression Register however, after they are charged, they can be put into low power operation. power; however, disabling the circuits increases the risk of pops and clicks. [2:1] ASLEW[1:0] Analog volume slew rate for playback volume controls. Table 69. Playback Power Management Register [7:6] HPBIAS[1:0] Headphone bias control. [5:4] DACBIAS[1:0] DAC bias control. [3:2] PBIAS[1:0] Playback path channel bias control. 1 PREN Playback right channel enable. 0 PLEN Playback left channel enable.

Table 70. DAC Control 0 Register channel, the right channel, or both channels.

01 Left channel in mono mode

10 Right channel in mono mode

11 Both channels in mono mode

5 DACPOL Invert input polarity of the DACs. 2 DEMPH DAC de-emphasis filter enable. The de-emphasis filter is designed for use with a sampling rate of 44.1 kHz only. [1:0] DACEN[1:0] DAC enable. Table 71. DAC Control 1 Register 0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings.

Table 72. DAC Control 2 Register 0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings. signals to a defined state when the signal source becomes three-state. Table 73. Serial Port Pad Control Register [7:6] ADCSDP[1:0] ADC_SDATA pad pull-up/pull-down configuration.

00 Pull-up

10 None (default)

11 Pull-down

[5:4] DACSDP[1:0] DAC_SDATA pad pull-up/pull-down configuration. [3:2] LRCLKP[1:0] LRCLK pad pull-up/pull-down configuration. [1:0] BCLKP[1:0] BCLK pad pull-up/pull-down configuration.

signals to a defined state when the signal source becomes three-state. Table 74. Control Port Pad Control 0 Register [7:6] CDATP[1:0] CDATA pad pull-up/pull-down configuration. [3:2] SCLP[1:0] SCL/CCLK pad pull-up/pull-down configuration. [1:0] SDAP[1:0] SDA/COUT pad pull-up/pull-down configuration. With IOVDD set to 3.3 V , the low and high drive strengths of the SDA/COUT pin are approximately 2.0 mA and 4.0 mA, respectively. mode may be useful for generating a stronger ACK pulse in I2C mode, if needed. Table 75. Control Port Pad Control 1 Register 0 SDASTR SDA/COUT pin drive strength.

With IOVDD set to 3.3 V , the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. the signal source becomes three-state. Table 76. Jack Detect Pin Control Register 5 JDSTR JACKDET/MICIN pin drive strength. [3:2] JDP[1:0] JACKDET/MICIN pad pull-up/pull-down configuration. the associated dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device. reactivated, without a wait period, by setting the dejitter window size to the default value of 3. Table 77. Dejitter Control Register [7:0] DEJIT[7:0] Dejitter window size.

on an external microcontroller, which triggers a rewrite of the corrupted memory. CRCEN bit low, fixing the error (presumably by reloading the program), and then setting the CRCEN bit high again. Table 78. Cyclic Redundancy Check Registers

pull-up is nominally 250 kΩ. The output CRC error and output watchdog error settings are sticky, that is, once set, they remain set until the ADAU1761 is reset. Table 79. GPIO Pin Functionality Bit Settings

0000 Input without debounce (default)

0100 Input with debounce (5 ms)

0101 Input with debounce (10 ms)

0110 Input with debounce (20 ms)

0111 Input with debounce (40 ms)

1000 Input controlled by I2C/SPI port

1001 Output set by I2C/SPI port, with pull-up

1010 Output set by I2C/SPI port, no pull-up

1011 Output set by DSP core, with pull-up

1100 Output set by DSP core, no pull-up

1101 Reserved

1110 Output CRC error (sticky)

1111 Output watchdog error (sticky)

Table 80. GPIO Pin Control Registers

must be enabled by setting the DOGEN bit high in Register R52 (Address 0x40D0). flag can also be read back over the control port from Register R56 (Address 0x40D4). Table 81. Watchdog Registers R52 16,592 0x40D0 DOGEN Watchdog enable bit. R56 16,596 0x40D4 DOGER Watchdog error (read-only bit). Table 82. DSP Sampling Rate Setting Register port sampling rate (set using the SPSR[2:0] bits in Register R64).

0111 Serial input data rate

1000 Serial output data rate

1111 None

Table 83. Serial Input Route Control Register from the DSP or from any TDM slot on the serial port.

0000 DSP to DACs [L, R] (default)

0001 Serial input [L0, R0] to DACs [L, R]

0010 Reserved

0011 Serial input [L1, R1] to DACs [L, R]

0100 Reserved

0101 Serial input [L2, R2] to DACs [L, R]

0110 Reserved

0111 Serial input [L3, R3] to DACs [L, R]

1000 Reserved

1001 Serial input [R0, L0] to DACs [L, R]

1010 Reserved

1011 Serial input [R1, L1] to DACs [L, R]

1100 Reserved

1101 Serial input [R2, L2] to DACs [L, R]

1110 Reserved

1111 Serial input [R3, L3] to DACs [L, R]

Table 84. Serial Output Route Control Register the DSP or to any TDM slot on the serial port.

0000 ADCs [L, R] to DSP (default)

0001 ADCs [L, R] to serial output [L0, R0]

0011 ADCs [L, R] to serial output [L1, R1]

0101 ADCs [L, R] to serial output [L2, R2]

0111 ADCs [L, R] to serial output [L3, R3]

1001 ADCs [L, R] to serial output [R0, L0]

1011 ADCs [L, R] to serial output [R1, L1]

1101 ADCs [L, R] to serial output [R2, L2]

1111 ADCs [L, R] to serial output [R3, L3]

these pins are configured as GPIO interfaces to the SigmaDSP . If these bits are set to 0, they are configured as serial data I/O port pins. Table 85. Serial Data/GPIO Pin Configuration Register 3 LRGP3 LRCLK or GPIO3 pin configuration select. 0 = LRCLK enabled (default). 2 BGP2 BCLK or GPIO2 pin configuration select. 1 SDOGP1 ADC_SDATA or GPIO1 pin configuration select. 0 = ADC_SDATA enabled (default). 0 SDIGP0 DAC_SDATA or GPIO0 pin configuration select. 0 = DAC_SDATA enabled (default). Table 86. DSP Enable Register Register R62 (Address 0x40F6). Table 87. DSP Run Register 0 DSPRUN Run the DSP . Set the DSPEN bit in Register R61 (Address 0x40F5) before setting this bit.

disabling the codec volume slew. Table 88. DSP Slew Modes Register 4 MOSLW Mono output slew generation. 3 ROSLW Line output right slew generation. 2 LOSLW Line output left slew generation. 1 RHPSLW Headphone right slew generation. 0 LHPSLW Headphone left slew generation. Table 89. Serial Port Sampling Rate Register rate (set using the DSPSR[3:0] bits in Register R57).

register to disable blocks that are not being used. Table 90. Clock Enable 0 Register disabled and stay set to their current state. 5 ALCPD ALC digital clock engine enable. 4 DECPD Decimator resync (dejitter) digital clock engine enable. 3 SOUTPD Serial routing outputs digital clock engine enable. 2 INTPD Interpolator resync (dejitter) digital clock engine enable. 1 SINPD Serial routing inputs digital clock engine enable. 0 SPPD Serial port digital clock engine enable. maximum power saving, use this register to disable clocks that are not being used. Table 91. Clock Enable 1 Register 1 CLK1 Digital Clock Generator 1. 0 CLK0 Digital Clock Generator 0.

Table 92. R8 and R9 Volume Settings Table 93. R14 Noise Gate Threshold

Table 94. R20, R21, R37, and R38 Volume Settings

Rev. C | Page 89 of 92 Binary Value Volume Attenuation (dB) 01100000 −36 01100001 −36.375 01100010 −36.75 01100011 −37.125 01100100 −37.5 01100101 −37.875 01100110 −38.25 01100111 −38.625 01101000 −39 01101001 −39.375 01101010 −39.75 01101011 −40.125 01101100 −40.5 01101101 −40.875 01101110 −41.25 01101111 −41.625 01110000 −42 01110001 −42.375 01110010 −42.75 01110011 −43.125 01110100 −43.5 01110101 −43.875 01110110 −44.25 01110111 −44.625 01111000 −45 01111001 −45.375 01111010 −45.75 01111011 −46.125 01111100 −46.5 01111101 −46.875 01111110 −47.25 01111111 −47.625 10000000 −48 10000001 −48.375 10000010 −48.75 10000011 −49.125 10000100 −49.5 10000101 −49.875 10000110 −50.25 10000111 −50.625 10001000 −51 10001001 −51.375 10001010 −51.75 10001011 −52.125 10001100 −52.5 10001101 −52.875 10001110 −53.25 10001111 −53.625 10010000 −54 Binary Value Volume Attenuation (dB) 10010001 −54.375 10010010 −54.75 10010011 −55.125 10010100 −55.5 10010101 −55.875 10010110 −56.25 10010111 −56.625 10011000 −57 10011001 −57.375 10011010 −57.75 10011011 −58.125 10011100 −58.5 10011101 −58.875 10011110 −59.25 10011111 −59.625 10100000 −60 10100001 −60.375 10100010 −60.75 10100011 −61.125 10100100 −61.5 10100101 −61.875 10100110 −62.25 10100111 −62.625 10101000 −63 10101001 −63.375 10101010 −63.75 10101011 −64.125 10101100 −64.5 10101101 −64.875 10101110 −65.25 10101111 −65.625 10110000 −66 10110001 −66.375 10110010 −66.75 10110011 −67.125 10110100 −67.5 10110101 −67.875 10110110 −68.25 10110111 −68.625 10111000 −69 10111001 −69.375 10111010 −69.75 10111011 −70.125 10111100 −70.5 10111101 −70.875 10111110 −71.25 10111111 −71.625 11000000 −72 11000001 −72.375

Table 95. R29 through R33 Volume Settings

Rev. C | Page 91 of 92 Binary Value Volume Setting (dB) 100001 −24 100010 −23 100011 −22 100100 −21 100101 −20 100110 −19 100111 −18 101000 −17 101001 −16 101010 −15 101011 −14 101100 −13 101101 −12 101110 −11 101111 −10 110000 −9 110001 −8 110010 −7 110011 −6 110100 −5 110101 −4 110110 −3 110111 −2 111000 −1 111001 0 111010 1 111011 2 111100 3 111101 4 111110 5 111111 6

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

3.50 REF

0.60 MAX

0.25 MIN

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