ADAU1592

ADAU1592 (Rev. B)

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

Class-D Audio Power Amplifier ADAU1592 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2020 Analog Devices, Inc. All rights reserved.

FEATURES

Integrated stereo modulator and power stage 0.005% THD + N 101 dB dynamic range PSRR > 65 dB R DS-ON < 0.3 Ω (per transistor) Efficiency > 90% (8 Ω) EMI-optimized modulator On/off-mute pop-noise suppression Short-circuit protection Overtemperature protection

APPLICATIONS

The ADAU1592 is a 2-channel, bridge-tied load (BTL) switching audio power amplifier with an integrated Σ-Δ modulator. The modulator accepts an analog input signal and generates a switching output to drive speakers directly. A digital, microcontroller-compatible interface provides control of reset, mute, and PGA gain as well as output signals for thermal and overcurrent error conditions. The output stage can operate from supply voltages ranging from 9 V to 18 V. The analog modulator and digital logic operate from a 3.3 V supply. FUNCTIONAL BLOCK DIAGRAM PVDD OUTL+ PGNDA2 PVDD OUTL– PGNDB2 PVDD OUTR+ PGNDC2 PVDD OUTR– PGNDD2 LEVEL SHIFT AND DEAD TIME CONTROL Σ-Δ MODULATOR TEMPERATURE/ OVERCURRENT PROTECTION MODE CONTROL LOGIC CLOCK OSCILLATOR PGA ADAU1592 fCLK/2 VOLTAGE REFERENCE PGA SLICER AINL SLC_TH PGA0 PGA1 PGA0 PGA1 AINR VREF AVDD AGND DVDD DGND OTWXTO XTI ERRMUTESTDNMO/ST 06749-001 Figure 1.

Rev. B | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

9/2020—Rev. A to Rev. B 9/2007—Rev. 0 to Rev. A 5/2007—Revision 0: Initial Version

Rev. B | Page 3 of 24 SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, PVDD = 15 V, ambient temperature = 25°C, load impedance = 6 Ω, clock frequency = 24.576 MHz, measurement bandwidth = 20 Hz to 20 kHz, unless otherwise specified. AUDIO PERFORMANCE Table 1. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT POWER1 1 kHz

12 W 1% THD + N, 8 Ω

15 W 10% THD + N, 8 Ω

14.5 W 1% THD + N, 6 Ω

18 W 10% THD + N, 6 Ω

19.5 W 1% THD + N, 4 Ω

24 W 10% THD + N, 4 Ω

EFFICIENCY 87 % @ 18 W, 6 Ω RDS-ON @ TCASE = 25°C Per High-Side Transistor 0.28 Ω @ 100 mA Per Low-Side Transistor 0.25 Ω @ 100 mA THERMAL CHARACTERISTICS Thermal Warning Active2 135 °C Die temperature Thermal Shutdown Active 150 °C Die temperature OVERCURRENT SHUTDOWN ACTIVE 5 6 A Peak current PVDD UNDERVOLTAGE SHUTDOWN 5.1 V INPUT LEVEL FOR FULL-SCALE OUTPUT Full-scale output @ 1% THD + N

1.0 Vrms PGA gain = 0 dB

0.5 Vrms PGA gain = 6 dB

0.25 Vrms PGA gain = 12 dB

0.125 Vrms PGA gain = 18 dB

TOTAL HARMONIC DISTORTION + NOISE (THD + N) 0.005 % 1 kHz, P OUT = 1 W, PGA gain = 0 dB SIGNAL-TO-NOISE RATIO (SNR) 99 101 dB A-weighted, referred to 1% THD + N output DYNAMIC RANGE (DNR) 99 101 dB A-weighted, measured with −60 dBFS input CROSSTALK (LEFT TO RIGHT OR RIGHT TO LEFT) −90 dB @ full-scale output voltage, 1% THD + N, 1 kHz AMPLIFIER GAIN PVDD = 15 V, 6 Ω PGA = 0 dB 19 dB PGA = 6 dB 25 dB PGA = 12 dB 31 dB PGA = 18 dB 37 dB OUTPUT NOISE VOLTAGE PVDD = 15 V, 6 Ω PGA = 0 dB 78 μV PGA = 6 dB 100 μV PGA = 12 dB 158 μV PGA = 18 dB 280 μV POWER SUPPLY REJECTION RATIO (PSRR) 65 dB 20 Hz to 20 kHz, 1.5 V p-p ripple, inputs ac-coupled to AGND 1 Output powers above 12 W at 4 Ω and above 18 W at 6 Ω are not continuous and are thermally limited by the package dissipation. 2 Thermal warning flag is for indication of device TJ reaching close to shutdown temperature.

Rev. B | Page 4 of 24 DC SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments INPUT IMPEDANCE 20 kΩ AINL/AINR OUTPUT DC OFFSET VOLTAGE ±3 mV POWER SUPPLIES Table 3. Parameter Min Typ Max Unit Test Conditions/Comments ANALOG SUPPLY VOLTAGE (AVDD) 3.0 3.3 3.6 V DIGITAL SUPPLY VOLTAGE (DVDD) 3.0 3.3 3.6 V POWER TRANSISTOR SUPPLY VOLTAGE (PVDD) 9 15 18 V POWER-DOWN CURRENT STDN held low AVDD 5 60 μA DVDD 0.1 0.24 mA PVDD 0.082 0.25 mA MUTE CURRENT MUTE held low AVDD 13 20 mA DVDD 1.7 3.2 mA PVDD 5.4 8 mA OPERATING CURRENT STDN and MUTE held high, no input AVDD 13 30 mA DVDD 2.7 4 mA PVDD 44 65 mA DIGITAL I/O Table 4. Parameter Min Typ Max Unit Test Conditions/Comments INPUT VOLTAGE Input Voltage High 2 V Input Voltage Low 0.8 V OUTPUT VOLTAGE Output Voltage High 2 V @ 2 mA Output Voltage Low 0.4 V @ 2 mA LEAKAGE CURRENT ON DIGITAL INPUTS 10 μA

1 Includes any induced voltage due to inductive load. soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance 1 With exposed pad (ePAD) soldered to 4-layer JEDEC standard PCB. 2 Through the bottom (ePAD) surface.

Rev. B | Page 8 of 24 Pin Number Mnemonic Type 1 Description 34, 35, 36 OUTR− O Output of High Power Tr ansistors, Right Channel Negative Polarity. 37, 38, 47, 48 PGND P Power Ground for High Po wer Transistors. Internally connected to ePAD. 39, 40, 41, 42, 43, 44, 45, 46 PVDD P Positive Power Supply for High Power Transistors. 1 I = input, O = output, P = power.

Figure 44. Block for Slicer Threshold Adjust, SLC_TH VTH is the voltage threshold at which the slicer is activated. Thus, the slicer is activated at and above 0.864 VIN rms. the slicer, SLC_TH should be connected directly to AGND. Table 9. Typical REXTERNAL Values applications. See the Protection Circuits section for further details. for setting the desired gain. fier full-scale input level changes as per the PGA gain setting. Table 10. Gain Settings outputs are open-drain and require external pull-up resistors. shutdown temperature is reached. needs to be toggled to low and then to high again.

to reduce the dc offset at the output. Figure 49. Input Equivalent Circuit RIN = 20 kΩ, fixed internally. SOURCE is the source resistance. CIN is the input coupling capacitor (2.2 μF typical). CREF is the filter capacitor for VREF. VREF is the analog reference voltage (AVDD/2 typical). VMIS is the dc offset due to mismatch in the op amp. leakage current of the CIN capacitor. during the power-up sequence. output (see Figure 49). This depends on the PGA gain setting. to the Power-Up/Power-Down Sequence section. section describes how to select the value for the CREF and CIN. recommended value for CREF is 4.7 μF. fLOW is the low corner frequency (−3 dB). RIN is the input resistance (20 kΩ). CIN is the input coupling capacitor. and should keep 20 Hz roll-off within −0.5 dB. Sequence section for more details. tion schematic in Figure 51 for details. care must be taken for power supply decoupling.

Rev. B | Page 20 of 24 capacitors must be placed very close to their respective pins with direct connection. This is important for reliable and safe operation of the device. One additional 1 μF capacitor in parallel to the 100 nF capacitor is also recommended. A bulk bypass capacitor of 470 μF is also recommended to remove the low frequency ripple due to load current. Similarly, one 100 nF capacitor is recommended between each DVDD/DGND and AVDD/AGND. These capacitors also must be placed close to their respective pins with direct connection. EXTERNAL PROTECTION FOR PVDD > 15 V As the PVDD supply voltage approaches 15 V and above, the available headroom with maximum PVDD is reduced. As with any switching amplifier, the outputs swing to full rail and the amount of overshoot due to parasitic elements of the package/board is significant. Therefore, for reliable and safe operation, it is recommended that external protection circuits be added for applications that require supply voltages >15 V. The use of an RC snubber or a Schottky diode on the outputs should be considered. The RC snubber should be connected between the OUTx+ pin and the OUTx− pin for each channel. The typical recommended values are 10 Ω and 680 pF. Also, both components must be placed close to the output pins. For two channels, two resistors and two capacitors are needed. If Schottky diodes are preferred, the diodes must be from each OUTx−/OUTx+ pin to PVDD/PGND. Therefore, a total of eight diodes is required for two channels. The Schottky diodes must be placed close to the output pins to be effective. CLOCK The ADAU1592 uses 24.576 MHz for the master clock, which is 512 × f S (fS = 48 kHz). There are several options for providing the clock. Option 1: Using a Quartz Crystal A quartz crystal of 24.576 MHz frequency can be connected between the XTI and XTO pins using two load capacitors suitable for the crystal oscillation mode. Option 2: Using a Ceramic Resonator The ADAU1592 can also be used with ceramic resonators similar to crystal by using the XTI and XTO pins. Option 3: Using an External Clock The ADAU1592 can be provided with an external clock of 24.576 MHz at the XTI pin. The logic level for the clock input should be in the range of 3.3 V and 50% typical duty cycle. For systems using multiple ADAU1592s, it is recommended to use only one clock source if the ADAU1592s share the same power supply to prevent the beat frequencies of asynchronous clocks from appearing in the audio band. Multiple ADAU1592s can be connected in a daisy chain by providing or generating a master clock from one ADAU1592 and subsequently connecting its XTO output to the XTI input of the next ADAU1592, and so on. However, using a simple logic buffer from the XTO pin of one ADAU1592 to the XTI pin of the next ADAU1592 is recommended. Because the clock output is now buffered, it can be connected to the XTI inputs of the remaining ADAU1592s, depending on the fanout capability of the logic buffer used.

For applications with PVDD > 15 V, add components R1 and R2 (10 Ω typical), C5 and C6 (680 pF typical), and D1 through D8 (CRS01/02). Figure 50. Typical Stereo Application Circuit Table 11. R3—Slicer Threshold Resistor Table 12. Output Filter Component Values

For applications with PVDD > 15 V, add components R1 (10 Ω typical), C5 (680 pF typical), and D1 through D4 (CRS01/02). Figure 51. Typical Mono Application Circuit Table 13. R3—Slicer Threshold Resistor Table 14. Output Filter Component Values

0.20 MIN

0.05 MAX

0.02 NOM

0.203 REF

5.50 REF

Figure 52. 48-Lead Lead Frame Chip Scale Package [LFCSP]

0.50 BSC

0.08 MAX

1.00 REF

Figure 53. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. B | Page 24 of 24 NOTES ©2007–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06749-9/20(B)