ADAU1513 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Integrated stereo power stage RDS-ON < 0.3 Ω (per transistor) Efficiency > 90% Short-circuit protection Overtemperature protection
APPLICATIONS
The ADAU1513 is a 2-channel bridge-tied load (BTL) Class-D audio power stage. The power stage can drive the speaker loads of 4 Ω at up to 15 W per channel at high efficiency. The 4-channel audio system can be formed when used with an ADAV4201 pulse-width modulator (PWM) processor using two ADAU1513s. The power stage accepts a
3.3 V logic differential PWM as input from an ADAV4201
processor. The power stage comprises thermal and output short-circuit protection with logic-level error flag outputs for interfacing to a system microcontroller along with reset and mute control of the power stage. The power stage operates from a range of power supply voltages from 9 V up to 18 V . The low power digital logic operates from a 3.3 V supply. The power stage can be used with modulators other than the ADAV4201. Contact your local sales department for application assistance. FUNCTIONAL BLOCK DIAGRAM PVDD OUTL+ PGNDA2 PVDD OUTL– PGNDB2 PVDD OUTR+ PGNDC2 PVDD OUTR– PGNDD2 LEVEL SHIFT AND DEAD TIME CONTROL TEMPERATURE/ OVERCURRENT PROTECTION MODE CONTROL LOGIC ADAU1513 VOLTAGE REFERENCE INL+ INL– INR+ INR– AVDD AGND DVDD DGND OTWERRMUTESTDN 06750-001 Figure 1.
Rev. 0 | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 3 of 16 SPECIFICATIONS DVDD = 3.3 V , AVDD = 3.3 V , PVDD = 15 V , ambient temperature = 25°C, load impedance = 8 Ω, measurement bandwidth = 20 Hz to 20 kHz, unless otherwise noted. Audio performance test data measured with ADAV4201. PERFORMANCE SUMMARY Table 1. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT POWER1 1 kHz
11 W 1% THD + N, 8 Ω
14 W 10% THD + N, 8 Ω
14.5 W 1% THD + N, 6 Ω
17.5 W 10% THD + N, 6 Ω
19 W 1% THD + N, 4 Ω
23 W 10% THD + N, 4 Ω
EFFICIENCY 90 % P OUT = 15 W RDS-ON Per High-Side Transistor 280 mΩ I D = 100 mA Per Low-Side Transistor 250 mΩ I D = 100 mA THERMAL CHARACTERISTICS Thermal Warning Active2 135 °C Die temperature Thermal Shutdown Active 150 °C Die temperature OVERCURRENT SHUTDOWN ACTIVE 5 A peak TOTAL HARMONIC DISTORTION PLUS NOISE (THD + N) 0.1 % P OUT = 1 W, 1 kHz SIGNAL-TO-NOISE RATIO (SNR) 96 dB A-weighted, referred to 1% THD + N output DYNAMIC RANGE 96 dB A-weighted, measured with −60 dBFS input CROSSTALK BETWEEN LEFT AND RIGHT CHANNELS 65 dB @ 0 dBFS input 20 Hz to 20 kHz UNDERVOLTAGE TRIP THRESHOLD 5 V MINIMUM OUTPUT PULSE WIDTH 50 ns 1 Output powers above 15 W at 4 Ω and above 18 W at 6 Ω may need extra heat-sinking for continuous operation. 2 Thermal warning flag is for indication of device TJ reaching close to shutdown temperature. POWER SUPPLIES Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL SUPPLY VOLTAGE (DVDD) 3.0 3.3 3.6 V ANALOG SUPPLY VOLTAGE (AVDD) 3.0 3.3 3.6 V POWER TRANSISTOR SUPPLY VOLTAGE (PVDD) 9 15 18 V POWER-DOWN CURRENT STDN held low AVDD 2 3 μA DVDD 50 55 μA PVDD 55 600 μA MUTE CURRENT MUTE held low AVDD 0.5 0.6 mA DVDD 0.9 1.2 mA PVDD 0.3 0.9 mA OPERATING CURRENT STDN and MUTE held high AVDD 0.5 0.6 mA DVDD 1.1 2.5 mA PVDD 34 40 mA
Rev. 0 | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating DVDD to DGND −0.3 V to +3.6 V AVDD to AGND −0.3 V to +3.6 V PVDD to PGND1 −0.3 V to +20.0 V PWM Inputs DGND − 0.3 V to DVDD + 0.3 V MUTE/STDN Inputs DGND − 0.3 V to DVDD + 0.3 V Operating Temperature Range −40°C to +85°C Storage Temperature Range –65°C to +150°C Maximum Junction Temperature 150°C θJA Thermal Resistance 26.7°C/W ΨJB Thermal Characterization (Junction-Board) 13.3°C/W ΨJT Thermal Characterization (Junction-Package Top) 0.2°C/W Lead Temperature Soldering (10 sec) 260°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 Includes any induced voltage due to inductive load. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
- EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND, DGND, AND AGND FOR TQFP-48.
- EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
Figure 4. Pin Configuration Table 7. Pin Function Descriptions 1, 2, 3 OUTL− O Output of High Power Transistors, Left Channel Negative Polarity. 4, 5, 6 OUTL+ O Output of High Power Transistors, Left Channel Positive Polarity. 7 INL− I Differential PWM Left Input (−). 8 INL+ I Differential PWM Left Input (+). 9 ERR O Overtemperature Shutdown Error Indicator (Active Low Open-Drain Output). 10 OTW O Overtemperature Warning Indicator (Active Low Open-Drain Output). 11 TEST2 I Reserved for Internal Use. Connect to DGND. 12 TEST3 I Reserved for Internal Use. Connect to DVDD. 13 INR− I Differential PWM Right Input (−). 14 INR+ I Differential PWM Right Input (+). 15 MUTE I Mute (Active Low Input). 16 STDN I Shutdown/Reset Input (Active Low Input). 17 TEST4 I Reserved for Internal Use. Connect to DGND. 18 TEST5 O Reserved for Internal Use. Do not connect. 19 DGND P Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD)2. 20 DVDD P Positive Supply for Digital Circuitry. 21 AVDD P Positive Supply for Analog Circuitry (Can be Tied to DVDD). 22 AGND P Analog Ground for Analog Circuitry. Internally connected to ePAD2. Can be tied to DGND. 23 TEST6 I Reserved for Internal Use. Connect to DGND. 24 TEST7 I Reserved for Internal Use. Connect to DGND. 25 TEST8 I Reserved for Internal Use. Connect to DGND. 26 TEST9 I Reserved for Internal Use. Connect to DGND. 27 TEST10 I Reserved for Internal Use. Connect to DGND. 28 TEST11 I Reserved for Internal Use. Connect to DGND. 29 TEST12 I Reserved for Internal Use. Connect to DGND. 30 TEST13 I Reserved for Internal Use. Connect to DGND. 31, 32, 33 OUTR+ O Output of High Power Transistors, Right Channel Positive Polarity.
Rev. 0 | Page 7 of 16 Pin Number Mnemonic Type 1 Description 34, 35, 36 OUTR− O Output of High Power Transistors, Right Channel Negative Polarity. 37, 38, 47, 48 PGND P Power Ground for High Power Transistors. Internally connected to ePAD2. 39, 40, 41, 42, 43, 44, 45, 46 PVDD P Positive Power Supply for High Power Transistors. 1 I = input, O = output, P = power. 2 ePAD is connected internally to PGND, DGND, and AGND.
short-circuit, and undervoltage protection. supply or bootstrap capacitor compared to all NMOS stages. The ADAU1513 includes comprehensive protection circuits. outputs are open drain, requiring external pull-up resistors. shutdown temperature is reached. needs to be toggled to low and then to high again. against excessive output current by pulling the ERR (Pin 9) low. microcontroller intervention. other thermal shutdown (ERR).
- Option 1: Using OTW
- Option 2: Using ERR The following sections provide further details of these two options. Option 1: Using OTW The OTW pin is pulled low when the die temperature reaches 130°C to 135°C This pin can be wired to the MUTE pin using an RC circuit as shown in Figure 28. 06750-027 ADAU1513 OTW TO MUTE LOGIC INPUT 1N4148 DVDD 100kΩ MUTE 47µF
Figure 28. Option 1 Schematic for Autorecovery The low logic level on OTW also pulls down the MUTE pin.
Rev. 0 | Page 14 of 16 DVDD, and PVDD supply connections, as well AGND, DGND, and PGND. In addition, the ADAU1513 incorporates a built-in undervoltage lockout logic on DVDD as well as PVDD. This helps detect undervoltage operation and eliminates the need to have an external mechanism to sense the supplies. The ADAU1513 monitors the DVDD and PVDD supply voltages and prevents the power stage from turning on if either of the supplies are not present or below the operating threshold. Therefore, if DVDD is missing or below the operating thresh- old, for example, the power stage will not turn on, even if the PVDD is present or vice versa. Because this protection is only present on DVDD and PVDD and not on AVDD, shorting both AVDD and DVDD externally or generating AVDD and DVDD from one power source is recommended. This ensures both AVDD and DVDD supplies are tracking each other and avoids the need to monitor the sequence with respect to PVDD. This also ensures minimal pop and click during power-up. When using separate AVDD and DVDD supplies, ensure that both supplies are stable before unmuting or turning on the power stage. During power-up, it is recommended to keep STDN and MUTE low to ensure that the power stage stays in high-Z mode. Similarly, during shutdown, pulling MUTE to logic low before pulling STDN down is recommended. However, where a fault event occurs, the power stage will shut down to protect the part. In this case, depending on the signal level, there is some pop at the speaker. During shutdown of the power supplies to reduce power consumption, it is highly recommended to mute the amplifier first, followed by pulling STDN low before shutting down any of the supplies. After MUTE is pulled low, the power supplies can be shut down in the following order: PVDD, DVDD, then AVDD. Where AVDD and DVDD are generated from a single source, ensure that PVDD is tuned off before DVDD and AVDD, and after issuing MUTE and STDN.
refer to the ADAV4201 data sheet. For applications with PVDD > 15 V , add components R1 and R2 = 10 Ω typical, C5 and C6 = 680 pF typical, and D1 through D8 = CRS01/02. Figure 31. Application Schematic Table 8. Suggested Low-Pass Filter Values
0.50 BSC
0.20 REF
0.80 MAX
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
0.25 MIN
Figure 32. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
0.08 MAX
1.00 REF
Figure 33. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] registered trademarks are the property of their respective owners.