ADAU1462WBCPZ150

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SigmaDSP Digital Audio Processor Data Sheet ADAU1462/ADAU1466 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Qualified for automotive applications Fully programmable audio DSP for enhanced sound processing Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V Up to 24 kWords of program memory Up to 80 kWords of parameter/data RAM Up to 6144 SIMD instructions per sample at 48 kHz Up to 1600 ms digital audio delay pool at 48 kHz Audio I/O and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz Flexible configuration for TDM, I 2S, left and right justified formats, and PCM Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range Stereo S/PDIF input and output at 192 kHz Four PDM microphone input channels Multichannel, byte addressable TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor I 2C and SPI control interfaces (both slave and master) Standalone operation Self-boot from serial EEPROM 6-channel, 10-bit SAR auxiliary control ADC 14 multipurpose pins for digital controls and outputs On-chip regulator for generating 1.2 V from 3.3 V supply 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm exposed pad Temperature range: −40°C to +105°C

APPLICATIONS

Automotive audio processing Head units Distributed amplifiers Rear seat entertainment systems Trunk amplifiers Commercial and professional audio processing FUNCTIONAL BLOCK DIAGRAM S/PDIF TRANSMITTER S/PDIF RECEIVER 8 × 2-CHANNEL ASYNCHRONOUS SAMPLE RATE CONVERTERS INPUT CLOCK DOMAINS (×4) OUTPUT CLOCK DOMAINS (×4) CLOCK OSCILLATOR GPIO/ AUX ADC PLLI2C/SPI SLAVE XTALIN/MCLK XTALOUTSPI/I2C* BCLK_IN3 TO BCLK_IN0/ LRCLK_IN3 TO LRCLK_IN0 (INPUT CLOCK PAIRS) SELFBOOT SPDIFIN SPDIFOUT CLKOUT SDATA_IN3 TO SDATA_IN0 (48-CHANNEL DIGITAL AUDIO INPUTS) SDATA_OUT3 TO SDATA_OUT0 (48-CHANNEL DIGITAL AUDIO OUTPUTS) REGULATOR ADAU1462/ ADAU1466 PLLFILT MP13 TO MP0 AUXADC5 TO AUXADC0 BCLK_OUT3 TO BCLK_OUT0 LRCLK_OUT3 TO LRCLK_OUT0 (OUTPUT CLOCK PAIRS) TEMPERATURE SENSOR THD_P VDRIVE THD_M I2C/SPI MASTER SPI/I2C* DIGITAL MIC INPUT SERIAL DATA INPUT PORTS (×4) SERIAL DATA OUTPUT PORTS (×4) DEJITTER AND CLOCK GENERATOR INPUT AUDIO ROUTING MATRIX OUTPUT AUDIO ROUTING MATRIX 294.912MHz PROGRAMMABLE AUDIO PROCESSING CORE RAM, ROM, WATCHDOG, MEMORY PARITY CHECK 14810-001 *SPI/I2C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA, SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS. Figure 1.

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 2 of 202 TABLE OF CONTENTS

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 3 of 202

REVISION HISTORY

3/2018—Rev. B to Rev. C Changes to S/PDIF Transmitter and Receiver Section and Deleted S/PDIF Receiver Section and Table 11; Renumbered Added I 10/2017—Rev. A to Rev. B 9/2017—Rev. 0 to Rev. A Change to Supply Current Analog Current (AVDD) Parameter, Change to Supply Current PLL Current (PVDD) Parameter and Supply Current Analog Current (AVDD) Parameter, Table 3 .... 5 8/2017—Revision 0: Initial Version

ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors. generations, leading to vastly improved code efficiency.

294.912 MHz and execute up to 6144 SIMD instructions per

wide range can generate up to 15 sample rates simultaneously. modulation (PDM) output of up to four MEMS microphones. more power at the same processing load. Table 1. Product Selection Table

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 5 of 202 SPECIFICATIONS 12.288 MHz, core clock (fCORE) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments POWER Supply Voltage Analog Voltage (AVDD) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC Digital Voltage (DVDD) 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing PLL Voltage (PVDD) 2.97 3.3 3.63 V Supply for PLL circuitry I/O Supply Voltage (IOVDD) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters Supply Current Analog Current (AVDD) 1.36 1.66 2 mA Idle State 1.00 1.10 40 μA Power applied, chip not programmed Reset State 1.00 1.10 40 μA Power applied, RESET held low PLL Current (PVDD) 8.3 10.1 12.9 mA 12.288 MHz MCLK with default PLL settings Idle State 18.3 18.7 40 μA Power applied, PLL not configured Reset State 18.3 18.7 40 μA Power applied, RESET held low I/O Current (IOVDD) Dependent on the number of active serial ports, clock pins, and characteristics of external loads Operation State 53 mA IOVDD = 3.3 V; all serial ports are clock masters 22 mA IOVDD = 1.8 V; all serial ports are clock masters Power-Down State 4.1 4.2 mA IOVDD = 1.8 V − 5% to 3.3 V + 10% Digital Current (DVDD) ADAU1466 Operation State Maximum Program 233 495 mA Typical Program 220 mA Test program includes 16-channel I/O, 10-band equalizer (EQ) per channel, all ASRCs active Minimal Program 213 mA Test program includes 2-channel I/O, 10-band EQ per channel ADAU1462 Operation State fCORE = 294.912 MHz Maximum Program 233 495 mA Typical Program 220 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 213 mA Test program includes 2-channel I/O, 10-band EQ per channel fCORE = 147.456 MHz Maximum Program 170 455 mA Typical Program 135 mA Test program includes 16-channel I/O, 10-band EQ per channel Minimal Program 110 mA Test program includes 2-channel I/O, 10-band EQ per channel Idle State 18.3 18.7 19.9 mA Power applied, DSP not enabled Reset State 18.3 18.7 19.9 mA Power applied, RESET held low ASYNCHRONOUS SAMPLE RATE CONVERTERS Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz I/O Sample Rate 6 192 kHz I/O Sample Rate Ratio 1:8 7.75:1 Total Harmonic Distortion + Noise (THD + N) −120 dB CRYSTAL OSCILLATOR Transconductance 8.3 10.6 13.4 mS REGULATOR DVDD Voltage 1.14 1.2 V Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10%

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 6 of 202 master clock input = 12.288 MHz, fCORE = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments POWER Supply Voltage Analog Voltage (AVDD) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC Digital Voltage (DVDD) 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing PLL Voltage (PVDD) 2.97 3.3 3.63 V Supply for PLL circuitry IOVDD Voltage (IOVDD) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters Supply Current Analog Current (AVDD) 1.36 1.66 2 mA Idle State 1.0 1.1 40 μA Reset State 1.0 1.1 40 μA PLL Current (PVDD) 8.3 10.2 15 mA 12.288 MHz master clock; default PLL settings Idle State 18.4 18.7 40 μA Power applied, PLL not configured Reset State 18.4 18.7 40 μA Power applied, RESET held low I/O Current (IOVDD) Dependent on the number of active serial ports, clock pins, and characteristics of external loads Operation State 53 mA IOVDD = 3.3 V; all serial ports are clock masters 22 mA IOVDD = 1.8 V; all serial ports are clock masters Power-Down State 4.1 4.3 mA IOVDD = 1.8 V − 5% to 3.3 V + 10% Digital Current (DVDD) ADAU1466 Operation State Maximum Program 485 920 mA Typical Program 330 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 213 mA Test program includes 2-channel I/O, 10-band EQ per channel ADAU1462 Operation State fCORE = 294.912 MHz Maximum Program 485 920 mA Typical Program 330 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 213 mA Test program includes 2-channel I/O, 10-band EQ per channel fCORE = 147.456 MHz Maximum Program 270 490 mA Typical Program 220 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 210 mA Test program includes 2-channel I/O, 10-band EQ per channel Idle State 5.9 15.7 559 mA Power applied, DSP not enabled Reset State 5.9 15.7 559 mA Power applied, RESET held low ASYNCHRONOUS SAMPLE RATE CONVERTERS Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz I/O Sample Rate 6 192 kHz I/O Sample Rate Ratio 1:8 7.75:1 THD + N −120 dB CRYSTAL OSCILLATOR Transconductance 8.1 10.6 14.6 mS REGULATOR DVDD Voltage 1.14 1.2 V Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10%

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 7 of 202

ELECTRICAL CHARACTERISTICS

Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUT Input Voltage Excluding SPDIFIN, which is not a standard digital input IOVDD = 3.3 V High Level (VIH) 1.71 3.3 V Low Level (VIL) 0 1.71 V IOVDD = 1.8 V High Level (VIH) 0.92 1.8 V Low Level (VIL) 0 0.89 V Input Leakage High Level (IIH) 2 μA Digital input pins with pull-up resistor 14 μA Digital input pins with pull-down resistor 2 μA Digital input pins with no pull resistor 8 μA MCLK 120 μA SPDIFIN Low Level (IIL) at 0 V −14 μA Digital input pins with pull-up resistor −2 μA Digital input pins with pull-down resistor −2 μA Digital input pins with no pull resistor −8 μA MCLK −120 μA SPDIFIN Input Capacitance (CI) 2 pF Guaranteed by design DIGITAL OUTPUT Output Voltage IOVDD = 3.3 V High Level (VOH) 3.09 3.3 V I OH = 1 mA Low Level (VOL) 0 0.26 V I OL = 1 mA IOVDD = 1.8 V High Level (VOH) 1.45 1.8 Low Level (VOL) 0 0.33 Digital Output Pins, Output Drive The digital output pins are driving low impedance PCB traces to a high impedance digital input buffer IOVDD = 1.8 V Drive Strength Setting Lowest 1 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Low 2 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly High 3 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Highest 5 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly IOVDD = 3.3 V Drive Strength Setting Lowest 2 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Low 5 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly High 10 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Highest 15 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 8 of 202 Auxiliary ADC Table 5. Parameter Min Typ Max Unit RESOLUTION 10 Bits FULL-SCALE ANALOG INPUT AVDD V NONLINEARITY Integrated Nonlinearity (INL) −2.5 +2.5 LSB Differential Nonlinearity (DNL) −2.5 +2.5 LSB GAIN ERROR −2.5 +2.5 LSB INPUT IMPEDANCE 200 kΩ SAMPLE RATE fCORE/6144 Hz

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 11 of 202 Multipurpose Pins (MPx) TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. Table 9. Parameter Min Max Unit Description fMP 24.576 MHz MPx maximum switching rate when pin is configured as a general-purpose input or general-purpose output tMPIL 10 × tCORE 6144 × t CORE sec MPx pin input latency until high/low value is read by core; the duration in the Max column is equal to the period of one audio sample when the DSP is processing 6144 instructions per sample S/PDIF Transmitter and Receiver TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%. Table 10. Parameter Min Max Unit Description AUDIO SAMPLE RATE Transmitter 18 192 kHz Audio sample rate of data output from S/PDIF transmitter Receiver 18 192 kHz Audio sample rate of data input to S/PDIF receiver

Figure 6. I2C Slave Port Timing Specifications

Figure 7. I2C Master Port Timing Specifications

Figure 8. SPI Slave Port Timing Specifications

Figure 9. SPI Master Port Timing Specifications

edges of the clock (see Figure 10). Figure 10. PDM Timing Diagram

ambient temperature supported in the application). recommended as the primary approach for thermal qualification. Table 17. Thermal Coefficients for ADAU1462/ADAU1466

1 Based on simulation using a JEDEC 2s2p thermal test PCB with 25 thermal vias in a

JEDEC natural convection environment, as per JESD51.

2 Based on simulation using a JEDEC 2s2p thermal test PCB with 25 thermal vias in a

JEDEC Junction to Board environment, as per JESD51. 3 Based on simulation using a cold plate attached directly to exposed paddle.

1. Configure the ADAU1462/ADAU1466 in the highest power

the power dissipated in the device.

1. Compute the maximum allowable surface temperature,
2. Measure the case temperature at the center of the
3. For safe operation, use TS < TS_MAX in the highest power

mode of operation in the application.

1. THE EXPOSED PAD MUST BE GROUNDED BY SOLDERING IT TO A COPPER SQUARE

TO A DEDICATED COPPER GROUND LAYER WITHIN THE PCB. Figure 11. Pin Configuration Table 18. Pin Function Descriptions a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. Pin 1 (DGND). See the Power Supply Bypass Capacitors and Grounding sections. when not in use. This pin is internally biased to IOVDD/2. pin when not in use. This pin is internally biased to IOVDD/2. ground plane. See the Power Supply Bypass Capacitors and Grounding sections. to Pin 6 (AGND). See the Power Supply Bypass Capacitors and Grounding sections. DSP program. Disconnect this pin when not in use. DSP program. Disconnect this pin when not in use. DSP program. Disconnect this pin when not in use.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 19 of 202 Pin No. Mnemonic Internal Pull Resistor Description 11 AUXADC3 None Auxiliary ADC Input Channel 3. This pin reads an analog input signal and uses its value in the DSP program. Disconnect this pin when not in use. 12 AUXADC4 None Auxiliary ADC Input Channel 4. This pin reads an analog input signal and uses its value in the DSP program. Disconnect this pin when not in use. 13 AUXADC5 None Auxiliary ADC Input Channel 5. This pin reads an analog input signal and uses its value in the DSP program. Disconnect this pin when not in use. 14 PGND None PLL Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 15 PVDD None PLL Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors to Pin 14 (PGND). See the Power Supply Bypass Capacitors and Grounding sections. 16 PLLFILT None PLL Filter. The voltage on the PLLFILT pin, which is internally generated, is typically between 1.65 V and 2.10 V. 17 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 18 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin to Pin 17 (DGND) with decoupling capacitors. See the Power Supply Bypass Capacitors and Grounding sections. 19 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 20 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass this pin to Pin 19 (DGND) with decoupling capacitors. See the Power Supply Bypass Capacitors and Grounding sections. 21 XTALIN/MCLK None Crystal Oscillator Input (XTALIN)/Master Clock Input to the PLL (MCLK). This pin can be supplied directly or generated by driving a crystal with the internal crystal oscillator via Pin 22 (XTALOUT). If a crystal is used, refer to the circuit shown in Figure 14. 22 XTALOUT None Crystal Oscillator Output for Driving an External Crystal. If a crystal is used, refer to the circuit shown in Figure 14. Disconnect this pin when not in use. 23 CLKOUT Configurable Master Clock Output. This pin drives a master clock signal to other ICs in the system. CLKOUT can be configured to output a clock signal with a frequency of 1×, 2×, 4×, or 8× the frequency of the divided clock signal being input to the PLL. Disconnect this pin when not in use. 24 RESET Pull-down Active Low Reset Input. A reset is triggered on a high to low edge and exited on a low to high edge. A reset event sets all RAMs and registers to their default values. 25 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections.

26 SS_M/MP0 Pull-up; nominally

250 kΩ; can be disabled by a write to control register SPI Master/Slave Select Port (SS_M)/Multipurpose, General-Purpose Input/Output (MP0). When in SPI master mode, this pin acts as the slave select signal to slave devices on the SPI bus. The pin must go low at the beginning of a master SPI transaction and high at the end of a transaction. This pin has an internal pull-up resistor that is nominally 250 kΩ. When the SELFBOOT pin is held high and the RESET pin has a transition from low to high, Pin 26 sets the communications protocol for self boot operation. If this pin is left floating, the SPI communications protocol is used for self boot operation. If this pin has a 10 kΩ pull-down resistor to DGND, the I communications protocol is used for self boot operation. When self boot operation is not used and this pin is not needed as a general-purpose input or output, leave it disconnected.

27 MOSI_M/MP1 Pull-up; can be

SPI Master Data Output Port (MOSI_M)/Multipurpose, General-Purpose Input/Output (MP1). When in SPI master mode, this pin sends data from the SPI master port to slave devices on the SPI bus. Disconnect this pin when not in use.

28 SCL_M/

SCLK_M/MP2 Pull-up; can be disabled by a write to control register I 2C Master Serial Clock Port (SCL_M)/SPI Master Mode Serial Clock (SCLK_M)/Multipurpose, General-Purpose Input/Output (MP2). When in I2C master mode, this pin functions as an open collector output and drives a serial clock to slave devices on the I2C bus; use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin drives the clock signal to slave devices on the SPI bus. Disconnect this pin when not in use.

29 SDA_M/

MISO_M/MP3 Pull-up; can be disabled by a write to control register I 2C Master Port Serial Data (SDA_M)/SPI Master Mode Data Input (MISO_M)/Multipurpose, General-Purpose Input/Output (MP3). When in I2C master mode, this pin functions as a bi- directional open collector data line between the I2C master port and slave devices on the I2C bus; use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin receives data from slave devices on the SPI bus. Disconnect this pin when not in use.

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 20 of 202 Pin No. Mnemonic Internal Pull Resistor Description

30 MISO/SDA Pull-up; can be

SPI Slave Data Output Port (MISO)/I2C Slave Serial Data Port (SDA). In SPI slave mode, this pin outputs data to the master device on the SPI bus. In I2C slave mode, this pin functions as a bi- directional open collector data line between the I2C slave port and the master device on the I2C bus; use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor.

31 SCLK/SCL Pull-up; can be

SPI Slave Port Serial Clock (SCLK)/I 2C Slave Port Serial Clock (SCL). In SPI slave mode, this pin receives the serial clock signal from the master device on the SPI bus. In I2C slave mode, this pin receives the serial clock signal from the master device on the I2C bus; use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor.

32 MOSI/ADDR1 Pull-up; can be

SPI Slave Port Data Input (MOSI)/I 2C Slave Port Address MSB (ADDR1). In SPI slave mode, this pin receives a data signal from the master device on the SPI bus. In I2C slave mode, this pin acts as an input and sets the chip address of the I2C slave port, in conjunction with Pin 33 (SS/ADDR0).

33 SS/ADDR0 Pull-up, nominally

250 kΩ; can be disabled by a write to control register SPI Slave Port Slave Select (SS)/I 2C Slave Port Address LSB (ADDR0). In SPI slave mode, this pin receives the slave select signal from the master device on the SPI bus. In I2C slave mode, this pin acts as an input and sets the chip address of the I2C slave port in conjunction with Pin 32 (MOSI/ADDR1). 34 SELFBOOT Pull-up Self Boot Select. This pin allows the device to perform a self boot, in which it loads its random access memory (RAM) and register settings from an external EEPROM. Connecting Pin 34 to logic high (IOVDD) initiates a self boot operation the next time there is a rising edge on Pin 24 (RESET ). When this pin is connected to ground, no self boot operation is initiated. This pin can be connected to IOVDD or to ground either directly or pulled up or down with a 1.0 kΩ or larger resistor. 35 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass this pin to Pin 36 (DGND) with decoupling capacitors. See the Power Supply Bypass Capacitors and Grounding sections. 36 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 37 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 38 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to Pin 37 (DGND). See the Power Supply Bypass Capacitors and Grounding sections.

39 LRCLK_OUT0/

Configurable Frame Clock, Serial Output Port 0 (LRCLK_OUT0)/Multipurpose, General-Purpose Input/Output (MP4). This pin is bidirectional, with the direction depending on whether Serial Output Port 0 is a master or slave. Disconnect this pin when not in use. 40 BCLK_OUT0 Configurable Bit Clock, Serial Output Port 0. This pin is bidirectional, with the direction depending on whether the Serial Output Port 0 is a master or slave. Disconnect this pin when not in use. 41 SDATA_OUT0 Configurable Serial Data Output Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel, and 16-channel modes. Disconnect this pin when not in use.

42 LRCLK_OUT1/

Configurable Frame Clock, Serial Output Port 1 (LRCLK_OUT1)/Multipurpose, General-Purpose Input/Output (MP5). This pin is bidirectional, with the direction depending on whether Serial Output Port 1 is a master or slave. Disconnect this pin when not in use. 43 BCLK_OUT1 Configurable Bit Clock, Serial Output Port 1. This pin is bidirectional, with the direction depending on whether Output Serial Port 1 is a master or slave. Disconnect this pin when not in use. 44 SDATA_OUT1 Configurable Serial Data Output Port 1 (Channel 16 to Channel 31). Capable of 2-channel, 4-channel, 8-channel, and 16-channel modes. Disconnect this pin when not in use. 45 MP6 Configurable Multipurpose, General-Purpose Inp ut/Output 6. Disconnect this pin when not in use. 46 MP7 Configurable Multipurpose, General-Purpose Inp ut/Output 7. Disconnect this pin when not in use.

47 LRCLK_OUT2/

Configurable Frame Clock, Serial Output Port 2 (LRCLK_OUT2)/Multipurpose, General-Purpose Input/Output (MP8). This pin is bidirectional, with the direction depending on whether Serial Output Port 2 is a master or slave. Disconnect this pin when not in use. 48 BCLK_OUT2 Configurable Bit Clock, Serial Output Port 2. This pin is bidirectional, with the direction depending on whether Serial Output Port 2 is a master or slave. Disconnect this pin when not in use. 49 SDATA_OUT2 Configurable Serial Data Output Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8-channel, or flexible TDM mode. Disconnect this pin when not in use.

50 LRCLK_OUT3/

Configurable Frame Clock, Serial Output Port 3 (LRCLK_OUT3)/Multipurpose, General-Purpose Input/Output (MP9). This pin is bidirectional, with the direction depending on whether Serial Output Port 3 is a master or slave. Disconnect this pin when not in use.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 21 of 202 Pin No. Mnemonic Internal Pull Resistor Description 51 BCLK_OUT3 Configurable Bit Clock, Serial Output Port 3. This pin is bidirectional, with the direction depending on whether Serial Output Port 3 is a master or slave. Disconnect this pin when not in use. 52 SDATA_OUT3 Configurable Serial Data Output Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel, 8-channel, and flexible TDM modes. Disconnect this pin when not in use. 53 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass Pin 53 with decoupling capacitors to Pin 54 (DGND). See the Power Supply Bypass Capacitors and Grounding sections. 54 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 55 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. 56 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to Pin 55 (DGND). See the Power Supply Bypass Capacitors and Grounding sections. 57 BCLK_IN0 Configurable Bit Clock, Serial Input Port 0. This pin is bidirectional, with the direction depending on whether Serial Input Port 0 is a master or slave. Disconnect this pin when not in use.

58 LRCLK_IN0/

Configurable Frame Clock, Serial Input Port 0 (LRCLK_IN0)/Multipurpose, General-Purpose Input/Output (MP10). This pin is bidirectional, with the direction depending on whether Serial Input Port 0 is a master or slave. Disconnect this pin when not in use. 59 SDATA_IN0 Configurable Serial Data Input Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel, or 16-channel mode. Disconnect this pin when not in use. 60 BCLK_IN1 Configurable Bit Clock, Serial Input Port 1. This pin is bidirectional, with the direction depending on whether the Serial Input Port 1 is a master or slave. Disconnect this pin when not in use.

61 LRCLK_IN1/

Configurable Frame Clock, Serial Input Port 1 (LRCLK_IN1)/Multipurpose, General-Purpose Input/Output (MP11). This pin is bidirectional, with the direction depending on whether the Serial Input Port 1 is a master or slave. Disconnect this pin when not in use. 62 SDATA_IN1 Configurable Serial Data Input Port 1 (Channels 16 to Channel 31). Capable of 2-channel, 4-channel, 8-channel, or 16-channel mode. Disconnect this pin when not in use. 63 THD_M None Thermal Diode Negative (−) Input. Connect this pin to the D− pin of an external temperature sensor IC. Disconnect this pin when not in use. 64 THD_P None Thermal Diode Positive (+) Input. Connect this pin to the D+ pin of an external temperature sensor IC. Disconnect this pin when not in use. 65 BCLK_IN2 Configurable Bit Clock, Serial Input Port 2. This pin is bidirectional, with the direction depending on whether the Serial Input Port 2 is a master or slave. Disconnect this pin when not in use.

66 LRCLK_IN2/

Configurable Frame Clock, Input Serial Port 2 (LRCLK_IN2)/Multipurpose, General-Purpose Input/Output (MP12). This pin is bidirectional, with the direction depending on whether Serial Input Port 2 is a master or slave. Disconnect this pin when not in use. 67 SDATA_IN2 Configurable Serial Data Input Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8-channel, or flexible TDM mode. Disconnect this pin when not in use. 68 BCLK_IN3 Configurable Bit Clock, Input Serial Port 3. This pin is bidirectional, with the direction depending on whether Input Serial Port 3 is a master or slave. Disconnect this pin when not in use.

69 LRCLK_IN3/

Configurable Frame Clock, Serial Input Port 3 (LRCLK_IN3)/Multipurpose, General-Purpose Input/Output (MP13). This pin is bidirectional, with the direction depending on whether Serial Input Port 3 is a master or slave. Disconnect this pin when not in use. 70 SDATA_IN3 Configurable Serial Data Input Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel, 8-channel, or flexible TDM mode. Disconnect this pin when not in use. 71 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass with decoupling capacitors to Pin 72 (DGND). 72 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. See the Power Supply Bypass Capacitors and Grounding sections. EP Exposed Pad None The exposed pad must be grounded by soldering it to a copper square of equivalent size on the PCB. Identical copper squares must exist on all layers of the board, connected by vias, and they must be connected to a dedicated copper ground layer within the PCB. See Exposed Pad PCB Design, Figure 87, and Figure 88.

Figure 12. System Block Diagram with Example Connections to External Components outputs, SigmaDSP core, and integrated sample rate converters. third party branded algorithms. flexibility without requiring hardware design changes. codecs that use similar flexible TDM streams.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 23 of 202 The DSP core is optimized for audio processing, and it can process audio at sample rates of up to 192 kHz. The program and parameter/data RAMs can be loaded with a custom audio processing signal flow built with the SigmaStudio graphical programming software from Analog Devices, Inc., which is available for download at www.analog.com. The values that are stored in the parameter RAM can control individual signal processing blocks, such as infinite impulse response (IIR) and finite impulse response (FIR) equalization filters, dynamics processors, audio delays, and mixer levels. A software safeload feature allows transparent parameter updates and prevents clicks on the output signals. Reliability features, such as memory parity checking and a program counter watchdog, help ensure that the system can detect and recover from any errors related to memory corruption. On the ADAU1462/ADAU1466, the audio data in an S/PDIF stream can be routed through an ASRC for processing in the DSP or can be sent directly to a serial audio output. Other components of the stream, including status and user bits, are not lost and can be used in algorithm or output on the MPx pins. The user can also independently program the nonaudio data that is embedded in the output signal of the S/PDIF transmitter. The 14 MPx pins are available to provide a simple user interface without the need for an external microcontroller. These multi- purpose pins are available to input external control signals and output flags or controls to other devices in the system. As inputs, the MPx pins can be connected to push buttons, switches, rotary encoders, or other external control circuitry to control the internal signal processing program. When configured as outputs, these pins can drive LEDs (with a buffer), output flags to a microcontroller, control other ICs, or connect to other external circuitry in an application. In addition to the multipurpose pins, six dedicated input pins (AUXADC5 to AUXADC0) are connected to an auxiliary ADC for use with analog controls such as potentiometers or system voltages. The SigmaStudio software programs and controls the device through the control port. In addition to designing and tuning a signal flow, the software can configure all of the DSP registers in real time and download a new program and parameters into the external self boot EEPROM. The SigmaStudio graphical interface allows anyone with audio processing knowledge to design a DSP signal flow and export production quality code without the need for writing text code. The software provides enough flexibility and programmability to allow an experienced DSP programmer to have in-depth control of the design. Algorithms are created in SigmaStudio by dragging and dropping signal processing cells from the library, connecting them together in a flow, compiling the design, and downloading the executable program and parameters to the SigmaDSP memory through the control port. The tasks of linking, compiling, and downloading the project are all handled automatically by the software. The signal processing cells included in the library range from primitive operations, such as addition and gain, to large and highly optimized building blocks. For example, the libraries include the following:  Single and double precision biquad filter  Monochannel and multichannel dynamics processors with peak or rms detection  Mixer and splitter  Tone and noise generator  Fixed and variable gain  Loudness  Delay  Stereo enhancement  Dynamic bass boost  Noise and tone source  Level detector  MPx pin control and conditioning  FFT and frequency domain processing algorithms Analog Devices continuously develops new processing algorithms and provides proprietary and third party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Several power saving mechanisms are available, including programmable pad strength for digital I/O pins and the ability to power down unused subsystems. Fabricated on a single monolithic integrated circuit for operation over the −40°C to +105°C temperature range, the device is housed in a 72-lead LFCSP package with an exposed pad to assist in heat dissipation. The device can be controlled in one of two operational modes, as follows:  The s ettings of the chip can be loaded and dynamically updated through the SPI/I2C port via SigmaStudio or a processor in the system.  The DSP can self boot from an external EEPROM in a system with no microcontroller.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 25 of 202 S T E P 123456789 1 0 1 1 1 2 IOVDD PINS PVDD PIN AVDD PIN DVDD PINS IOVDD TO DVDD LEVEL SHIFTER ENABLE (INTERNAL) PVDD TO DVDD LEVEL SHIFTER ENABLE (INTERNAL) AVDD TO DVDD LEVEL SHIFTER ENABLE (INTERNAL) RESET PIN RESET (INTERNAL) MASTER POWER-ON RESET (INTERNAL) XTALIN/MCLK PIN CLOCK INPUT TO THE PLL PLL OUTPUT CLOCK

DESCRIPTION

STARTING CONDITIONS. ALL SIGNALS ARE LOW. IF POWER SUPPLIES ARE SEPARATE, APPLY VOLTAGE TO IOVDD FIRST. APPLY MASTER CLOCK SIGNAL TO XTALIN/MCLK, UNLESS MASTER CLOCK IS AUTOMATICALLY GENERATED USING A CRYSTAL OSCILLATOR CIRCUIT. SUPPLY PVDD AT THE SAME TIME, OR AFTER, IOVDD. DO NOT BRING UP PVDD BEFORE IOVDD. SUPPLY AVDD AT THE SAME TIME, OR AFTER, IOVDD. DO NOT BRING UP AVDD BEFORE IOVDD. IF DVDD IS EXTERNALLY SUPPLIED, SUPPLY IT AT THE SAME TIME AS IOVDD AND PVDD, OR AFTER PVDD. DO NOT BRING IT UP BEFORE IOVDD OR PVDD. AFTER ALL SUPPLIES REACH THEIR NOMINAL LEVELS, THE LEVEL SHIFTERS ACTIVATE, ALLOWING SIGNALS TO PASS INTERNALLY BETWEEN POWER DOMAINS. WHEN THE IOVDD TO DVDD AND PVDD TO DVDD LEVEL SHIFTERS BECOME ACTIVE, THE MASTER CLOCK INPUT SIGNAL IS PASSED TO THE PLL. IF THE RESET PIN IS NOTALREADY HIGH, PULL IT HIGH AT ANY TIME. (AT THE BEGINNING OF A POWER SEQUENCE, THE STATE OF THE RESET PIN IS DON’T CARE.) THE INTERNAL RESET SIGNAL GOES HIGH WHEN THE FOLLOWING CONDITIONSARE TRUE: ALL POWER SUPPLIES ARE VALID, AND THE RESET PIN IS LOGIC HIGH. WHEN THE INTERNAL RESET GOES HIGH, THE DSP CORE RUNS INITIALIZATION CODE, WHICH REQUIRES EIGHT CYCLES OF THE XTALIN/MCLK SIGNAL. AT 12.2888MHz, THE PROCESS REQUIRES 650ns. THE CONTROL PORT IS NOW ACCESSIBLE. PROGRAM THE PLL USING REGISTER WRITES. THE PLL THEN LOCKS, REQUIRING A MAXIMUM OF 10.666ms. AFTER THE PLL LOCKS, OTHER REGISTERS CAN BE PROGRAMMED, AND THE DSP CAN START RUNNING. 14810-013 Figure 13. Power Sequencing and POR Timing Diagram for a System with Separate Power Supplies

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 26 of 202 System Initialization Sequence Before the IC can process the audio in the DSP , the following initialization sequence must be completed. 1. If possible, apply the required voltage to all four power supply domains (IOVDD, AVDD, PVDD, and DVDD) simultaneously. If simultaneous application is not possible, supply IOVDD first to prevent damage or reduced operating lifetime. If using the on-board regulator, AVDD and PVDD can be supplied in any order, and DVDD is then generated automatically. If not using the on-board regulator, AVDD, PVDD, and DVDD can be supplied in any order following IOVDD. 2. Start providing a master clock signal to the XTALIN/MCLK pin, or, if using the crystal oscillator, let the crystal oscillator start generating a master clock signal. The master clock signal must be valid when the DVDD supply stabilizes. 3. If the SELFBOOT pin is pulled high, a self boot sequence initiates on the master control port. Wait until the self boot operation is complete. 4. If SPI slave control mode is desired, toggle the SS/ADDR0 pin three times. Ensure that each toggle lasts at least the duration of one cycle of the master clock being input to the XTALIN/MCLK pin. When the SS/ADDR0 line rises for the third time, the slave control port is then in SPI mode. 5. Execute the register and memory write sequence that is required to configure the device in the proper operating mode. Table 19 contains an example series of register writes used to configure the system at startup. The contents of the data column may vary depending on the system configuration. The configuration that is listed in Table 19 represents the default initialization sequence for project files generated in SigmaStudio. Recommended Program/Parameter Loading Procedure When writing large amounts of data to the program or parameter RAM in direct write mode (such as when downloading the initial contents of the RAMs from an external memory), use the hibernate register (Address 0xF400) to disable the processor core, thus preventing unpleasant noises from appearing at the audio output. When small amounts of data are transmitted during real-time operation of the DSP (such as when updating individual parameters), the software safeload mechanism can be used (see the Software Safeload section).

Table 19. Example System Initialization Register Write Sequence1 N/A N/A N/A Toggle SS/ADDR0 three times to enable SPI slave mode, if necessary. 0xF890 0x00, 0x00 SOFT_RESET Enter soft reset. 0xF890 0x00, 0x01 SOFT_RESET Exit soft reset. 0xF000 0x00, 0x60 PLL_CTRL0 Set feedback divider to 96 (this is the default power-on setting). 0xF001 0x00, 0x02 PLL_CTRL1 Set PLL input clock divider to 4. 0xF002 0x00, 0x01 PLL_CLK_SRC Set clock source to PLL clock. 0xF005 0x00, 0x05 MCLK_OUT Enable MCLK output (12.288 MHz). 0xF003 0x00, 0x01 PLL_ENABLE Enable PLL. rarely used in most systems). are not being used in the system. 0xF899 0x00, 0x00 SECONDPAGE_ENABLE Toggle the SECONDPAGE_ENABLE to point at host port memory Page 0. provided by SigmaStudio compiler). 0xF899 0x00,0x01 SECONDPAGE_ENABLE Toggle the SECONDPAGE_ENABLE to point at host port memory Page 1. provided by SigmaStudio compiler). provided by SigmaStudio compiler). provided by SigmaStudio compiler). 0xF404 0x00, 0x00 START_ADDRESS Set program start address as defined by the SigmaStudio compiler. 0xF401 0x00, 0x02 START_PULSE Set DSP core start pulse to internally generated pulse. N/A N/A N/A Configure any other registers that require nondefault values. 0xF402 0x00, 0x00 START_CORE Stop the core. 0xF402 0x00, 0x01 START_CORE Start the core. N/A N/A N/A Wait 50 μs for initialization program to execute.

Table 20. Optimal Predivider and Feedback Divider Settings for Varying Input MCLK Frequencies

(START_PULSE), Bits[4:0] (START_PULSE). available instructions (see Table 21). filter works for the full frequency range of the PLL. Figure 16. PLL Filter is typically between 1.65 V and 2.10 V . Table 21. Maximum Instructions/Sample

1 The instructions per sample in these cases exceed the program memory

subroutines or branches are required in the SigmaStudio program.

32 BCLK/sample, 64 BCLK/sample, 128 BCLK/sample, 256 BCLK/

Input Frequency is the PLL output (nominally 294.912 MHz). Output Frequency is the frame clock output frequency. generator configuration registers. frequency of the nominal output frequency. tor (N) and the integer denominator (M) are each nine bits long. a higher precision when generating arbitrary clock frequencies. clock is multiplied when passing through that block.

294.912 MHz ÷ 1024 × 1 ÷ 6 = 48 kHz

294.912 MHz ÷ 1024 × 1 ÷ 9 = 32 kHz

Figure 17. PLL and Clock Generators Block Diagram Figure 18. PLL and Audio Clock Generators with Default Settings and Resulting Clock Frequencies Labeled, XTALIN/MCLK = 12.288 MHz

Figure 19. PLL and Audio Clock Generators with Default Settings and Resulting Clock Frequencies Labeled, XTALIN/MCLK = 11.2896 MHz

270.9504 MHz ÷ 1024 × 80 ÷ 441 = 48 kHz

by the setting of the MCLK_OUT register (Address 0xF005). for a nominal system clock of 294.912 MHz. a nominal system clock of 294.912 MHz. for a nominal system clock of 294.912 MHz. a nominal system clock of 294.912 MHz. Figure 20. Clock Output Generator drive long cables or other high impedance transmission lines. require interaction or control from the user.

Clock Generator Registers section. Table 22. Master Clock, PLL, and Clock Generator Registers supplies: IOVDD, DVDD, AVDD, and PVDD. IOVDD supply must be present. digital logic circuitry. It must be 1.2 V ± 5%. even if the PLL is not in use. Table 23. Power Supply Details

1.8 V − 5% to

3.3 V + 10%

internal structure of the regulator is shown in Figure 22. emitter and base to help stabilize the regulator for varying loads. flowing into the VDRIVE pin, even for minimal regulator loads. Figure 21 shows the connection of the external components. Figure 21. External Components Required for Voltage Regulator Circuit not use the regulator to provide a voltage supply to external ICs. There are no control registers associated with the regulator. Figure 22. Simplified Block Diagram of Regulator Internal Structure, Including External Components

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 35 of 202 SLAVE CONTROL PORTS A total of four control ports are available: two slave ports and two master ports. The slave I2C port and slave SPI port allow an external master device to modify the contents of the memory and registers. The master I2C port and master SPI port allow the device to self boot and to send control messages to slave devices on the same bus. Slave Control Port Overview To program the DSP and configure the control registers, a slave port is available that can communicate using either the I2C or SPI protocols. Any external device that controls the ADAU1462/ ADAU1466, including a hardware interface used with SigmaStudio for development or a microcontroller in a large running system, uses the slave control port to communicate with the DSP . This port is unrelated to the master communications port that also uses the I 2C or SPI protocols. The master port enables applications without an external controller and can read from an external EEPROM to self boot and control external ICs. The slave communications port defaults to I 2C mode; however, it can be put into SPI mode by toggling SS (SS/ADDR0), the slave select pin, from high to low three times. The slave select pin must be held low for at least one master clock period (that is, one period of the clock on the XTALIN_MCLK input pin). Only the PLL configuration registers (0xF000 to 0xF004) are accessible before the PLL locks. For this reason, always write to the PLL registers first after the chip powers up. After the PLL locks, the remaining registers and the RAM become accessible. See the System Initialization Sequence section for more information. SLAVE CONTROL PORT ADDRESSING Unlike earlier SigmaDSP processors, the ADAU1462/ADAU1466 slave control port 16-bit addressing cannot provide direct access to the total amount of memory available to the DSP core on its wider internal busses. Full read/write access to all memory and addressable registers is possible, but it must be accessed as two pages of memory in the slave control port address space. Page 0 is referred to as lower memory and Page 1 as upper memory. The single-bit register SECONDPAGE_ENABLE (0xF899) selects the active page. Within a page, all addresses are accessible using both single address mode and burst mode. The first byte (Byte 0) of a control port write contains the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) together form the subaddress of the register location within the memory maps of the ADAU1462/ADAU1466. This subaddress must be two bytes long because the memory locations within the devices are directly addressable, and their sizes exceed the range of single byte addressing. The third byte to the end of the sequence contain the data, such as control port data, program data, or parameter data. The number of bytes written per word depends on the type of data. For more information, see the Burst Mode Writing and Reading section. The ADAU1462/ADAU1466 must have a valid master clock to write to the slave control port, with the exception of the PLL configuration registers, 0xF000 to 0xF004. If large blocks of data must be downloaded, halt the output of the DSP core (using Register 0xF400, HIBERNATE), load new data, and then restart the device (using Register 0xF402, START_CORE). This process is most common during the booting sequence at startup or when loading a new program into RAM because the ADAU1462/ADAU1466 has several mechanisms for updating signal processing parameters in real time without causing pops or clicks. When updating a signal processing parameter while the DSP core is running, use the software safeload function. This function allows atomic writes to memory and prevents updates to parameters across the boundary of an audio frame, which can lead to an audio artifact such as a click or pop sound. For more information, see the Software Safeload section. The slave control port supports either I 2C or SPI, but not simultaneously. The function of each pin is described in Table 25 for the two modes. Burst Mode Writing and Reading Burst write and read modes are available for convenience when writing large amounts of data to contiguous registers. In these modes, the chip and memory addresses are written once, and then a large amount of data can follow uninterrupted. The sub- addresses are automatically incremented at the word boundaries. This increment happens automatically after a single word write or read unless a stop condition is encountered (I 2C mode) or the slave select is disabled and brought high (SPI mode). A burst write starts like a single word write, but, following the first data-word, the data-word for the next address can be written immediately without sending its 2-byte address. The control registers in the ADAU1462/ADAU1466 are two bytes wide, and the memories are four bytes wide. The auto-increment feature knows the word length at each subaddress; therefore, it is not necessary to manually specify the subaddress for each address in a burst write. The subaddresses are automatically incremented by one address, following each read or write of a data-word, regardless of whether there is a valid register or RAM word at that address.

Table 25. Control Port Pin Functions points to the lower or upper areas of PM, DM0, and DM1. addressing is contiguous and seamless to the DSP core. SECONDPAGE_ENABLE has no effect on these registers. the value of Address 0x0000 in DM1 memory. the value of Address 0x4FFF in DM1 memory. the value of Address 0x5000 in DM1 memory. the value of Address 0x9FFF in DM1 memory.

Figure 26. ADAU1462 Slave Port Address to DSP Core Address Mapping

Figure 27. ADAU1466 Slave Port Address to DSP Core Address Mapping

01110 R / W

Figure 28. I2C Slave Single Word Write Operation (Two Bytes)

01110 R/W

Figure 29. I2C Slave Burst Mode Write Operation (N Bytes) Figure 30. I2C Slave Burst Mode Read Operation (N Bytes) Figure 31 shows the format of a single word write operation. acknowledge by pulling SDA low. address increments after the appropriate number of bytes.  AM means acknowledge by master.  AS means acknowledge by slave.

select signals (SS). See Table 30 for more information. therefore, no other master devices can exist on the same SPI bus. serial RAM devices and was confirmed to work in all cases.

10 MHz or higher), a condition may arise where there is a high

ming on the part of the user. fast mode operation with speeds between 20 kHz and 400 kHz. 8-bit aligned. No error detection or correction is implemented. pins, MP2 and MP3. See Table 31 for more information. Table 30. SPI Master Interface Pin Functionality SCL_M/SCLK_M/MP2 SCLK SPI master port serial clock. This pin driv es the clock signal to slave devices on the SPI master bus. SDA_M/MISO_M/MP3 MISO SPI master port data input. This pin receives data from slave devices on the SPI master bus. Table 31. I2C Master Interface Pin Functionality slave devices on the I2C bus. The line connected to this pin must have a 2.0 kΩ pull-up resistor to IOVDD.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 45 of 202 SELF BOOT The master control port is capable of booting the device from a single EEPROM by connecting the SELFBOOT pin to logic high (IOVDD) and powering up the power supplies while the RESET pin is pulled high. This initiates a self boot operation, in which the master control port downloads all required memory and register settings and automatically starts executing the DSP program without requiring external intervention or supervision. A self boot operation can also be triggered while the device is already in operation by initiating a rising edge of the RESET pin while the SELFBOOT pin is held high. When the self boot operation begins, the state of the SS_M/MP0 pin determines whether the SPI master or the I 2C master carries out the self boot operation. If the SS_M/MP0 pin is connected to logic low, the I2C master port carries out the self boot operation. Otherwise, connect this pin to the slave select pin of the external slave device. The SPI master port then carries out the self boot operation. When self booting from SPI, the chip assumes the following:  The slave EEPROM is selected via the SS_M/MP0 pin.  The slave EEPROM has 16-bit or 24-bit addressing, giving it a total memory size of between 4 kb and 64 Mb.  The slave EEPROM supports serial clock frequencies down to 1 MHz or lower (a majority of the self boot operation uses a much higher clock frequency, but the initial transactions are performed at a slower frequency).  The data stored in the slave EEPROM follows the format described in the EEPROM Self Boot Data Format section.  The data is stored in the slave EEPROM with the MSB first.  The slave EEPROM supports SPI Mode 3.  The slave EEPROM sequential read operation has the command of 0x03.  The slave EEPROM can be accessed immediately after it is powered up, with no manual configuration required. When self booting from I 2C, the chip assumes the following:  The slave EEPROM has I2C Address 0x50.  The slave EEPROM has 16-bit addressing, giving it a size of between 16 kb and 512 kb.  The slave EEPROM supports standard mode clock frequencies of 100 kHz and lower (a majority of the self boot operation uses a much higher clock frequency, but the initial transactions are performed at a slower frequency).  The data stored in the slave EEPROM follows the format described in the EEPROM Self Boot Data Format section.  The slave EEPROM can be accessed immediately after it is powered, with no manual configuration required. Self Boot Failure The SPI or I2C master port attempts to self boot from the EEPROM three times. If all three self boot attempts fail, the SigmaDSP core issues a software panic and then enters a sleep state. During a self boot operation, the panic manager is unable to output a panic flag on a multipurpose pin. Therefore, the only way to debug a self boot failure is by reading back the status of Register 0xF427 (PANIC_FLAG) and Register 0xF428 (PANIC_CODE). The contents of Register 0xF428 indicate the nature of the failure.

details of the data format are described in this section. arbitrary number of variable length blocks, and a fixed footer. in the DSP memory through configuration of the block header. EEPROM memory (see Figure 41). and address of the data, followed by a series of 4-byte data packets.  One LST bit, which signals the last block before the footer. additional blocks are still to follow.  13 bits that are reserved for future use. Set these bits to 0b0. ignored unless the LST bit is set to 0b1. of packets is defined by the 16-bit data length.

10101010 A D D R E S S O F F I R S T B O O T B L O C K

Figure 40. Self Boot EEPROM Header Format Figure 41. Self Boot EEPROM Data Block Format

memory allocation varies, depending on the EEPROM design. exists in a separate EEPROM. bus, the self boot mechanism works only with the first EEPROM. Figure 42. Self Boot EEPROM Footer Format

the audio is routed between different functional blocks. its available audio data connections. in the IO folder of the SigmaStudio algorithm toolbox. Figure 43. Audio Routing Overview

serial input pins (see Table 32). SigmaStudio, including their graphical appearance in the software. Table 32. Serial Input Pin Mapping to SigmaStudio Input Cells Table 33. Detailed Serial Input Mapping to SigmaStudio Input Channels

Figure 44. Serial Port Audio Input Mapping to DSP in SigmaStudio

the SDATA_OUT3 pin (see Table 36 and Figure 47). Table 36. Serial Output Pin Mapping from SigmaStudio Channels

0 SDATA_OUT0 Left 0 0 0

1 SDATA_OUT0 Right 1 1 1

2 SDATA_OUT0 Not applicable 2 2 2

3 SDATA_OUT0 Not applicable 3 3 3

4 SDATA_OUT0 Not applicable Not applicable 4 4

5 SDATA_OUT0 Not applicable Not applicable 5 5

6 SDATA_OUT0 Not applicable Not applicable 6 6

7 SDATA_OUT0 Not applicable Not applicable 7 7

8 SDATA_OUT0 Not applicable Not applicable Not applicable 8

9 SDATA_OUT0 Not applicable Not applicable Not applicable 9

10 SDATA_OUT0 Not applicable Not applicable Not applicable 10

11 SDATA_OUT0 Not applicable Not applicable Not applicable 11

12 SDATA_OUT0 Not applicable Not applicable Not applicable 12

13 SDATA_OUT0 Not applicable Not applicable Not applicable 13

14 SDATA_OUT0 Not applicable Not applicable Not applicable 14

15 SDATA_OUT0 Not applicable Not applicable Not applicable 15

16 SDATA_OUT1 Left 0 0 0

17 SDATA_OUT1 Right 1 1 1

18 SDATA_OUT1 Not applicable 2 2 2

19 SDATA_OUT1 Not applicable 3 3 3

20 SDATA_OUT1 Not applicable Not applicable 4 4

21 SDATA_OUT1 Not applicable Not applicable 5 5

22 SDATA_OUT1 Not applicable Not applicable 6 6

23 SDATA_OUT1 Not applicable Not applicable 7 7

24 SDATA_OUT1 Not applicable Not applicable Not applicable 8

25 SDATA_OUT1 Not applicable Not applicable Not applicable 9

26 SDATA_OUT1 Not applicable Not applicable Not applicable 10

27 SDATA_OUT1 Not applicable Not applicable Not applicable 11

28 SDATA_OUT1 Not applicable Not applicable Not applicable 12

29 SDATA_OUT1 Not applicable Not applicable Not applicable 13

30 SDATA_OUT1 Not applicable Not applicable Not applicable 14

31 SDATA_OUT1 Not applicable Not applicable Not applicable 15

32 SDATA_OUT2 Left 0 0 0

33 SDATA_OUT2 Right 1 1 1

34 SDATA_OUT2 Not applicable 2 2 2

35 SDATA_OUT2 Not applicable 3 3 3

36 SDATA_OUT2 Not applicable Not applicable 4 4

37 SDATA_OUT2 Not applicable Not applicable 5 5

38 SDATA_OUT2 Not applicable Not applicable 6 6

39 SDATA_OUT2 Not applicable Not applicable 7 7

40 SDATA_OUT3 Left 0 0 0

41 SDATA_OUT3 Right 1 1 1

42 SDATA_OUT3 Not applicable 2 2 2

43 SDATA_OUT3 Not applicable 3 3 3

44 SDATA_OUT3 Not applicable Not applicable 4 4

45 SDATA_OUT3 Not applicable Not applicable 5 5

46 SDATA_OUT3 Not applicable Not applicable 6 6

47 SDATA_OUT3 Not applicable Not applicable 7 7

Figure 47. DSP to Serial Output Mapping in SigmaStudio PDM microphone inputs, the S/PDIF receiver, or the ASRCs. Figure 48. Configuring the Serial Output Data Channels (SOUT_SOURCEx controlled by Register 0xF1C0 (SPDIFTX_INPUT). Figure 49. S/PDIF Transmitter Source Selection output cells in SigmaStudio. Table 37. S/PDIF Output Mapping from SigmaStudio Channels

0 Left

1 Right

Figure 50. DSP to S/PDIF Transmitter Output Mapping in SigmaStudio

accordingly. For more information, see Figure 60 and Table 38. Table 38. For more detailed information, see the Audio Signal

16 CHASRC TO DSP

Figure 60. ASRC Outputs Table 38. Audio Routing Matrix Registers

and SDATA_OUT1 are capable of 16-channel mode. Serial Port Configuration Registers section. the audio data and clocks as they pass in and out of the device. Table 39 describes this relationship. Table 39. Relationship Between Hardware Serial Data Pins distribution is described in Table 40. ports is 192 kHz. The minimum sample rate is 6 kHz. where the data for each channel is located in the serial data stream. Flexible TDM Interface section for more information. configurations for each serial audio port. text accompanies each figure. Table 40. Relationship Between Data Pin, Audio Channels, Clock Pins, and TDM Options

SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b001). The bit clock signal is omitted from the figure. (DATA_FMT)), all of which are shown in Figure 62.

8 BITS

16 BITS IDLE 16 BITS IDLE16 BITS IDLE

16 BITS IDLE

16 BITS IDLE16 BITS IDLE

THE AUDIO DATA CROSSES THE THRESHOLD BETWEEN TWO FRAMES, WHICH MAY VIOLATE THE SPECIFICATIONS OF OTHER DEVICES IN THE SYSTEM. Figure 62. Serial Audio Data Formats; Four Channels, 32 Bits per Channel

Table 41. Relationship Between Serial Data Pins and Clock Pins in Master or Slave Mode

Figure 69. 24-Bit Serial Input Example

8 ZEROS

7 MSBs

1 LSB

Figure 70. 24-Bit Serial Output Example

Table 44. Serial Port Registers

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 68 of 202 FLEXIBLE TDM INTERFACE The flexible TDM interface is available as an optional mode of operation on the SDATA_IN2 and SDATA_IN3 serial input ports, as well as on the SDATA_OUT2 and SDATA_OUT3 serial output ports. To use flexible TDM mode, the corresponding serial ports must be set in flexible TDM mode (SERIAL_BYTE_x_0 register, Bits[6:5] (WORD_LEN) = 0b11 and SERIAL_BYTE_x_0 register, Bits[2:0] = 0b010). Flexible TDM input mode requires that both SDATA_IN2 and SDATA_IN3 be configured for flexible TDM mode. Likewise, flexible TDM output mode requires that both SDATA_OUT2 and SDATA_OUT3 pins be configured for flexible TDM mode. The flexible TDM interface provides byte addressable data place- ment in the input and output data streams on the corresponding serial data input/output pins. Each data stream is configured like a standard 8-channel TDM interface, with a total of 256 data bits (or 32 bytes) in the span of an audio frame. Because flexible TDM mode runs on two pins simultaneously, and each pin has 32 bytes of data, this means that there are a total of 64 data bytes. In flexible TDM input mode, each input channel inside the device can select its source data from any of the 64 input data bytes. In flexible TDM output mode, any serial output channel can be routed to any of the 64 output data bytes. Flexible TDM Input In flexible TDM input mode, two 256-bit data streams are input to the SDATA_IN2 and SDATA_IN3 pins. These 256 bits of data compose eight channels of four bytes each, for a total of 32 bytes on each pin, and a total of 64 bytes when both input pins are combined. The flexible TDM input functional block routes the desired input byte to a given byte in the serial input channels. Those serial input channels are then available as normal audio data in the audio routing matrix. The data can be passed to the DSP core, the ASRC inputs, or the serial outputs as needed. There are a total of 64 control registers (FTDM_INx) that can be configured to set up the mapping of input data bytes to the corresponding bytes in the serial input channels. Each byte in each serial input channel has a corresponding control register, which selects the incoming data byte on the serial input pins that must be mapped to it. Figure 71 shows, from left to right, the data streams entering the serial input pins, the serial input channels, and the registers (see FTDM_INx, Register 0xF300 to Register 0xF33F) that correspond to each byte in the serial input channels. Flexible TDM Output In flexible TDM output mode, two 256-bit data streams are output from the SDATA_OUT2 and SDATA_OUT3 pins. These 256 bits of data compose eight channels of four bytes each, for a total of 32 bytes on each pin, and a total of 64 bytes when both input pins are combined. The flexible TDM output functional block routes the desired byte from the desired serial output channel to a given byte in the output streams. The serial output channels originate from the audio routing matrix, which is configured using the SOUT_SOURCEx control registers. There are a total of 64 control registers (see FTDM_OUTx, Register 0xF388 to Register 0xF3BF) that can be configured to set up the mapping of the bytes in the serial output channels and the bytes in the data streams exiting the serial output pins. Each byte in the data streams being output from the serial output pins has a corresponding control register, which selects the desired byte from the desired serial output channel. Figure 72 shows, from left to right, the serial output channels originating from the routing matrix, the serial output pins and data streams, and the control registers (FTDM_OUTx) that correspond to each byte in the serial output data streams.

Figure 71. Flexible TDM Input Mapping

Figure 72. Flexible TDM Output Mapping

TDM Interface Registers section. Table 45. Flexible TDM Registers

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 72 of 202 Address Register Description 0xF330 FTDM_IN48 FTDM mapping for the se rial inputs (Channel 44, Bits[31:24]) 0xF331 FTDM_IN49 FTDM mapping for the se rial inputs (Channel 44, Bits[23:16]) 0xF332 FTDM_IN50 FTDM mapping for the se rial inputs (Channel 44, Bits[15:8]) 0xF333 FTDM_IN51 FTDM mapping for the se rial inputs (Channel 44, Bits[7:0]) 0xF334 FTDM_IN52 FTDM mapping for the se rial inputs (Channel 45, Bits[31:24]) 0xF335 FTDM_IN53 FTDM mapping for the se rial inputs (Channel 45, Bits[23:16]) 0xF336 FTDM_IN54 FTDM mapping for the se rial inputs (Channel 45, Bits[15:8]) 0xF337 FTDM_IN55 FTDM mapping for the se rial inputs (Channel 45, Bits[7:0]) 0xF338 FTDM_IN56 FTDM mapping for the se rial inputs (Channel 46, Bits[31:24]) 0xF339 FTDM_IN57 FTDM mapping for the se rial inputs (Channel 46, Bits[23:16]) 0xF33A FTDM_IN58 FTDM mapping for the serial inputs (Channel 46, Bits[15:8]) 0xF33B FTDM_IN59 FTDM mapping for the serial inputs (Channel 46, Bits[7:0]) 0xF33C FTDM_IN60 FTDM mapping for the serial inputs (Channel 47, Bits[31:24]) 0xF33D FTDM_IN61 FTDM mapping for the serial inputs (Channel 47, Bits[23:16]) 0xF33E FTDM_IN62 FTDM mapping for the serial inputs (Channel 47, Bits[15:8]) 0xF33F FTDM_IN63 FTDM mapping for the serial inputs (Channel 47, Bits[7:0]) 0xF380 FTDM_OUT0 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[31:24]) 0xF381 FTDM_OUT1 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[23:16]) 0xF382 FTDM_OUT2 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[15:8]) 0xF383 FTDM_OUT3 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[7:0]) 0xF384 FTDM_OUT4 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[31:24]) 0xF385 FTDM_OUT5 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[23:16]) 0xF386 FTDM_OUT6 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[15:8]) 0xF387 FTDM_OUT7 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[7:0]) 0xF388 FTDM_OUT8 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[31:24]) 0xF389 FTDM_OUT9 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[23:16]) 0xF38A FTDM_OUT10 FTDM mapping for the seri al outputs (Port 2, Channel 2, Bits[15:8]) 0xF38B FTDM_OUT11 FTDM mapping for the seri al outputs (Port 2, Channel 2, Bits[7:0]) 0xF38C FTDM_OUT12 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[31:24]) 0xF38D FTDM_OUT13 FTDM mapping for the seri al outputs (Port 2, Channel 3, Bits[23:16]) 0xF38E FTDM_OUT14 FTDM mapping for the seri al outputs (Port 2, Channel 3, Bits[15:8]) 0xF38F FTDM_OUT15 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[7:0]) 0xF390 FTDM_OUT16 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[31:24]) 0xF391 FTDM_OUT17 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[23:16]) 0xF392 FTDM_OUT18 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[15:8]) 0xF393 FTDM_OUT19 FTDM mapping for the seri al outputs (Port 2, Channel 4, Bits[7:0]) 0xF394 FTDM_OUT20 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[31:24]) 0xF395 FTDM_OUT21 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[23:16]) 0xF396 FTDM_OUT22 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[15:8]) 0xF397 FTDM_OUT23 FTDM mapping for the seri al outputs (Port 2, Channel 5, Bits[7:0]) 0xF398 FTDM_OUT24 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[31:24]) 0xF399 FTDM_OUT25 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[23:16]) 0xF39A FTDM_OUT26 FTDM mapping for the seri al outputs (Port 2, Channel 6, Bits[15:8]) 0xF39B FTDM_OUT27 FTDM mapping for the seri al outputs (Port 2, Channel 6, Bits[7:0]) 0xF39C FTDM_OUT28 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[31:24]) 0xF39D FTDM_OUT29 FTDM mapping for the seri al outputs (Port 2, Channel 7, Bits[23:16]) 0xF39E FTDM_OUT30 FTDM mapping for the seri al outputs (Port 2, Channel 7, Bits[15:8]) 0xF39F FTDM_OUT31 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[7:0]) 0xF3A0 FTDM_OUT32 FTDM mapping for the seri al outputs (Port 3, Channel 0, Bits[31:24]) 0xF3A1 FTDM_OUT33 FTDM mapping for the seri al outputs (Port 3, Channel 0, Bits[23:16]) 0xF3A2 FTDM_OUT34 FTDM mapping for the seri al outputs (Port 3, Channel 0, Bits[15:8]) 0xF3A3 FTDM_OUT35 FTDM mapping for the seri al outputs (Port 3, Channel 0, Bits[7:0]) 0xF3A4 FTDM_OUT36 FTDM mapping for the seri al outputs (Port 3, Channel 1, Bits[31:24])

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 73 of 202 Address Register Description 0xF3A5 FTDM_OUT37 FTDM mapping for the seri al outputs (Port 3, Channel 1, Bits[23:16]) 0xF3A6 FTDM_OUT38 FTDM mapping for the seri al outputs (Port 3, Channel 1, Bits[15:8]) 0xF3A7 FTDM_OUT39 FTDM mapping for the seri al outputs (Port 3, Channel 1, Bits[7:0]) 0xF3A8 FTDM_OUT40 FTDM mapping for the seri al outputs (Port 3, Channel 2, Bits[31:24]) 0xF3A9 FTDM_OUT41 FTDM mapping for the seri al outputs (Port 3, Channel 2, Bits[23:16]) 0xF3AA FTDM_OUT42 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[15:8]) 0xF3AB FTDM_OUT43 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[7:0]) 0xF3AC FTDM_OUT44 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[31:24]) 0xF3AD FTDM_OUT45 FTDM mapping for the seri al outputs (Port 3, Channel 3, Bits[23:16]) 0xF3AE FTDM_OUT46 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[15:8]) 0xF3AF FTDM_OUT47 FTDM mapping for the seri al outputs (Port 3, Channel 3, Bits[7:0]) 0xF3B0 FTDM_OUT48 FTDM mapping for the seri al outputs (Port 3, Channel 4, Bits[31:24]) 0xF3B1 FTDM_OUT49 FTDM mapping for the seri al outputs (Port 3, Channel 4, Bits[23:16]) 0xF3B2 FTDM_OUT50 FTDM mapping for the seri al outputs (Port 3, Channel 4, Bits[15:8]) 0xF3B3 FTDM_OUT51 FTDM mapping for the seri al outputs (Port 3, Channel 4, Bits[7:0]) 0xF3B4 FTDM_OUT52 FTDM mapping for the seri al outputs (Port 3, Channel 5, Bits[31:24]) 0xF3B5 FTDM_OUT53 FTDM mapping for the seri al outputs (Port 3, Channel 5, Bits[23:16]) 0xF3B6 FTDM_OUT54 FTDM mapping for the seri al outputs (Port 3, Channel 5, Bits[15:8]) 0xF3B7 FTDM_OUT55 FTDM mapping for the seri al outputs (Port 3, Channel 5, Bits[7:0]) 0xF3B8 FTDM_OUT56 FTDM mapping for the seri al outputs (Port 3, Channel 6, Bits[31:24]) 0xF3B9 FTDM_OUT57 FTDM mapping for the seri al outputs (Port 3, Channel 6, Bits[23:16]) 0xF3BA FTDM_OUT58 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[15:8]) 0xF3BB FTDM_OUT59 FTDM mapping for the seri al outputs (Port 3, Channel 6, Bits[7:0]) 0xF3BC FTDM_OUT60 FTDM mapping for the seri al outputs (Port 3, Channel 7, Bits[31:24]) 0xF3BD FTDM_OUT61 FTDM mapping for the seri al outputs (Port 3, Channel 7, Bits[23:16]) 0xF3BE FTDM_OUT62 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[15:8]) 0xF3BF FTDM_OUT63 FTDM mapping for the seri al outputs (Port 3, Channel 7, Bits[7:0])

accurate representation of the data input. to ASRC 6; and Channel 14 and Channel 15 belong to ASRC 7. ASRC is configured using the ASRC_OUT_RATEx registers. Audio Signal Routing section. where GDS is the group delay in seconds. successfully locked to the incoming signal. preferable to using Register 0xF581. Table 46. For a more detailed description, refer to the ASRC Status and Control Registers section. Table 46. Asynchronous Sample Rate Converters Registers clock signal is embedded in the data using biphase mark code. word lengths can be independently set to 16, 20, or 24 bits. specification. It does not meet the AES3 professional specification. must be routed through an ASRC. frequencies between 18 kHz and 192 kHz.

below 200 Hz, and a minimum signal voltage of 200 mV . registers in the control register map. format, as shown in Table 47. (TDMOUT) are configured to enable auxiliary output mode. sample rate (see Table 138). Table 47. S/PDIF Auxiliary Output Mode, TDM8 Data Format

3 No data

6 No data

S/PDIF Interface Registers section. Table 48. S/PDIF Interface Registers

Configuration Registers section. Table 50. Multipurpose Pins Registers

24.56-bit format provides more than 42 dB of headroom. available, and circular buffer addressing is possible. initially scaling down the input signal in the DSP signal flow. DSP systems commonly use a standard numeric format. and B is the number of bits to the right of the decimal point. each point in the data flow in both binary and decibel levels.

1.23 FORMAT

8.24 FORMAT

Figure 80. Signal Range for 1.23 Format (Serial Ports, ASRCs) and 8.24 Format (DSP Core)

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 82 of 202 Numerical Format: 8.24 The linear range is −128.0 to (+128.0 − 1 LSB). The dynamic range (ratio of the largest possible signal level to the smallest possible nonzero signal level) is 192 dB. The following are examples of this numerical format: 0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = −128.0 0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xE0000000 = −32.0 0b 1111 1000 0000 0000 0000 0000 0000 0000 = 0xF8000000 = −8.0 0b 1111 1110 0000 0000 0000 0000 0000 0000 = 0xFE000000 = −2 0b 1111 1111 0000 0000 0000 0000 0000 0000 = 0xFF000000 = −1 0b 1111 1111 1000 0000 0000 0000 0000 0000 = 0xFF800000 = −0.5 0b 1111 1111 1110 0110 0110 0110 0110 0110 = 0xFFE66666 = −0.1 0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xFFFFFFFF = −0.00000005 (1 LSB below 0.0) 0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0.0 0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 0.00000005 (1 LSB above 0.0) 0b 0000 0000 0001 1001 1001 1001 1001 1001 = 0x00199999 = 0.1 0b 0000 0000 0100 0000 0000 0000 0000 0000 = 0x00400000 = 0.25 0b 0000 0000 1000 0000 0000 0000 0000 0000 = 0x00800000 = 0.5 0b 0000 0001 0000 0000 0000 0000 0000 0000 = 0x01000000 = 1.0 0b 0000 0010 0000 0000 0000 0000 0000 0000 = 0x02000000 = 2.0 0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7FFFFFFF = 127.99999994 (1 LSB below 128.0)

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 83 of 202 Numerical Format: 32.0 The 32.0 format is used for logic signals in the DSP program flow that are integers. The linear range is −2,147,483,648 to +2,147,483,647. The dynamic range (ratio of the largest possible signal level to the smallest possible nonzero signal level) is 192 dB. The following are examples of this numerical format: 0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = −2147483648 0b 1000 0000 0000 0000 0000 0000 0000 0001 = 0x80000001 = −2147483647 0b 1000 0000 0000 0000 0000 0000 0000 0010 = 0x80000002 = −2147483646 0b 1100 0000 0000 0000 0000 0000 0000 0000 = 0xC0000000 = −1073741824 0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xE0000000 = −536870912 0b 1111 1111 1111 1111 1111 1111 1111 1100 = 0xFFFFFFFC = −4 0b 1111 1111 1111 1111 1111 1111 1111 1110 = 0xFFFFFFFE = −2 0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xFFFFFFFF = −1 0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0 0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 1 0b 0000 0000 0000 0000 0000 0000 0000 0010 = 0x00000002 = 2 0b 0000 0000 0000 0000 0000 0000 0000 0011 = 0x00000003 = 3 0b 0000 0000 0000 0000 0000 0000 0000 0100 = 0x00000004 = 4 0b 0111 1111 1111 1111 1111 1111 1111 1110 = 0x7FFFFFFE = 2147483646 0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7FFFFFFF = 2147483647

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 84 of 202 Hardware Accelerators The core includes accelerators like division, square root, barrel shifters, Base 2 logarithm, Base 2 exponential, slew, and a pseudorandom number generator. These hardware accelerators reduce the number of instructions required for complex audio processing algorithms. The division accelerator enables efficient processing for audio algorithms like compression and limiting. The square root accelerator enables efficient processing for audio algorithms such as loudness, rms envelopes, and filter coefficient calculations. The logarithm and exponent accelerators enable efficient processing for audio algorithms involving decibel conversion. The slew accelerators provide click free updates of parameters that must change slowly over time, allowing audio processing algorithms such as mixers, crossfaders, dynamic filters, and dynamic volume controls. The pseudorandom number generator can efficiently produce white noise, pink noise, and dither. Programming the SigmaDSP Core The SigmaDSP is programmable via the SigmaStudio graphical development tools. When the SigmaDSP core is running a program and the user needs to reprogram the program and data memories during operation of the device, the core must be stopped while the memory is being updated to avoid undesired noises on the DSP outputs. The following sequence of steps is appropriate for programming the memories at boot time, or reprogramming the memories during operation: 1. Enable soft reset (Register 0xF890 (SOFT_RESET), Bit 0 (SOFT_RESET) = 0b0), then disable soft reset (Register 0xF890 (SOFT_RESET), Bit 0 (SOFT_RESET) = 0b1). 2. If the DSP is in the process of executing a program, wait for the current sample or block to finish processing. For programs with no block processing elements in the signal flow, use the length of one sample. For example, at a sample rate of 48 kHz, one sample is 1/48000 sec, or 20.83 μs. For programs with block processing elements in the signal flow, use the length of one block. For example, at a sample rate of 48 kHz, with a block size of 256 samples, one block is 256/48,000 sec, or 53.3 ms. 3. After waiting the appropriate amount of time, as defined in the previous step, download the new program and data memory contents to the corresponding memory locations using the I 2C/SPI slave control port. 4. Start the DSP core (Register 0xF402 (START_CORE), Bit 0 (START_CORE) = 0b1). 5. Wait at least two audio samples for the DSP initialization to execute. For example, at a sample rate of 48 kHz, two samples are equal to 2/48,000 sec, or 41.66 μs.

memories and generates alerts if error conditions are encountered. memory, stack, software program, and core op codes. preprogrammed action, if necessary. Table 52. For a more detailed description, see the DSP Core Table 52. DSP Core and Reliability Registers

parameters match the defaults shown in Table 53. Table 53. Software Safeload Memory Address Defaults increments automatically for each data-word. when it is written, a safeload write is triggered on the next frame. must be zero. The second write triggers the safeload operation. delay corrupts the downloaded data. definitions in an excerpt from the compiler_output.log file.

1. Confirm that no safeload operation has been executed in

the span of the last audio sample.

1. Write the desired data to the data_SafeLoad, Bit x
2. Write the desired starting target address to the
3. Write the number of words to be transferred to the

one word, and the maximum write length is five words.

1. Wait one audio frame for the safeload operation to complete.

Figure 81. Compiler Log Output Excerpt with SafeLoad Module Definitions well as the registers related to the panic manager. function. For more details, see the Soft Reset Register section. Table 54. Soft Reset Register good mixed-signal PCB design practices. description, see the Hardware Interfacing Registers section.

Table 55. Pin Drive Strength, Slew Rate, and Pull Configuration Registers

divided into two main parts: memory and registers. (16 kWords storing 32-bit data). The ADAU1462/ADAU1466 have 8 kWords of program memory. parity errors when they are detected. cannot be accidentally overwritten or corrupted at run time. The DSP core is able to access directly all memory and registers. compiler, and they require no action on the part of the user. increases the efficiency of audio processing algorithm development. constants, such as pi and factors of 2, and complex constants. memory spaces for the ADAU1462 are defined in Table 57. Table 56. ADAU1466 Memory Map Table 57. ADAU1462 Memory Map

Figure 82. ADAU1462 Slave Port Memory Map and the Mapping onto the SigmaDSP Core Memory

Figure 83. ADAU1466 Slave Port Memory Map and the Mapping onto the SigmaDSP Core Memory

All control registers store 16 bits (two bytes) of data. The register map is defined in Table 58. Table 58. Control Register Summary

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 93 of 202 Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0xF380 ... 0xF3BF FTDM_OUTx [15:8] RESERVED 0x0000 RW [7:0] SLOT_ ENABLE_OUT REVERSE_ OUT_BYTE SERIAL_ OUT_SEL CHANNEL_OUT_POS BYTE_OUT_POS 0xF400 HIBERNATE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] HIBERNATE 0xF401 START_PULSE [15:8] RESERVED[10:3] 0x0002 RW [7:0] RESERVED[2:0] START_PULSE 0xF402 START_CORE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] START_CORE 0xF403 KILL_CORE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] KILL_CORE 0xF404 START_ADDRESS [15:8] START_ADDRESS[15:8] 0x0000 RW [7:0] START_ADDRESS[7:0] 0xF405 CORE_STATUS [15:8] RESERVED[12:5] 0x0000 R [7:0] RESERVED[4:0] CORE_STATUS 0xF420 DEBUG_MODE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] DEBUG_MODE 0xF421 PANIC_CLEAR [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PANIC_CLEAR 0xF422 PANIC_PARITY_MASK [15:8] RESERVED DM1_BANK3_ MASK DM1_BANK2_ MASK DM1_BANK1_ MASK DM1_BANK0_ MASK 0x0003 RW [7:0] DM0_BANK3_ MASK DM0_BANK2_ MASK DM0_BANK1_ MASK DM0_BANK0_ MASK PM1_MASK PM0_MASK ASRC1_MASK ASRC0_MASK 0xF423 PANIC_SOFTWARE_ MASK [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PANIC_ SOFTWARE 0xF424 PANIC_WD_MASK [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PANIC_WD 0xF425 PANIC_STACK_MASK [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PANIC_STACK 0xF426 PANIC_LOOP_MASK [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PANIC_LOOP 0xF427 PANIC_FLAG [15:8] RESERVED[14:7] 0x0000 R [7:0] RESERVED[6:0] PANIC_FLAG 0xF428 PANIC_CODE [15:8] ERR_SOFT ERR_LOOP ERR_STACK ERR_ WATCHDOG ERR_DM1B3 ERR_DM1B2 ERR_DM1B1 ERR_DM1B0 0x0000 R [7:0] ERR_DM0B3 ERR_DM0B2 ERR_DM0B1 ERR_DM 0B0 ERR_PM1 ERR_PM0 ERR_ASRC1 ERR_ASRC0 0xF429 DECODE_OP0 [15:8] DECODE_OP0[15:8] 0x0000 R [7:0] DECODE_OP0[7:0] 0xF42A DECODE_OP1 [15:8] DECODE_OP1[15:8] 0x0000 R [7:0] DECODE_OP1[7:0] 0xF42B DECODE_OP2 [15:8] DECODE_OP2[15:8] 0x0000 R [7:0] DECODE_OP2[7:0] 0xF42C DECODE_OP3 [15:8] DECODE_OP3[15:8] 0x0000 R [7:0] DECODE_OP3[7:0] 0xF42D EXECUTE_OP0 [15:8] DECODE_EX0[15:8] 0x0000 R [7:0] DECODE_EX0[7:0] 0xF42E EXECUTE_OP1 [15:8] DECODE_EX1[15:8] 0x0000 R [7:0] DECODE_EX1[7:0] 0xF42F EXECUTE_OP2 [15:8] DECODE_EX2[15:8] 0x0000 R [7:0] DECODE_EX2[7:0] 0xF430 EXECUTE_OP3 [15:8] DECODE_EX3[15:8] 0x0000 R [7:0] DECODE_EX3[7:0] 0xF431 DECODE_COUNT [15:8] DECODE_COUNT[15:8] 0x0000 R [7:0] DECODE_COUNT[7:0] 0xF432 EXECUTE_COUNT [15:8] EXECUTE_COUNT[15:8] 0x0000 R [7:0] EXECUTE_COUNT[7:0] 0xF433 SOFTWARE_VALUE_0 [15:8] SOFTWARE_VALUE_0[15:8] 0x0000 R [7:0] SOFTWARE_VALUE_0[7:0] 0xF434 SOFTWARE_VALUE_1 [15:8] SOFTWARE_VALUE_1[15:8] 0x0000 R [7:0] SOFTWARE_VALUE_1[7:0] 0xF443 WATCHDOG_ MAXCOUNT [15:8] RESERVED WD_MAXCOUNT[12:8] 0x0000 RW [7:0] WD_MAXCOUNT[7:0]

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 94 of 202 Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0xF444 WATCHDOG_ PRESCALE [15:8] RESERVED[11:4] 0x0000 RW [7:0] RESERVED[3:0] WD_PRESCALE 0xF450 BLOCKINT_EN [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] BLOCKINT_EN 0xF451 BLOCKINT_VALUE [15:8] BLOCKINT_VALUE[15:8] 0x0000 RW [7:0] BLOCKINT_VALUE[7:0] 0xF460 PROG_CNTR0 [15:8] RESERVED 0x0000 R [7:0] PROG_CNTR_MSB 0xF461 PROG_CNTR1 [15:8] PROG_CNTR_LSB[15:8] 0x0000 R [7:0] PROG_CNTR_LSB[7:0] 0xF462 PROG_CNTR_CLEAR [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PROG_CNTR_ CLEAR 0xF463 PROG_CNTR_LENGTH0 [15:8] RESERVED 0x0000 R [7:0] PROG_LENGTH_MSB 0xF464 PROG_CNTR_LENGTH1 [15:8] PROG_LENGTH_LSB[15:8] 0x0000 R [7:0] PROG_LENGTH_LSB[7:0] 0xF465 PROG_CNTR_ MAXLENGTH0 [15:8] RESERVED 0x0000 R [7:0] PROG_MAXLENGTH_MSB 0xF466 PROG_CNTR_ MAXLENGTH1 [15:8] PROG_MAXLENGTH_LSB[15:8] 0x0000 R [7:0] PROG_MAXLENGTH_LSB[7:0] 0xF467 PANIC_PARITY_MASK1 [15:8] RESERVED DM0_BANK1_ SUBBANK4_ MASK DM0_BANK1_ SUBBANK3_ MASK DM0_BANK1_ SUBBANK2_ MASK DM0_BANK1_ SUBBANK1_ MASK DM0_BANK1_ SUBBANK0_ MASK 0x0000 RW [7:0] RESERVED DM0_BANK0_ SUBBANK4_ MASK DM0_BANK0_ SUBBANK3_ MASK DM0_BANK0_ SUBBANK2_ MASK DM0_BANK0_ SUBBANK1_ MASK DM0_BANK0_ SUBBANK0_ MASK 0xF468 PANIC_PARITY_MASK2 [15:8] RESERVED DM0_BANK3_ SUBBANK4_ MASK DM0_BANK3_ SUBBANK3_ MASK DM0_BANK3_ SUBBANK2_ MASK DM0_BANK3_ SUBBANK1_ MASK DM0_BANK3_ SUBBANK0_ MASK 0x0000 RW [7:0] RESERVED DM0_BANK2_ SUBBANK4_ MASK DM0_BANK2_ SUBBANK3_ MASK DM0_BANK2_ SUBBANK2_ MASK DM0_BANK2_ SUBBANK1_ MASK DM0_BANK2_ SUBBANK0_ MASK 0xF469 PANIC_PARITY_MASK3 [15:8] RESERVED DM1_BANK1_ SUBBANK4_ MASK DM1_BANK1_ SUBBANK3_ MASK DM1_BANK1_ SUBBANK2_ MASK DM1_BANK1_ SUBBANK1_ MASK DM1_BANK1_ SUBBANK0_ MASK 0x0000 RW [7:0] RESERVED DM1_BANK0_ SUBBANK4_ MASK DM1_BANK0_ SUBBANK3_ MASK DM1_BANK0_ SUBBANK2_ MASK DM1_BANK0_ SUBBANK1_ MASK DM1_BANK0_ SUBBANK0_ MASK 0xF46A PANIC_PARITY_MASK4 [15:8] RESERVED DM1_BANK3_ SUBBANK4_ MASK DM1_BANK3_ SUBBANK3_ MASK DM1_BANK3_ SUBBANK2_ MASK DM1_BANK3_ SUBBANK1_ MASK DM1_BANK3_ SUBBANK0_ MASK 0x0000 RW [7:0] RESERVED DM1_BANK2_ SUBBANK4_ MASK DM1_BANK2_ SUBBANK3_ MASK DM1_BANK2_ SUBBANK2_ MASK DM1_BANK2_ SUBBANK1_ MASK DM1_BANK2_ SUBBANK0_ MASK 0xF46B PANIC_PARITY_MASK5 [15:8] RESERVED PM_BANK1_ SUBBANK5_ MASK PM_BANK1_ SUBBANK4_ MASK PM_BANK1_ SUBBANK3_ MASK PM_BANK1_ SUBBANK2_ MASK PM_BANK1_ SUBBANK1_ MASK PM_BANK1_ SUBBANK0_ MASK 0x0000 RW [7:0] RESERVED PM_BANK0_ SUBBANK5_ MASK PM_BANK0_SUB BANK4_MASK PM_BANK0_ SUBBANK3_ MASK PM_BANK0_ SUBBANK2_ MASK PM_BANK0_ SUBBANK1_ MASK PM_BANK0_ SUBBANK0_ MASK 0xF46C PANIC_CODE1 [15:8] RESERVED ERR_ DM0B1SB4 ERR_ DM0B1SB3 ERR_ DM0B1SB2 ERR_ DM0B1SB1 ERR_ DM0B1SB0 0x0000 R [7:0] RESERVED ERR_ DM0B0SB4 ERR_ DM0B0SB3 ERR_ DM0B0SB2 ERR_ DM0B0SB1 ERR_ DM0B0SB0 0xF46D PANIC_CODE2 [15:8] RESERVED ERR_ DM0B3SB4 ERR_ DM0B3SB3 ERR_ DM0B3SB2 ERR_ DM0B3SB1 ERR_ DM0B3SB0 0x0000 R [7:0] RESERVED ERR_ DM0B2SB4 ERR_ DM0B2SB3 ERR_ DM0B2SB2 ERR_ DM0B2SB1 ERR_ DM0B2SB0 0xF46E PANIC_CODE3 [15:8] RESERVED ERR_ DM1B1SB4 ERR_ DM1B1SB3 ERR_ DM1B1SB2 ERR_ DM1B1SB1 ERR_ DM1B1SB0 0x0000 R [7:0] RESERVED ERR_ DM1B0SB4 ERR_ DM1B0SB3 ERR_ DM1B0SB2 ERR_ DM1B0SB1 ERR_ DM1B0SB0 0xF46F PANIC_CODE4 [15:8] RESERVED ERR_ DM1B3SB4 ERR_ DM1B3SB3 ERR_ DM1B3SB2 ERR_ DM1B3SB1 ERR_ DM1B3SB0 0x0000 R [7:0] RESERVED ERR_ DM1B2SB4 ERR_ DM1B2SB3 ERR_ DM1B2SB2 ERR_ DM1B2SB1 ERR_ DM1B2SB0 0xF470 PANIC_CODE5 [15:8] RESERVED ERR_PM_ B1SB5 ERR_PM_ B1SB4 ERR_PM_ B1SB3 ERR_PM_ B1SB2 ERR_PM_ B1SB1 ERR_PM_ B1SB0 0x0000 R [7:0] RESERVED ERR_PM_ B0SB5 ERR_PM_ B0SB4 ERR_PM_ B0SB3 ERR_PM_ B0SB2 ERR_PM_ B0SB1 ERR_PM_ B0SB0

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 95 of 202 Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0xF510 ... 0xF51D MPx_MODE [15:8] RESERVED SS_SELECT 0x0000 RW [7:0] DEBOUNCE_VALUE MP_MODE MP_ENABLE 0xF520 ... 0xF52D MPx_WRITE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] MP_REG_WRITE 0xF530 ... 0xF53D MPx_READ [15:8] RESERVED[14:7] 0x0000 R [7:0] RESERVED[6:0] MP_REG_READ 0xF560 ... 0xF561 DMIC_CTRLn [15:8] RESERVED CUTOFF MIC_DATA_SRC 0x4000 RW [7:0] RESERVED DMIC_CLK HPF DMPOL DMSW DMIC_EN 0xF580 ASRC_LOCK [15:8] RESERVED 0x0000 R [7:0] ASRC7L ASRC6L ASRC5L ASRC4L ASRC3L ASRC2L ASRC1L ASRC0L 0xF581 ASRC_MUTE [15:8] RESERVED LOCKMUTE ASRC_RAMP1 ASRC_RAMP0 0x0000 RW [7:0] ASRC7M ASRC6M ASRC5M ASRC4M ASRC3M ASRC2M ASRC1M ASRC0M 0xF582 ... 0xF589 ASRCx_RATIO [15:8] ASRC_RATIO[15:8] 0x0000 R [7:0] ASRC_RATIO[7:0] 0xF590 ASRC_RAMPMAX_OVR [15:8] ASRC_RAMPMAX_OVR[15:12] OVERRIDE OVR_RAMPMAX_VALUE[10:8] 0x07FF RW [7:0] OVR_RAMPMAX_VALUE[7:0] 0xF591 ... 0xF598 ASRCx_RAMPMAX [15:8] ASRCx_RAMPMAX[15:11] RAMPMAX_VALUE[10:8] 0x07FF RW [7:0] RAMPMAX_VALUE[7:0] 0xF5A0 ... 0xF5A5 ADC_READx [15:8] ADC_VALUE[15:8] 0x0000 R [7:0] ADC_VALUE[7:0] 0xF600 SPDIF_LOCK_DET [15:8] RESERVED[14:7] 0x0000 R [7:0] RESERVED[6:0] LOCK 0xF601 SPDIF_RX_CTRL [15:8] RESERVED[11:4] 0x0000 RW [7:0] RESERVED[3:0] FASTLOCK FSOUTSTRENG TH RX_LENGTHCTRL 0xF602 SPDIF_RX_DECODE [15:8] RESERVED RX_WORDLENGTH_R[3:2] 0x0000 R [7:0] RX_WORDLENGTH_R[1:0] RX_WORDLENGTH_L COMPR_TYPE AUDIO_TYPE 0xF603 SPDIF_RX_ COMPRMODE [15:8] COMPR_MODE[15:8] 0x0000 R [7:0] COMPR_MODE[7:0] 0xF604 SPDIF_RESTART [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] RESTART_AUDIO 0xF605 SPDIF_LOSS_OF_LOCK [15:8] RESERVED[14:7] 0x0000 R [7:0] RESERVED[6:0] LOSS_OF_LOCK 0xF606 SPDIF_RX_MCLKSPEED [15:8] RESERVED[14:7] 0x0001 RW [7:0] RESERVED[6:0] RX_MCLKSPEED 0xF607 SPDIF_TX_MCLKSPEED [15:8] RESERVED[14:7] 0x0001 RW [7:0] RESERVED[6:0] TX_MCLKSPEED 0xF608 SPDIF_AUX_EN [15:8] RESERVED[10:3] 0x0000 RW [7:0] RESERVED[2:0] TDMOUT_CLK TDMOUT 0xF60F SPDIF_RX_AUXBIT_ READY [15:8] RESERVED[14:7] 0x0000 R [7:0] RESERVED[6:0] AUXBITS_READY 0xF610 ... 0xF61B SPDIF_RX_CS_LEFT_x [15:8] SPDIF_RX_CS_LEFT[15:8] 0x0000 R [7:0] SPDIF_RX_CS_LEFT[7:0] 0xF620 ... 0xF62B SPDIF_RX_CS_RIGHT_x [15:8] SPDIF_RX_CS_RIGHT[15:8] 0x0000 R [7:0] SPDIF_RX_CS_RIGHT[7:0] 0xF630 ... 0xF63B SPDIF_RX_UD_LEFT_x [15:8] SPDIF_RX_UD_LEFT[15:8] 0x0000 R [7:0] SPDIF_RX_UD_LEFT[7:0] 0xF640 ... 0xF64B SPDIF_RX_UD_RIGHT_x [15:8] SPDIF_RX_UD_RIGHT[15:8] 0x0000 R [7:0] SPDIF_RX_UD_RIGHT[7:0] 0xF650 ... 0xF65B SPDIF_RX_VB_LEFT_x [15:8] SPDIF_RX_VB_LEFT[15:8] 0x0000 R [7:0] SPDIF_RX_VB_LEFT[7:0] 0xF660 ... 0xF66B SPDIF_RX_VB_RIGHT_x [15:8] SPDIF_RX_VB_RIGHT[15:8] 0x0000 R [7:0] SPDIF_RX_VB_RIGHT[7:0] 0xF670 ... 0xF67B SPDIF_RX_PB_LEFT_x [15:8] SPDIF_RX_PB_LEFT[15:8] 0x0000 R [7:0] SPDIF_RX_PB_LEFT[7:0]

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 96 of 202 Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0xF680 ... 0xF68B SPDIF_RX_PB_RIGHT_x [15:8] SPDIF_RX_PB_RIGHT[15:8] 0x0000 R [7:0] SPDIF_RX_PB_RIGHT[7:0] 0xF690 SPDIF_TX_EN [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] TXEN 0xF691 SPDIF_TX_CTRL [15:8] RESERVED[13:6] 0x0000 RW [7:0] RESERVED[5:0] TX_ LENGTHCTRL 0xF69F SPDIF_TX_AUXBIT_SOU RCE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] TX_AUXBITS_ SOURCE 0xF6A0 ... 0xF6AB SPDIF_TX_CS_LEFT_x [15:8] SPDI F_TX_CS_LEFT[15:8] 0x0000 RW [7:0] SPDIF_TX_CS_LEFT[7:0] 0xF6B0 ... 0xF6BB SPDIF_TX_CS_RIGHT_x [15:8] SPDIF_TX_CS_RIGHT[15:8] 0x0000 RW [7:0] SPDIF_TX_CS_RIGHT[7:0] 0xF6C0 ... 0xF6CB SPDIF_TX_UD_LEFT_x [15:8] SPDI F_TX_UD_LEFT[15:8] 0x0000 RW [7:0] SPDIF_TX_UD_LEFT[7:0] 0xF6D0 ... 0xF6DB SPDIF_TX_UD_RIGHT_x [15:8] SPDIF_TX_UD_RIGHT[15:8] 0x0000 RW [7:0] SPDIF_TX_UD_RIGHT[7:0] 0xF6E0 ... 0xF6EB SPDIF_TX_VB_LEFT_x [15:8] SPDI F_TX_VB_LEFT[15:8] 0x0000 RW [7:0] SPDIF_TX_VB_LEFT[7:0] 0xF6F0 ... 0xF6FB SPDIF_TX_VB_RIGHT_x [15:8] SPDIF_TX_VB_RIGHT[15:8] 0x0000 RW [7:0] SPDIF_TX_VB_RIGHT[7:0] 0xF700 ... 0xF70B SPDIF_TX_PB_LEFT_x [15:8] SPDIF_TX_PB_LEFT[15:8] 0x0000 RW [7:0] SPDIF_TX_PB_LEFT[7:0] 0xF710 ... 0xF71B SPDIF_TX_PB_RIGHT_x [15:8] SPDIF_TX_PB_RIGHT[15:8] 0x0000 RW [7:0] SPDIF_TX_PB_RIGHT[7:0] 0xF780 ... 0xF783 BCLK_INx_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] BCLK_IN_PULL BCLK_IN_SLEW BCLK_IN_DRIVE 0xF784 ... 0xF787 BCLK_OUTx_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] BCLK_OUT_ PULL BCLK_OUT_SLEW BCLK_OUT_DRIVE 0xF788 ... 0xF78B LRCLK_INx_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] LRCLK_IN_PULL LRCLK_IN_SLEW LRCLK_IN_DRIVE 0xF78C ... 0xF78F LRCLK_OUTx_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] LRCLK_OUT_ PULL LRCLK_OUT_SLEW LRCLK_OUT_DRIVE 0xF790 ... 0xF793 SDATA_INx_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] SDATA_IN_PULL SDATA_IN_SLEW SDATA_IN_DRIVE 0xF794 ... 0xF797 SDATA_OUTx_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] SDATA_OUT_ PULL SDATA_OUT_SLEW SDATA_OUT_DRIVE 0xF798 SPDIF_TX_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] SPDIF_TX_PULL SPDIF_TX_SLEW SPDIF_TX_DRIVE 0xF799 SCLK_SCL_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] SCLK_SCL_PULL SCLK_SCL_SLEW SCLK_SCL_DRIVE 0xF79A MISO_SDA_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] MISO_SDA_ PULL MISO_SDA_SLEW MISO_SDA_DRIVE 0xF79B SS_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] SS_PULL SS_SLEW SS_DRIVE 0xF79C MOSI_ADDR1_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] MOSI_ADDR1_ PULL MOSI_ADDR1_SLEW MOSI_ADDR1_DRIVE 0xF79D SCLK_SCL_M_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] SCLK_SCL_M_ PULL SCLK_SCL_M_SLEW SCLK_SCL_M_DRIVE

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 97 of 202 Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0xF79E MISO_SDA_M_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] MISO_SDA_M_ PULL MISO_SDA_M_SLEW MISO_SDA_M_DRIVE 0xF79F SS_M_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] SS_M_PULL SS_M_SLEW SS_M_DRIVE 0xF7A0 MOSI_M_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] MOSI_M_PULL MOSI_M_SLEW MOSI_M_DRIVE 0xF7A1 MP6_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] MP6_PULL MP6_SLEW MP6_DRIVE 0xF7A2 MP7_PIN [15:8] RESERVED[10:3] 0x0018 RW [7:0] RESERVED[2:0] MP7_PULL MP7_SLEW MP7_DRIVE 0xF7A3 CLKOUT_PIN [15:8] RESERVED[10:3] 0x0008 RW [7:0] RESERVED[2:0] CLKOUT_PULL CLKOUT_SLEW CLKOUT_DRIVE 0xF899 SECONDPAGE_ENABLE [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] PAGE 0xF890 SOFT_RESET [15:8] RESERVED[14:7] 0x0000 RW [7:0] RESERVED[6:0] SOFT_RESET

does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1. Table 59. Bit Descriptions for PLL_CTRL0 format. For example, the default feedback divider value of 96 is stored as 0x60. (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1. Table 60. Bit Descriptions for PLL_CTRL1 make the input to the PLL as close to 3.072 MHz as possible.

00 Divide by 1

01 Divide by 2

10 Divide by 4

11 Divide by 8

written to this register does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1. Table 61. Bit Descriptions for PLL_CLK_SRC nominal operating frequency of the core and the clock generator inputs.

0 Direct from XTALIN/MCLK pin

1 PLL clock

(PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), and Register 0xF005 (MCLK_OUT) are activated. Table 62. Bit Descriptions for PLL_ENABLE

0 PLL disabled

1 PLL enabled

Table 63. Bit Descriptions for PLL_LOCK

0 PLL unlocked

1 PLL locked

Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE), changes state from 0b0 to 0b1. Table 64. Bit Descriptions for MCLK_OUT [2:1] CLKOUT_RATE Frequency of CLKOUT. Frequency of the signal output from the CLKOUT pin. CLKOUT pin of the device. When disabled, the CLKOUT pin is high impedance.

0 CLKOUT pin disabled

1 CLKOUT pin enabled

requires no interaction on the part of the user. Ensure that the PLL watchdog is enabled at all times. Table 65. Bit Descriptions for PLL_WATCHDOG

0 PLL watchdog disabled

1 PLL watchdog enabled

This register contains the denominator (M) for Clock Generator 1. Table 66. Bit Descriptions for CLK_GEN1_M This register contains the numerator (N) for Clock Generator 1. Table 67. Bit Descriptions for CLK_GEN1_N This register contains the denominator (M) for Clock Generator 2. Table 68. Bit Descriptions for CLK_GEN2_M

This register contains the numerator (N) for Clock Generator 2. Table 69. Bit Descriptions for CLK_GEN2_N This register contains the denominator (M) for Clock Generator 3. Table 70. Bit Descriptions for CLK_GEN3_M This register contains the numerator (N) for Clock Generator 3. Table 71. Bit Descriptions for CLK_GEN3_N

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 105 of 202 Input Reference for Clock Generator 3 Register Address: 0xF026, Reset: 0x000E, Name: CLK_GEN3_SRC Clock Generator 3 can generate audio clocks using the PLL output (system clock) as a reference, or it can optionally use a reference clock entering the device from an external source either on a multipurpose pin (MPx) or the S/PDIF receiver. This register determines the source of the reference signal.

Table 72. Bit Descriptions for CLK_GEN3_SRC the source pin. Otherwise, the PLL output is used as the reference clock.

1. For example: if Bit 4 (CLK_GEN3_SRC) = 0b1 (an external reference

base output sample rate of Clock Generator 3 is 48 kHz × 2048/1024 = 96 kHz.

0 Reference signal provided by PLL output; multiply the frequency of that

signal by N and divide it by M.

1 Reference signal provided by the signal input to the hardware pin defined

then divide by 1024) to get the resulting sample rate. M is ignored. wave clock representing the reference sample rate.

0000 Input reference source is SS_M/MP0

0001 Input reference source is MOSI_M/MP1

0010 Input reference source is SCL_M/SCLK_M/MP2

0011 Input reference source is SDA_M/MISO_M/MP3

0100 Input reference source is LRCLK_OUT0/MP4

0101 Input reference source is LRCLK_OUT1/MP5

0110 Input reference source is MP6

0111 Input reference source is MP7

1000 Input reference source is LRCLK_OUT2/MP8

1001 Input reference source is LRCLK_OUT3/MP9

1010 Input reference source is LRCLK_IN0/MP10

1011 Input reference source is LRCLK_IN1/MP11

1100 Input reference source is LRCLK_IN2/MP12

1101 Input reference source is LRCLK_IN3/MP13

1110 Input reference source is S/PDIF receiver (recovered frame clock)

the PLL output or from an external reference signal, which is configured in Register 0xF026, Bit 4 (CLK_GEN3_SRC). Table 73. Bit Descriptions for CLK_GEN3_LOCK

0 Not locked

1 Locked

these functional blocks are disabled, the current draw on the corresponding supply pins decreases. Table 74. Bit Descriptions for POWER_ENABLE0 function while this bit is disabled.

0 Power disabled

1 Power enabled

ceases to function while this bit is disabled.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 109 of 202 Bits Bit Name Settings Description Reset Access 10 CLK_GEN1_PWR Clock Generator 1 power enable. When this bit is disabled, Clock Generator 1 is disabled and ceases to output audio clocks. Any LRCLK_OUTx, LRCLK_INx or BCLK_OUTx, BCLK_INx pins that are configured to output clocks generated by Clock Generator 1 output a logic low signal while Clock Generator 1 is disabled. Any functional block in hardware, including the DSP core, that is configured to be clocked by Clock Generator 1 ceases to function when this bit is disabled. 0x0 RW 9 ASRCBANK1_PWR ASRC 4, ASRC 5, ASRC 6, ASRC 7 power enable. When this bit is disabled, ASRC Channel 8 to Channel 15 are disabled, and their output data streams cease. 0x0 RW 8 ASRCBANK0_PWR ASRC 0, ASRC 1, ASRC 2, ASRC 3 power enable. When this bit is disabled, ASRC Channel 0 to Channel 7 are disabled, and their output data streams cease. 0x0 RW 7 SOUT3_PWR SDATA_OUT3 power enable. When this bit is disabled, the SDATA_OUT3 pin and associated serial port circuitry are also disabled. LRCLK_OUT3 and BCLK_OUT3 are not affected. 0x0 RW 6 SOUT2_PWR SDATA_OUT2 power enable. When this bit is disabled, the SDATA_OUT2 pin and associated serial port circuitry is disabled. LRCLK_OUT2 and BCLK_OUT2 are not affected. 0x0 RW 5 SOUT1_PWR SDATA_OUT1 power enable. When this bit is disabled, the SDATA_OUT1 pin and associated serial port circuitry are also disabled. LRCLK_OUT1 and BCLK_OUT1 are not affected. 0x0 RW 4 SOUT0_PWR SDATA_OUT0 power enable. When this bit is disabled, the SDATA_OUT0 pin and associated serial port circuitry are disabled. LRCLK_OUT0 and BCLK_OUT0 are not affected. 0x0 RW 3 SIN3_PWR SDATA_IN3 power enable. When this bit is disabled, the SDATA_IN3 pin and associated serial port circuitry are disabled. LRCLK_IN3 and BCLK_IN3 are not affected. 0x0 RW 2 SIN2_PWR SDATA_IN2 power enable. When this bit is disabled, the SDATA_IN2 pin and associated serial port circuitry are disabled. LRCLK_IN2 and BCLK_IN2 are not affected. 0x0 RW 1 SIN1_PWR SDATA_IN1 power enable. When this bit is disabled, the SDATA_IN1 pin and associated serial port circuitry are disabled. The LRCLK_IN1 and BCLK_IN1 pins are not affected. 0x0 RW 0 SIN0_PWR SDATA_IN0 power enable. When this bit is disabled, the SDATA_IN0 pin and associated serial port circuitry are disabled. The LRCLK_IN0 and BCLK_IN0 pins are not affected. 0x0 RW

when not in use. When these functional blocks are disabled, the current draw on the corresponding supply pins decreases. Table 75. Bit Descriptions for POWER_ENABLE1 4 PDM1_PWR PDM Microphone Channel 2 and PDM Microphone Channel 3 power enable. 3 PDM0_PWR PDM Microphone Channel 0 and PDM Microphone Channel 1 power enable. and the output is held at logic low as long as this bit is disabled. 1 RX_PWR S/PDIF receiver power enable. This bit disables the S/PDIF receiver circuit. powered down, their outputs cease to update, and they hold their last value.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 111 of 202 AUDIO SIGNAL ROUTING REGISTERS ASRC Input Selector Register Address: 0xF100 to Address 0xF107 (Increments of 0x1), Reset: 0x0000, Name: ASRC_INPUTx These eight registers configure the input signal to the corresponding eight stereo ASRCs on the ADAU1466 and ADAU1462. ASRC_INPUT0 configures ASRC Channel 0 and ASRC Channel 1, ASRC_INPUT1 configures ASRC Channel 2 and ASRC Channel 3, and so on. Valid input signals to the ASRCs include Serial Input Channel 0 to Serial Input Channel 47, the PDM Microphone Input Channel 0 to PDM Microphone Input Channel 3, and the S/PDIF Receiver Channel 0 to S/PDIF Receiver Channel 1.

Table 76. Bit Descriptions for ASRC_INPUTx channel is routed to the ASRC.

00000 Serial Input Channel 0 and Serial Input Channel 1

00001 Serial Input Channel 2 and Serial Input Channel 3

00010 Serial Input Channel 4 and Serial Input Channel 5

00011 Serial Input Channel 6 and Serial Input Channel 7

00100 Serial Input Channel 8 and Serial Input Channel 9

00101 Serial Input Channel 10 and Serial Input Channel 11

00110 Serial Input Channel 12 and Serial Input Channel 13

00111 Serial Input Channel 14 and Serial Input Channel 15

01000 Serial Input Channel 16 and Serial Input Channel 17

01001 Serial Input Channel 18 and Serial Input Channel 19

01010 Serial Input Channel 20 and Serial Input Channel 21

01011 Serial Input Channel 22 and Serial Input Channel 23

01100 Serial Input Channel 24 and Serial Input Channel 25

01101 Serial Input Channel 26 and Serial Input Channel 27

01110 Serial Input Channel 28 and Serial Input Channel 29

01111 Serial Input Channel 30 and Serial Input Channel 31

10000 Serial Input Channel 32 and Serial Input Channel 33

10001 Serial Input Channel 34 and Serial Input Channel 35

10010 Serial Input Channel 36 and Serial Input Channel 37

10011 Serial Input Channel 38 and Serial Input Channel 39

10100 Serial Input Channel 40 and Serial Input Channel 41

10101 Serial Input Channel 42 and Serial Input Channel 43

10110 Serial Input Channel 44 and Serial Input Channel 45

10111 Serial Input Channel 46 and Serial Input Channel 47

000 Not used

001 From serial input ports; select channels using Bits[7:3] (ASRC_SIN_CHANNEL)

010 From DSP core outputs

011 From S/PDIF receiver

100 From digital PDM Microphone Input Channel 0 and PDM Microphone Input

101 From digital PDM Microphone Input Channel 2 and PDM Microphone Input

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 113 of 202 ASRC Output Rate Selector Register Address: 0xF140 to Address 0xF147 (Increments of 0x1), Reset: 0x0000, Name: ASRC_OUT_RATEx These eight registers configure the target output sample rates of the corresponding eight stereo ASRCs on the ADAU1466 and ADAU1462. The ASRC takes any arbitrary input sample rate and automatically attempts to resample the data in that signal and output it at the target sample rate as configured by these registers. Each of the eight registers corresponds to one of the eight stereo ASRCs. ASRC_OUT_RATE0 configures ASRC Channel 0 and ASRC Channel 1, ASRC_INPUT1 configures ASRC Channel 2 and ASRC Channel 3, ASRC_OUT_ RATE2 configures ASRC Channel 4 and ASRC Channel 5, ASRC_OUT_RATE3 configures ASRC Channel 6 and ASRC Channel 7, ASRC_OUT_RATE4 configures ASRC Channel 8 and ASRC Channel 9, ASRC_OUT_RATE5 configures ASRC Channel 10 and ASRC Channel 11, ASRC_OUT_RATE6 configures ASRC Channel 12 and ASRC Channel 13, and ASRC_OUT_RATE7 configures ASRC Channel 14 and ASRC Channel 15. The ASRCs lock their output frequencies to the audio sample rates of any of the serial output ports, the DSP start pulse rate of the core, or one of several internally generated sample rates coming from the clock generators.

Table 77. Bit Descriptions for ASRC_OUT_RATEx to a serial output port, the DSP core, or an internally generated rate.

0000 No output rate selected

0001 Use sample rate of SDATA_OUT0 (Register 0xF211 (SERIAL_BYTE_4_1), Bits[4:0])

0010 Use sample rate of SDATA_OUT1 (Register 0xF215 (SERIAL_BYTE_5_1), Bits[4:0])

0011 Use sample rate of SDATA_OUT2 (Register 0xF219 (SERIAL_BYTE_6_1), Bits[4:0])

0100 Use sample rate of SDATA_OUT3 (Register 0xF21D (SERIAL_BYTE_7_1), Bits[4:0])

0101 Use DSP core audio sampling rate (Register 0xF401 (START_PULSE), Bits[4:0])

0110 Internal rate (the base output rate of Clock Generator 1); see Register 0xF020

0111 Internal rate × 2 (the doubled output rate of Clock Generator 1); see Register 0xF020

1000 Internal rate × 4 (the quadrupled output rate of Clock Generator 1); see Register 0xF020

1001 Internal rate × (1/2) the halved output rate of Clock Generator 1); see Register 0xF020

1010 Internal rate × (1/3) (one-third output of Clock Generator 2); see Register 0xF022

1011 Internal rate × (1/4) (quartered output of Clock Generator 1); see Register 0xF020

1100 Internal rate × (1/6) (one-sixth output of Clock Generator 2); see Register 0xF022

These 24 registers correspond to the 24 pairs of output channels used by the serial output ports. Each register corresponds to two audio channels. SOUT_SOURCE0 corresponds to Channel 0 and Channel 1, SOUT_SOURCE1 corresponds to Channel 2 and Channel 3, and so on. SOUT_SOURCE0 to SOUT_SOURCE7 map to the 16 total channels (Channel 0 to Channel 15) that are fed to SDATA_OUT0. SOUT_SOURCE8 to SOUT_SOURCE15 map to the 16 total channels (Channel 16 to Channel 31) that are fed to SDATA_OUT1. SOUT_SOURCE16 to SOUT_SOURCE19 map to the eight total channels (Channel 32 to Channel 39) that are fed to SDATA_OUT2. SOUT_SOURCE20 to SOUT_SOURCE23 map to the eight total channels (Channel 40 to Channel 47) that are fed to SDATA_OUT3. corresponding audio output channels of the DSP core, from an ASRC output pair, or directly from the PDM microphone inputs. Table 78. Bit Descriptions for SOUT_SOURCEx select which ASRC channels are routed to the serial output channels.

000 ASRC 0 (Channel 0 and Channel 1)

001 ASRC 1 (Channel 2 and Channel 3)

010 ASRC 2 (Channel 4 and Channel 5)

011 ASRC 3 (Channel 6 and Channel 7)

100 ASRC 4 (Channel 8 and Channel 9)

101 ASRC 5 (Channel 10 and Channel 11)

110 ASRC 6 (Channel 12 and Channel 13)

111 ASRC 7 (Channel 14 and Channel 15)

000 Disabled; these output channels are not used

001 Direct copy of data from co rresponding serial input channels

010 Data from corresponding DSP core output channels

011 From ASRC (select channel usin g Bits[5:3], SOUT_ASRC_SELECT)

100 Digital PDM Microphone Input Channel 0 and Digital PDM Microphone

101 Digital PDM Microphone Input Channel 2 and Digital PDM Microphone

S/PDIF outputs of the DSP core or directly from the S/PDIF receiver. Table 79. Bit Descriptions for SPDIFTX_INPUT

00 Disables S/PDIF transmitter

01 Data originates from S/PDIF Output Channel 0 and S/PDIF Output Channel 1

10 Data copied directly from S/PDIF Receiver Channel 0 and S/PDIF Receiver

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 117 of 202 SERIAL PORT CONFIGURATION REGISTERS Serial Port Control 0 Register Address: 0xF200 to 0xF21C (Increments of 0x4), Reset: 0x0000, Name: SERIAL_BYTE_x_0 These eight registers configure several settings for the corresponding serial input and serial output ports. Channel count, MSB position, data-word length, clock polarity, clock sources, and clock type are configured using these registers. On the input side, Register 0xF200 (SERIAL_BYTE_0_0) corresponds to SDATA_IN0; Register 0xF204 (SERIAL_BYTE_1_0) corresponds to SDATA_IN1; Register 0xF208 (SERIAL_BYTE_2_0) corresponds to SDATA_IN2; and Register 0xF20C (SERIAL_BYTE_3_0) corresponds to SDATA_IN3. On the output side, Register 0xF210 (SERIAL_BYTE_4_0) corresponds to SDATA_OUT0; Register 0xF214 (SERIAL_BYTE_5_0) corresponds to SDATA_OUT1; Register 0xF218 (SERIAL_BYTE_6_0) corresponds to SDATA_OUT2; and Register 0xF21C (SERIAL_BYTE_7_0) corresponds to SDATA_OUT3.

Table 80. Bit Descriptions for SERIAL_BYTE_x_0 pins for SDATA_INx pins or LRCLK_OUTx pins for SDATA_OUTx pins).

000 Slave from LRCLK_IN0 or LRCLK_OUT0

001 Slave from LRCLK_IN1 or LRCLK_OUT1

010 Slave from LRCLK_IN2 or LRCLK_OUT2

011 Slave from LRCLK_IN3 or LRCLK_OUT3

100 Master mode; corresponding LRCLK pin actively outputs a clock signal

BCLK_OUTx pins for SDATA_OUTx pins).

000 Slave from BCLK_IN0 or BCLK_OUT0

001 Slave from BCLK_IN1 or BCLK_OUT1

010 Slave from BCLK_IN2 or BCLK_OUT2

011 Slave from BCLK_IN3 or BCLK_OUT3

100 Master mode; corresponding BCLK pi n actively outputs a clock signal

1 Pulse with a width equal to one bit clock cycle

0 Negative polarity; frame starts on falling edge of frame clock

1 Positive polarity; frame starts on rising edge of frame clock

0 Negative polarity; data transiti ons on falling edge of bit clock

1 Positive polarity; data transitions on rising edge of bit clock

input or output cells are required in SigmaStudio.

11 Flexible TDM mode (configure using Register 0xF300 to Register 0xF33F,

the corresponding serial port.

00 I 2S (delay data by one BCLK cycle)

01 Left justified (delay data by zero BCLK cycles)

10 Right justified for 24-bit data (delay data by 8 BCLK cycles)

11 Right justified for 16-bit data (delay data by 16 BCLK cycles)

(SERIAL_BYTE_6_1) corresponds to SDATA_OUT2; and Register 0xF21D (SERIAL_BYTE_7_1) corresponds to SDATA_OUT3. Table 81. Bit Descriptions for SERIAL_BYTE_x_1

1 The corresponding serial data output pin is high impedance during

0 Drive every output channel

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 120 of 202 Bits Bit Name Settings Description Reset Access [4:3] CLK_DOMAIN Selects the clock generator to use for the serial port. These bits select the clock generator to use for this serial port when it is configured as a clock master. This setting is valid only when Bits[15:13] (LRCLK_SRC) of the corresponding SERIAL_BYTE_x_0 register are set to 0b100 (master mode) and Bits[12:10] (BCLK_SRC) are set to 0b100 (master mode). 0x0 RW

00 Clock Generator 1

01 Clock Generator 2

10 Clock Generator 3 (high precision clock generator)

[2:0] FS Sample rate. These bits set the sample rate to use for the serial port when it is configured as a clock master. This setting is valid only when Bits[15:13] (LRCLK_SRC) of the corresponding SERIAL_BYTE_x_0 register are set to 0b100 (master mode) and Bits[12:10] BCLK_SRC are set to 0b100 (master mode). Bits[4:3] (CLK_DOMAIN) select which clock generator to use, and Bits[2:0] (FS) select which of the five clock generator outputs to use. 0x2 RW

000 Quarter rate of selected clock generator

001 Half rate of selected clock generator

010 Base rate of selected clock generator

011 Double rate of selected clock generator

100 Quadruple rate of selected clock generator

input to the SDATA_IN2 and SDATA_IN3 pins. Table 82. Bit Descriptions for FTDM_INx the selected input pin is ignored.

0 Disable byte

1 Enable byte

reversing the order of the bits from MSB to LSB.

0 Do not reverse bits (big endian)

1 Reverse bits (little endian)

channel assignment is determined by Bits[4:2] (CHANNEL_IN_POS).

0 Select data from the flexible TDM stream on the SDATA_IN2 pin

1 Select data from the flexible TDM stream on the SDATA_IN3 pin

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 122 of 202 Bits Bit Name Settings Description Reset Access [4:2] CHANNEL_IN_POS Source channel selector. These bits map the slot to an audio input channel. If Bit 5 (SERIAL_IN_SEL) = 0b0, Position 0 maps to Channel 32, Position 1 maps to Channel 33, and so on. If Bit 5 (SERIAL_IN_SEL) = 0b1, Position 0 maps to Channel 40, Position 1 maps to Channel 41, and so on. 0x0 RW

000 Channel 0 (in the TDM8 stream)

001 Channel 1 (in the TDM8 stream)

010 Channel 2 (in the TDM8 stream)

011 Channel 3 (in the TDM8 stream)

100 Channel 4 (in the TDM8 stream)

101 Channel 5 (in the TDM8 stream)

110 Channel 6 (in the TDM8 stream)

111 Channel 7 (in the TDM8 stream)

[1:0] BYTE_IN_POS Byte selector for source channel. These bits determine which byte the slot fills in the channel selected by Bit 5 (SERIAL_IN_SEL) and Bits[4:2] (CHANNEL_IN_POS). Each channel consists of four bytes that are selectable by the four options available in this bit field. 0x0 RW

00 Byte 0; Bits[31:24]

01 Byte 1; Bits[23:16]

10 Byte 2; Bits[15:8]

11 Byte 3; Bits[7:0]

FTDM Mapping for the Serial Outputs Register Address: 0xF380 to 0xF3BF (Increments of 0x1), Reset: 0x0000, Name: FTDM_OUTx These 64 registers correspond to the 64 data slots for the flexible TDM output modes on the SDATA_OUT2 and SDATA_OUT3 pins. Slot 0 to Slot 31 are available for use on SDATA_OUT2, and Slot 32 to Slot 63 are available for use on SDATA_OUT3. Each slot can potentially hold one byte of data. Slots are mapped to corresponding audio channels in the serial ports by Bits[5:0] in these registers.

Table 83. Bit Descriptions for FTDM_OUTx period in which the corresponding flexible TDM slot is output. slot by optionally reversing the order of the bits from MSB to LSB.

0 Do not reverse byte (big endian)

1 Reverse byte (little endian)

of data for the corresponding flexible TDM output slot.

0 Serial Output Channel 32 to Serial Output Channel 39

1 Serial Output Channel 40 to Serial Output Channel 47

Serial Output Channel 40 and Serial Output Channel 47.

000 Serial Output Channel 32 or Serial Output Channel 40

001 Serial Output Channel 33 or Serial Output Channel 41

010 Serial Output Channel 34 or Serial Output Channel 42

011 Serial Output Channel 35 or Serial Output Channel 43

100 Serial Output Channel 36 or Serial Output Channel 44

101 Serial Output Channel 37 or Serial Output Channel 45

110 Serial Output Channel 38 or Serial Output Channel 46

111 Serial Output Channel 39 or Serial Output Channel 47

to 32 bits in the data-word, four bytes are available.

any other control registers. During hibernation, interrupts to the core are disabled. This prevents audio from flowing into or out of the DSP core. Because DSP processing ceases when hibernation is active, there is a significant drop in the current consumption on the DVDD supply. Table 84. Bit Descriptions for Hibernate 0 Not hibernating; interrupts enabled. 1 Enter hibernation; interrupts disabled.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 125 of 202 Start Pulse Selection Register Address: 0xF401, Reset: 0x0002, Name: START_PULSE This register selects the start pulse that marks the beginning of each audio frame in the DSP core. This effectively sets the sample rate of the audio going through the DSP . This start pulse can originate from either an internally generated pulse (from Clock Generator 1 or Clock Generator 2) or from an external clock that is received on one of the LRCLK pins of one of the serial ports. Any audio input or output from the DSP core that is asynchronous to this DSP start pulse rate must go through an ASRC. If asynchronous audio signals (that is, signals that are not synchronized to whatever start pulse is selected) are input to the DSP without first going through an ASRC, samples are skipped or doubled, leading to distortion and audible artifacts in the audio signal.

Table 85. Bit Descriptions for START_PULSE

00000 Base sample rate ÷ 4 (12 kHz for 48 kHz base sample rate) (1/4 output of Clock Generator 1)

00001 Base sample rate ÷ 2 (24 kHz for 48 kHz base sample rate) (1/2 output of Clock Generator 1)

00010 Base sample rate (48 kHz for 48 kHz base sample rate) (×1 output of Clock Generator 1)

00011 Base sample rate × 2 (96 kHz for 48 kHz base sample rate) (×2 output of Clock Generator 1)

00100 Base sample rate × 4 (192 kHz for 48 kHz base sample rate) (×4 output of Clock

00101 Base sample rate ÷ 6 (8 kHz for 48 kHz base sample rate) (1/4 output of Clock Generator 2)

00110 Base sample rate ÷ 3 (16 kHz for 48 kHz base sample rate) (1/2 output of Clock Generator 2)

01000 Serial Input Port 0 sample rate (Regis ter 0xF201 (SERIAL_BYTE_0_1), Bits[4:0])

01001 Serial Input Port 1 sample rate (Regis ter 0xF205 (SERIAL_BYTE_1_1), Bits[4:0])

01010 Serial Input Port 2 sample rate (Regis ter 0xF209 (SERIAL_BYTE_2_1), Bits[4:0])

01011 Serial Input Port 3 sample rate (Register 0xF20D (SERIAL_BYTE_3_1), Bits[4:0])

01100 Serial Output Port 0 sample rate (Register 0xF211 (SERIAL_BYTE_4_1), Bits[4:0])

01101 Serial Output Port 1 sample rate (Register 0xF215 (SERIAL_BYTE_5_1), Bits[4:0])

01110 Serial Output Port 2 sample rate (Register 0xF219 (SERIAL_BYTE_6_1), Bits[4:0])

01111 Serial Output Port 3 sample rate (Regis ter 0xF21D (SERIAL_BYTE_7_1), Bits[4:0])

10000 S/PDIF receiver sample rate (derived from the S/PDIF input stream)

core, use Register 0xF400 (HIBERNATE), Bit 0 (HIBERNATE). Table 86. Bit Descriptions for START_CORE

0 START_CORE A transition of this bit from 0b0 to 0b1 enables the DSP core to start executing

its program. A transition from 0b1 to 0b0 does not affect the DSP core.

0 A transition from 0b0 to 0b1 enables the DSP core to start program execution

1 A transition from 0b1 to 0b0 does not affect the DSP core

Table 87. Bit Descriptions for KILL_CORE Register 0xF400 (HIBERNATE) to halt the core in a controlled manner.

0 A transition from 0b0 to 0b1 immediately halts the core

1 A transition from 0b1 to 0b0 has no effect

modify the value of this register. Table 88. Bit Descriptions for START_ADDRESS

(HIBERNATE), Register 0xF402 (START_CORE), and Register 0xF403 (KILL_CORE). Table 89. Bit Descriptions for CORE_STATUS 001 Core is running normally. explicitly defined in the DSP program.

011 Core is in sleep mode (the core may be actively running a program, but it

is explicitly called in the DSP program.

(PANIC_CLEAR) of this register from 0b0 to 0b1 and then back to 0b0 again to clear the flag and reset the state of the panic manager. Table 90. Bit Descriptions for PANIC_CLEAR

0 Panic manager is not cleared

1 Clear panic manager (on a rising edge of this bit)

configure which memories, if any, are subject to error reporting. Table 91. Bit Descriptions for PANIC_PARITY_MASK

0 Report DM1_BANK3 parity mask errors

1 Do not report DM1_BANK3 parity mask errors

0 Report DM1_BANK2 parity mask errors

1 Do not report DM1_BANK2 parity mask errors

0 Report DM1_BANK1 parity mask errors

1 Do not report DM1_BANK1 parity mask errors

0 Report DM1_BANK0 parity mask errors

1 Do not report DM1_BANK0 parity mask errors

0 Report DM0_BANK3 parity mask errors

1 Do not report DM0_BANK3 parity mask errors

0 Report DM0_BANK2 parity mask errors

1 Do not report DM0_BANK2 parity mask errors

0 Report DM0_BANK1 parity mask errors

1 Do not report DM0_BANK1 parity mask errors

0 Report DM0_BANK0 parity mask errors

1 Do not report DM0_BANK0 parity mask errors

0 Report PM1 parity mask errors

1 Do not report PM1 parity mask errors

0 Report PM0 parity mask errors

1 Do not report PM0 parity mask errors

0 Report ASRC 1 parity mask errors

1 Do not report ASRC 1 parity mask errors

0 Report ASRC 0 parity mask errors

1 Do not report ASRC 0 parity mask errors

whether software errors are reported to the panic manager or ignored. Table 92. Bit Descriptions for PANIC_SOFTWARE_MASK

0 Report parity errors

1 Do not report parity errors

watchdog errors are reported to the panic manager or ignored. Table 93. Bit Descriptions for PANIC_WD_MASK

0 Report watchdog errors

1 Do not report watchdog errors

errors are reported to the panic manager or ignored. Table 94. Bit Descriptions for PANIC_STACK_MASK

0 Report stack errors

1 Do not report stack errors

the user to configure whether loop errors are reported to the panic manager or ignored. Table 95. Bit Descriptions for PANIC_LOOP_MASK

0 Report loop errors

1 Do not report loop errors

(PANIC_STACK_MASK), and Register 0xF426 (PANIC_LOOP_MASK). Table 96. Bit Descriptions for PANIC_FLAG Register 0xF421 (PANIC_CLEAR).

0 No error

1 Error

register is cleared by toggling Register 0xF421 (PANIC_CLEAR). Table 97. Bit Descriptions for PANIC_CODE

0 No error from the software panic

1 Error from the software panic

0 No error from the loop overrun

1 Error from the loop overrun

0 No error from the stack overrun

1 Error from the stack overrun

0 No error from the watchdog counter

1 Error from the watchdog counter

0 No error in DM1 Bank 3

1 Error in DM1 Bank 3

0 No error in DM1 Bank 2

1 Error in DM1 Bank 2

0 No error in DM1 Bank 1

1 Error in DM1 Bank 1

0 No error in DM1 Bank 0

1 Error in DM1 Bank 0

0 No error in DM0 Bank 3

1 Error in DM0 Bank 3

0 No error in DM0 Bank 2

1 Error in DM0 Bank 2

0 No error in DM0 Bank 1

1 Error in DM0 Bank 1

0 No error in DM0 Bank 0

1 Error in DM0 Bank 0

0 No error in PM1

1 Error in PM1

0 No error in PM0

1 Error in PM0

0 No error in ASRC 1

1 Error in ASRC 1

0 No error in ASRC 0

1 Error in ASRC 0

Table 98. Bit Descriptions for EXECUTE_COUNT

Table 99. Bit Descriptions for SOFTWARE_VALUE_0 Table 100. Bit Descriptions for SOFTWARE_VALUE_1

This register is designed to start counting at a specified number and decrement by 1 for each clock cycle of the system clock in the core. instructions expected to execute in the program, such that an error occurs if the program does not finish in time for the next incoming sample. Table 101. Bit Descriptions for WATCHDOG_MAXCOUNT

1024, a very large watchdog counter, on the order of 8.5 billion clock cycles, can be achieved. Table 102. Bit Descriptions for WATCHDOG_PRESCALE

0000 Increment every 64 clock cycles

0001 Increment every 128 clock cycles

0010 Increment every 256 clock cycles

0011 Increment every 512 clock cycles

0100 Increment every 1024 clock cycles

0101 Increment every 2048 clock cycles

0110 Increment every 4096 clock cycles

0111 Increment every 8192 clock cycles

1000 Increment every 16,384 clock cycles

1001 Increment every 32,768 clock cycles

1010 Increment every 65,536 clock cycles

1011 Increment every 131,072 clock cycles

This register enables block interrupts, which are necessary when frequency domain processing is required in the audio processing program. to manually change the value of this register after SigmaStudio has configured it. Table 103. Bit Descriptions for BLOCKINT_EN

0 Disable block interrupts

1 Enable block interrupts

by the DSP core. When the counter reaches the value determined by this register, a block interrupt is generated and the counter is reset. to manually change the value of this register after SigmaStudio has configured it. Table 104. Bit Descriptions for BLOCKINT_VALUE This register, in combination with Register 0xF461 (PROG_CNTR1), stores the current value of the program counter. Table 105. Bit Descriptions for PROG_CNTR0

This register, in combination with Register 0xF460 (PROG_CNTR0), stores the current value of the program counter. Table 106. Bit Descriptions for PROG_CNTR1 Table 107. Bit Descriptions for PROG_CNTR_CLEAR

0 Allow the program counter to update itself

1 Clear the program counter and disable it from updating itself

counter during the last audio frame or block. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 108. Bit Descriptions for PROG_CNTR_LENGTH0

counter during the last audio frame or block. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 109. Bit Descriptions for PROG_CNTR_LENGTH1 the program counter since the DSP core started. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 110. Bit Descriptions for PROG_CNTR_MAXLENGTH0 the program counter since the DSP core started. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 111. Bit Descriptions for PROG_CNTR_MAXLENGTH1

Table 112. Bit Descriptions for PANIC_PARITY_MASK1

0 Report Bank 1 Subbank 4 parity errors

1 Ignore Bank 1 Subbank 4 parity errors

0 Report Bank 1 Subbank 3 parity errors

1 Ignore Bank 1 Subbank 3 parity errors

0 Report Bank 1 Subbank 2 parity errors

1 Ignore Bank 1 Subbank 2 parity errors

0 Report Bank 1 Subbank 1 parity errors

1 Ignore Bank 1 Subbank 1 parity errors

0 Report Bank 1 Subbank 0 parity errors

1 Ignore Bank 1 Subbank 0 parity errors

0 Report Bank 0 Subbank 4 parity errors

1 Ignore Bank 0 Subbank 4 parity errors

0 Report Bank 0 Subbank 3 parity errors

1 Ignore Bank 0 Subbank 3 parity errors

0 Report Bank 0 Subbank 2 parity errors

1 Ignore Bank 0 Subbank 2 parity errors

0 Report Bank 0 Subbank 1 parity errors

1 Ignore Bank 0 Subbank 1 parity errors

0 Report Bank 0 Subbank 0 parity errors

1 Ignore Bank 0 Subbank 0 parity errors

Table 113. Bit Descriptions for PANIC_PARITY_MASK2

0 Report Bank 3 Subbank 4 parity errors

1 Ignore Bank 3 Subbank 4 parity errors

0 Report Bank 3 Subbank 3 parity errors

1 Ignore Bank 3 Subbank 3 parity errors

0 Report Bank 3 Subbank 2 parity errors

1 Ignore Bank 3 Subbank 2 parity errors

0 Report Bank 3 Subbank 1 parity errors

1 Ignore Bank 3 Subbank 1 parity errors

0 Report Bank 3 Subbank 0 parity errors

1 Ignore Bank 3 Subbank 0 parity errors

0 Report Bank 2 Subbank 4 parity errors

1 Ignore Bank 2 Subbank 4 parity errors

0 Report Bank 2 Subbank 3 parity errors

1 Ignore Bank 2 Subbank 3 parity errors

0 Report Bank 2 Subbank 2 parity errors

1 Ignore Bank 2 Subbank 2 parity errors

0 Report Bank 2 Subbank 1 parity errors

1 Ignore Bank 2 Subbank 1 parity errors

0 Report Bank 2 Subbank 0 parity errors

1 Ignore Bank 2 Subbank 0 parity errors

Table 114. Bit Descriptions for PANIC_PARITY_MASK3

Table 115. Bit Descriptions for PANIC_PARITY_MASK4

Table 116. Bit Descriptions for PANIC_PARITY_MASK5

0 Report Bank 1 Subbank 5 parity errors

1 Ignore Bank 1 Subbank 5 parity errors

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 147 of 202 Bits Bit Name Settings Description Reset Access 11 PM_BANK1_SUBBANK3_MASK Bank 1 Subbank 3 mask. 0x0 RW 10 PM_BANK1_SUBBANK2_MASK Bank 1 Subbank 2 mask. 0x0 RW 9 PM_BANK1_SUBBANK1_MASK Bank 1 Subbank 1 mask. 0x0 RW 8 PM_BANK1_SUBBANK0_MASK Bank 1 Subbank 0 mask. 0x0 RW [7:6] RESERVED Reserved. 0x0 RW 5 PM_BANK0_SUBBANK5_MASK Bank 0 Subbank 5 mask. 0x0 RW

0 Report Bank 0 Subbank 5 parity errors

1 Ignore Bank 0 Subbank 5 parity errors

4 PM_BANK0_SUBBANK4_MASK Bank 0 Subbank 4 mask. 0x0 RW 3 PM_BANK0_SUBBANK3_MASK Bank 0 Subbank 3 mask. 0x0 RW 2 PM_BANK0_SUBBANK2_MASK Bank 0 Subbank 2 mask. 0x0 RW 1 PM_BANK0_SUBBANK1_MASK Bank 0 Subbank 1 mask. 0x0 RW 0 PM_BANK0_SUBBANK0_MASK Bank 0 Subbank 0 mask. 0x0 RW

Table 117. Bit Descriptions for PANIC_CODE1

0 No error in Bank 1 Subbank 4

1 Error in Bank 1 Subbank 4

0 No error in Bank 1 Subbank 3

1 Error in Bank 1 Subbank 3

0 No error in Bank 1 Subbank 2

1 Error in Bank 1 Subbank 2

0 No error in Bank 1 Subbank 1

1 Error in Bank 1 Subbank 1

0 No error in Bank 1 Subbank 0

1 Error in Bank 1 Subbank 0

0 No error in Bank 0 Subbank 4

1 Error in Bank 0 Subbank 4

0 No error in Bank 0 Subbank 3

1 Error in Bank 0 Subbank 3

0 No error in Bank 0 Subbank 2

1 Error in Bank 0 Subbank 2

0 No error in Bank 0 Subbank 1

1 Error in Bank 0 Subbank 1

0 No error in Bank 0 Subbank 0

1 Error in Bank 0 Subbank 0

Table 118. Bit Descriptions for PANIC_CODE2

0 No error in Bank 3 Subbank 4

1 Error in Bank 3 Subbank 4

0 No error in Bank 3 Subbank 3

1 Error in Bank 3 Subbank 3

0 No error in Bank 3 Subbank 2

1 Error in Bank 3 Subbank 2

0 No error in Bank 3 Subbank 1

1 Error in Bank 3 Subbank 1

0 No error in Bank 3 Subbank 0

1 Error in Bank 3 Subbank 0

0 No error in Bank 2 Subbank 4

1 Error in Bank 2 Subbank 4

0 No error in Bank 2 Subbank 3

1 Error in Bank 2 Subbank 3

0 No error in Bank 2 Subbank 2

1 Error in Bank 2 Subbank 2

0 No error in Bank 2 Subbank 1

1 Error in Bank 2 Subbank 1

0 No error in Bank 2 Subbank 0

1 Error in Bank 2 Subbank 0

Table 119. Bit Descriptions for PANIC_CODE3

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 151 of 202 Bits Bit Name Settings Description Reset Access 9 ERR_DM1B1SB1 Error in Bank 1 Subbank 1. 0x0 R 8 ERR_DM1B1SB0 Error in Bank 1 Subbank 0. 0x0 R [7:5] RESERVED Reserved. 0x0 RW 4 ERR_DM1B0SB4 Error in Bank 0 Subbank 4. 0x0 R 3 ERR_DM1B0SB3 Error in Bank 0 Subbank 3. 0x0 R 2 ERR_DM1B0SB2 Error in Bank 0 Subbank 2. 0x0 R 1 ERR_DM1B0SB1 Error in Bank 0 Subbank 1. 0x0 R 0 ERR_DM1B0SB0 Error in Bank 0 Subbank 0. 0x0 R Panic Parity Error DM1 Bank [3:2] Register Address: 0xF46F, Reset: 0x0000, Name: P ANIC_CODE4

Table 120. Bit Descriptions for PANIC_CODE4

Table 121. Bit Descriptions for PANIC_CODE5

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 154 of 202 Bits Bit Name Settings Description Reset Access 4 ERR_PM_B0SB4 Error in Bank 0 Subbank 4. 0x0 R 3 ERR_PM_B0SB3 Error in Bank 0 Subbank 3. 0x0 R 2 ERR_PM_B0SB2 Error in Bank 0 Subbank 2. 0x0 R 1 ERR_PM_B0SB1 Error in Bank 0 Subbank 1. 0x0 R 0 ERR_PM_B0SB0 Error in Bank 0 Subbank 0. 0x0 R

Table 122. Bit Descriptions for MPx_MODE be connected to the SPI master port, all using different slave select lines. multipurpose pin that has been configured as a slave select output.

000 Slave Select Channel 1

001 Slave Select Channel 2

010 Slave Select Channel 3

011 Slave Select Channel 4

100 Slave Select Channel 5

101 Slave Select Channel 6

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 156 of 202 Bits Bit Name Settings Description Reset Access [7:4] DEBOUNCE_VALUE Debounce circuit setting. These bits configure the duration of the debounce circuitry when the corresponding pin is configured as an input (Bits[3:1] (MP_MODE) = 0b000). 0x0 RW 0001 0.3 ms debounce 0010 0.6 ms debounce 0011 0.9 ms debounce 0100 5.0 ms debounce 0101 10.0 ms debounce 0110 20.0 ms debounce 0111 40.0 ms debounce

0000 No debounce

[3:1] MP_MODE Pin mode (when multipurpose function is enabled). These bits select the function of the corresponding pin if it is enabled in multipurpose mode (Bit 0 (MP_ENABLE) = 0b1). 0x0 RW

000 General-purpose digital input

001 General-purpose input, driven by control port; sends its value to the DSP

core, but that value can be overwritten by a direct register write

010 General-purpose output with pull-up

011 General-purpose output without pull-up

100 PDM microphone data input

101 Panic manager error flag output

110 Slave select line for the master SPI port

0 MP_ENABLE Function selection (multipurpose or clock/control). This bit selects whether the corresponding pin is used as a multipurpose pin or as its primary function (which could be either an audio clock or control bus pin). 0x0 RW

0 Audio clock or control port function enabled; the settings of the MPx_MODE,

MPx_WRITE, and MPx_READ registers are ignored

1 Multipurpose function enabled

that is output from the DSP core can be configured by directly writing to these registers. Table 123. Bit Descriptions for MPx_WRITE

0 MP_REG_WRITE Multipurpose pin output state when pin is configured as an output written

logic low (off ) or logic high (on).

0 Multipurpose pin output low

1 Multipurpose pin output high

Table 124. Bit Descriptions for MPx_READ

0 Multipurpose pin input low

1 Multipurpose pin input high

(DMIC_CTRL1) configures PDM Microphone Channel 2 and PDM Microphone Channel 3. Table 125. Bit Descriptions for DMIC_CTRLx

15 RESERVED 0x0 RW

microphone data signal(s). To use these bits, Bit 3 (HPF), must be enabled.

Data Sheet ADAU1462/ADAU1466 Rev. C | Page 159 of 202 Bits Bit Name Settings Description Reset Access [11:8] MIC_DATA_SRC Digital PDM microphone data source pin. These bits configure which hardware pin acts as a data input from the PDM microphone(s). Up to two microphones can be connected to a single pin. 0x0 RW

0000 SS_M/MP0

0001 MOSI_M/MP1

0010 SCL_M/SCLK_M/MP2

0011 SDA_M/MISO_M/MP3

0100 LRCLK_OUT0/MP4

0101 LRCLK_OUT1/MP5

0110 MP6

0111 MP7

1000 LRCLK_OUT2/MP8

1001 LRCLK_OUT3/MP9

1010 LRCLK_IN0/MP10

1011 LRCLK_IN1/MP11

1100 LRCLK_IN2/MP12

1101 LRCLK_IN3/MP13

7 RESERVED 0x0 RW

[6:4] DMIC_CLK Digital PDM microphone clock select. A valid bit clock signal must be assigned to the PDM microphones. Any of the four BCLK_INPUTx or four BCLK_OUTPUTx signals can be used. A trace must connect the selected pin to the clock input pin on the corresponding PDM microphone(s). If the corresponding BCLK_x pin is not configured in master mode, use an external clock source, with the BCLK_x pin and the PDM microphone acting as slaves. 0x0 RW

000 BCLK_IN0

001 BCLK_IN1

010 BCLK_IN2

011 BCLK_IN3

100 BCLK_OUT0

101 BCLK_OUT1

110 BCLK_OUT2

111 BCLK_OUT3

3 HPF High-pass filter enable. This bit enables or disables a high-pass filter to remove dc components from the microphone data signals. The cutoff of the filter is controlled by Bits[14:12] (CUTOFF). 0x0 RW

0 HPF disabled

1 HPF enabled

2 DMPOL Data polarity swap. When this bit is set to 0b0, a logic high data input is treated as logic high, and a logic low data input is treated as logic low. When this bit is set to 0b1, the opposite is true: a logic high data input is treated as a logic low, and a logic low data input is treated as logic high. This effectively inverts the amplitude of the incoming audio data. 0x0 RW

0 Data polarity normal

1 Data polarity inverted

1 DMSW Digital PDM microphone channel swap. In DMIC_CTRL0, this bit swaps PDM Microphone Channel 0 and PDM Microphone Channel 1. In the DMIC_CTRL1 register, this bit swaps PDM Microphone Channel 2 and PDM Microphone Channel 3. 0x0 RW

0 Normal

1 Swap left and right channels

0 DMIC_EN Digital PDM microphone enable. This bit enables or disables the data input from the PDM microphones. 0x0 RW

0 Digital PDM microphone disabled

1 Digital PDM microphone enabled

conditions is not true, the corresponding lock bit is high. Table 126. Bit Descriptions for ASRC_LOCK

0 Locked

1 Unlocked

341.3 ms. Bit 10 (LOCKMUTE) allows the ASRCs to automatically mute themselves in the event that lock status is lost or not attained. Table 127. Bit Descriptions for ASRC_MUTE the automatic LOCKMUTE behavior.

0 Do not mute when lock is lost

1 Mute when lock is lost, and unmute when lock is reattained

ADAU1462/ADAU1466 Data Sheet Rev. C | Page 162 of 202 Bits Bit Name Settings Description Reset Access 9 ASRC_RAMP1 ASRC 7 to ASRC 4 mute disable. ASRC 7 to ASRC 4 (Channel 15 to Channel 8) are defined as ASRC Block 1. This bit enables or disables mute ramping for all ASRCs in Block 1. If this bit is 0b1, Bit 7 (ASRC7M), Bit 6 (ASRC6M), Bit 5 (ASRC5M), and Bit 4 (ASRC4M) are ignored, and the outputs of ASRC 7 to ASRC 4 are active at all times. 0x0 RW

0 Enabled

1 Disabled; ASRC 7 to ASRC 4 never mute automatically and cannot be

8 ASRC_RAMP0 ASRC 3 to ASRC 0 mute disable. ASRC 3 to ASRC 0 (Channel 7 to Channel 0) are defined as ASRC Block 0. This bit enables or disables mute ramping for all ASRCs in Block 0. If this bit is 0b1, Bit 3 (ASRC3M), Bit 2 (ASRC2M), Bit 1 (ASRC1M), and Bit 0 (ASRC0M) are ignored, and the outputs of ASRC 3 to ASRC 0 are active at all times. 0x0 RW

1 Disabled; ASRC 3 to ASRC 0 never mute automatically and cannot be

7 ASRC7M ASRC 7 manual mute. 0x0 RW

0 Not muted

1 Muted

6 ASRC6M ASRC 6 manual mute. 0x0 RW 5 ASRC5M ASRC 5 manual mute. 0x0 RW 4 ASRC4M ASRC 4 manual mute. 0x0 RW 3 ASRC3M ASRC 3 manual mute. 0x0 RW 2 ASRC2M ASRC 2 manual mute. 0x0 RW 1 ASRC1M ASRC 1 manual mute. 0x0 RW 0 ASRC0M ASRC 0 manual mute. 0x0 RW

Table 128. Bit Descriptions for ASRCx_RATIO the input to output rate of the corresponding ASRC. It is stored in 4.12 format. Table 129. Bit Descriptions for ASRC_RAMPMAX_OVR

0 Disable RAMPMAX override

1 Enable RAMPMAX override

Table 130. Bit Descriptions for ASRCx_RAMPMAX

Table 131. Bit Descriptions for ADC_READx linearly mapped to dc voltages between 0 V and AVDD.

This register contains a flag that monitors the S/PDIF receiver and provides a way to check the validity of the input signal. Table 132. Bit Descriptions for SPDIF_LOCK_DET

0 No lock acquired; no valid input stream detected

1 Successful lock to input stream

This register provides controls that govern the behavior of the S/PDIF receiver on the ADAU1466 and ADAU1462. Table 133. Bit Descriptions for SPDIF_RX_CTRL

0 Normal (locks after 64 consecutive valid samples)

1 Fast (locks after eight consecutive valid samples)

applies to the output of the recovered frame clock from the S/PDIF receiver.

0 Strong; output is continued as we ll as is possible when the receiver

1 Weak; output is interrupted as soon as receiver notices a loss of lock condition

11 Automatic (determined by channel status bits detected in the input stream)

them, providing insight into the data format of the S/PDIF input stream. Table 134. Bit Descriptions for SPDIF_RX_DECODE

1 COMPR_TYPE AC3 or DTS compression (valid only if Bit 0 (AUDIO_TYPE) = 0b1

0 AC3

1 DTS

0 Linear PCM

1 Compressed

the 16-bit code that represents the type of compression being used. Table 135. Bit Descriptions for SPDIF_RX_COMPRMODE valid input signal is detected, set Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), to 0b1 at all times. Table 136. Bit Descriptions for SPDIF_RESTART

0 RESTART_AUDIO Allows the S/PDIF receiver to automatically resume outputting audio

when it successfully recovers from a loss of lock.

0 Do not automatically restart the audio when a relock occurs

1 Restarts the audio automatically when a relock occurs, and resets

0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), can be reset to 0b0 if required. Table 137. Bit Descriptions for SPDIF_LOSS_OF_LOCK

0 S/PDIF receiver is locked to the input stream and has not lost lock since

1 S/PDIF receiver acquired a lock on the input stream but then subsequently

outputs an 8-channel TDM stream containing this decoded information. Channel 0 in the TDM8 stream contains the 24 audio bits from the left S/PDIF input channel, followed by eight zero bits. S/PDIF input channel, followed by eight zero bits. and the audio type bit (0b0 represents PCM and 0b1 represents compressed), followed by eight zero bits. Channel 3 in the TDM8 stream contains 32 zero bits. Channel 4 in the TDM8 stream contains the 24 audio bits from the right S/PDIF input channel, followed by eight zero bits. right S/PDIF input channel, followed by eight zero bits. Channel 6 in the TDM8 stream contains 32 zero bits. Channel 7 in the TDM8 stream contains 23 zero bits, the block start bit, and eight zero bits. Table 138. Bit Descriptions for SPDIF_AUX_EN 0b1110, and Register 0xF026 (CLK_GEN3_SRC), Bit 4 (CLK_GEN3_SRC), must be 0b1.

1 Use filtered clocks from internal clock generator

0001 Output on SDATA_OUT0

0010 Output on SDATA_OUT1

0100 Output on SDATA_OUT2

1000 Output on SDATA_OUT3

0000 Disable S/PDIF TDM output

Table 139. Bit Descriptions for SPDIF_RX_AUXBIT_READY

0 Auxiliary bits are not ready to be output

1 Auxiliary bits are ready to be output

Table 140. Bit Descriptions for SPDIF_RX_CS_LEFT_x Table 141. Bit Descriptions for SPDIF_RX_CS_RIGHT_x

Table 142. Bit Descriptions for SPDIF_RX_UD_LEFT_x Table 143. Bit Descriptions for SPDIF_RX_UD_RIGHT_x These 12 registers store the 192 validity bits decoded from the left channel of the S/PDIF input stream on the ADAU1466 and ADAU1462. Table 144. Bit Descriptions for SPDIF_RX_VB_LEFT_x

These 12 registers store the 192 validity bits decoded from the left channel of the S/PDIF input stream on the ADAU1466 and ADAU1462. Table 145. Bit Descriptions for SPDIF_RX_VB_RIGHT_x These 12 registers store the 192 parity bits decoded from the left channel of the S/PDIF input stream on the ADAU1466 and ADAU1462. Table 146. Bit Descriptions for SPDIF_RX_PB_LEFT_x These 12 registers store the 192 parity bits decoded from the right channel of the S/PDIF input stream on the ADAU1466 and ADAU1462. Table 147. Bit Descriptions for SPDIF_RX_PB_RIGHT_x

the purpose of power savings, set Register 0xF051 (POWER_ENABLE1), Bit 2 (TX_PWR) = 0b0. Table 148. Bit Descriptions for SPDIF_TX_EN

0 Disabled

1 Enabled

stream of the S/PDIF receiver automatically set the word length on the S/PDIF transmitter. Table 149. Bit Descriptions for SPDIF_TX_CTRL

11 Automatic (determined by channel status bits detected in the S/PDIF

SPDIF_TX_VB_RIGHT_x, SPDIF_TX_PB_LEFT_x, and SPDIF_TX_PB_RIGHT_x. Table 150. Bit Descriptions for SPDIF_TX_AUXBIT_SOURCE

0 Source from register map (user programmable)

1 Source from S/PDIF receiver (derived from input data stream)

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 151. Bit Descriptions for SPDIF_TX_CS_LEFT_x

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 152. Bit Descriptions for SPDIF_TX_CS_RIGHT_x (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 153. Bit Descriptions for SPDIF_TX_UD_LEFT_x (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 154. Bit Descriptions for SPDIF_TX_UD_RIGHT_x

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 155. Bit Descriptions for SPDIF_TX_VB_LEFT_x (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 156. Bit Descriptions for SPDIF_TX_VB_RIGHT_x (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 157. Bit Descriptions for SPDIF_TX_PB_LEFT_x

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 158. Bit Descriptions for SPDIF_TX_PB_RIGHT_x

Register 0xF781 corresponds to BCLK_IN1, Register 0xF782 corresponds to BCLK_IN2, and Register 0xF783 corresponds to BCLK_IN3. Table 159. Bit Descriptions for BCLK_INx_PIN

0 Pull-down disabled

1 Pull-down enabled

00 Slowest

01 Slow

10 Fast

11 Fastest

00 Lowest

01 Low

10 High

11 Highest

Table 160. Bit Descriptions for BCLK_OUTx_PIN

Register 0xF78B corresponds to LRCLK_IN3/MP13. Table 161. Bit Descriptions for LRCLK_INx_PIN

Register 0xF78F corresponds to LRCLK_OUT3/MP9. Table 162. Bit Descriptions for LRCLK_OUTx_PIN

Register 0xF791 corresponds to SDATA_IN1, Register 0xF792 corresponds to SDATA_IN2, and Register 0xF793 corresponds to SDATA_IN3. Table 163. Bit Descriptions for SDATA_INx_PIN

Table 164. Bit Descriptions for SDATA_OUTx_PIN

This register configures the drive strength, slew rate, and pull resistors for the SPDIFOUT pin on the ADAU1466 and ADAU1462. Table 165. Bit Descriptions for SPDIF_TX_PIN

This register configures the drive strength, slew rate, and pull resistors for the SCLK/SCL pin. Table 166. Bit Descriptions for SCLK_SCL_PIN

0 Pull-up disabled

1 Pull-up enabled

This register configures the drive strength, slew rate, and pull resistors for the MISO/SDA pin. Table 167. Bit Descriptions for MISO_SDA_PIN

This register configures the drive strength, slew rate, and pull resistors for the SS/ADDR0 pin. Table 168. Bit Descriptions for SS_PIN

This register configures the drive strength, slew rate, and pull resistors for the MOSI/ADDR1 pin. Table 169. Bit Descriptions for MOSI_ADDR1_PIN

This register configures the drive strength, slew rate, and pull resistors for the SCL_M/SCLK_M/MP2 pin. Table 170. Bit Descriptions for SCLK_SCL_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the SDA_M/MISO_M/MP3 pin. Table 171. Bit Descriptions for MISO_SDA_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the SS_M/MP0 pin. Table 172. Bit Descriptions for SS_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the MOSI_M/MP1 pin. Table 173. Bit Descriptions for MOSI_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP6 pin. Table 174. Bit Descriptions for MP6_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP7 pin. Table 175. Bit Descriptions for MP7_PIN

This register configures the drive strength, slew rate, and pull resistors for the CLKOUT pin. Table 176. Bit Descriptions for CLKOUT_PIN

(PLL_LOCK), Register 0xF005 (MCLK_OUT), and Register 0xF006 (PLL_W ATCHDOG), as well as registers related to the panic manager. it to 0b1 enables normal operation and setting it to 0b0 enables the soft reset state. Table 177. Bit Descriptions for SOFT_RESET

0 Soft reset enabled

1 Soft reset disabled; normal operation

EMI increases, creating noisy supplies. examples, see the AN-311 Application Note. Figure 89. Ferrite Bead Power Supply Isolation Circuit Example

Figure 90. Automotive Infotainment Amplifier Block Diagram

a transistor, are required for proper operation of the device. with the VDRIVE pin left floating. high frequency return currents with a short path to ground. frequency currents from the DSP and other digital circuitry. switches from idle mode to operating mode. to improve the EMI/EMC performance of the system. Figure 91. Supporting Component Placement and Layout

PCB manufacturing guidelines.

60 SECONDS

150 SECONDS

180 SECONDS 20 SECONDS

40 SECONDS

480 SECONDS MAX

Figure 92. Soldering Profile Figure 93. PCB Decal Dimensions

0.20 REF

0.80 MAX

0.05 MAX

0.02 NOM

8.50 REF

0.25 MIN

Figure 94. 72-Lead Lead Frame Chip Scale Package [LFCSP] 2 The EVAL-ADAU1466Z can be used to evaluate both the ADAU1462 and the ADAU1466. to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). registered trademarks are the prop erty of their respective owners.