ADAU1446YSTZ-3A-RL

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SigmaDSP Digital Audio Processor with Flexible Audio Routing Matrix ADAU1442/ADAU1445/ADAU1446 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Fully programmable audio digital signal processor (DSP) for enhanced sound processing Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows

172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz

4k parameter RAM, 8k data RAM Flexible audio routing matrix (FARM) 24-channel digital input and output Up to 8 stereo asynchronous sample rate converters (from 1:8 up to 7.75:1 ratio and 139 dB DNR) Stereo S/PDIF input and output Supports serial and TDM I/O, up to f S = 192 kHz Multichannel byte-addressable TDM serial port Pool of 170 ms digital audio delay (at 48 kHz) Clock oscillator for generating master clock from crystal PLL for generating core clock from common audio clocks I 2C and SPI control interfaces Standalone operation Self-boot from serial EEPROM 4-channel, 10-bit auxiliary control ADC Multipurpose pins for digital controls and outputs Easy implementation of available third-party algorithms On-chip regulator for generating 1.8 V from 3.3 V supply 100-lead TQFP and LQFP packages Temperature range: −40°C to +105°C

APPLICATIONS

Automotive audio processing Head units Navigation systems Rear-seat entertainment systems DSP amplifiers (sound system amplifiers) Commercial audio processing FUNCTIONAL BLOCK DIAGRAM PROGRAMMABLE AUDIO PROCESSOR CORE S/PDIF TRANSMITTER S/PDIF RECEIVER UP TO 16 CHANNELS OF ASYNCHRONOUS SAMPLE RATE CONVERTERS SERIAL CLOCK DOMAINS (×12) CLOCK OSCILLATOR MP/ AUX ADC PLL I2C/SPI CONTROL INTERFACE AND SELF-BOOT XTALI XTALO BIT CLOCK† (BCLK) FRAME CLOCK† (LRCLK) BIT CLOCK† (BCLK) FRAME CLOCK† (LRCLK) SPI/I2C* SELFBOOT SPDIFI SPDIFO CLKOUT SDATA_IN[8:0] (24-CHANNEL DIGITAL AUDIO INPUT) SDATA_OUT[8:0] (24-CHANNEL DIGITAL AUDIO OUTPUT) FLEXIBLE AUDIO ROUTING MATRIX (FARM) SERIAL DATA INPUT PORT (×9) SERIAL DATA OUTPUT PORT (×9) 1.8V REGULATOR 07696-001 MP[11:4] MP[3:0]/ ADC[3:0] *SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS. †THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS, SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS. ADAU1442/ ADAU1445/ ADAU1446 Figure 1.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 2 of 92 TABLE OF CONTENTS Serial Output Flexible TDM Interface Modes and Settings . 78

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 3 of 92

REVISION HISTORY

9/10—Rev. B to Rev. C Changes to Stereo ASRC[3:0] Lock Status and Mute Register (Address 0xE101), Stereo ASRC[3:0] Mute Ramp Disable Register (Address 0xE103), and Stereo ASRC[7:4] Lock Status 4/10—Rev. A to Rev. B Changes to Power-Up Sequence Section, System Initialization Changes to ASRC Input Select Pairs[7:0] Registers Changes to Stereo ASRC[3:0] Lock Status and Mute Register Changes to Stereo ASRC[7:4] Lock Status and Mute Register Added Multipurpose Pin Value Registers (Address 0x129A to Address 0x12A5) Section and Table 66; Renumbered 4/09—Rev. 0 to Rev. A Added Minimum Digital Current (DVDD) of ADAU1446, Maximum Digital Current (DVDD) of ADAU1446, and A VDD, DVDD, PVDD During Operation of ADAU1446 Changes to Flexible Audio Routing Matrix—Input Side Section; Changes to ASRC Input Select Pairs[7:0] Registers (Address 0xE080 Changes to Serial Output Data Selector Bits 1/09—Revision 0: Initial Version

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 4 of 92 GENERAL DESCRIPTION The ADAU1442/ADAU1445/ADAU1446 are enhanced audio processors that allow full flexibility in routing all input and output signals. The SigmaDSP® core features full 28-bit processing (56-bit in double-precision mode), synchronous parameter loading for ensuring filter stability, and 100% code efficiency with the SigmaStudio™ tools. This DSP allows system designers to compensate for the real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression, limiting, and third-party branded algorithms. The flexible audio routing matrix (FARM) allows the user to multiplex inputs from multiple sources running at various sample rates to or from the SigmaDSP core. This drastically reduces the complexity of signal routing and clocking issues in the audio system. FARM includes up to eight stereo asynchronous sample rate converters (depending on the device model), Sony/ Philips Digital Interconnect Format (S/PDIF) input and output, and serial (I 2S) and time division multiplexing (TDM) I/Os. Any of these inputs can be routed to the SigmaDSP core or to any of the asynchronous sample rate converters (ASRCs). Similarly, any one of the output signals can be taken from the SigmaDSP core or from any of the ASRC outputs. This routing scheme, which can be modified at any time via control registers, allows for maximum system flexibility. The ADAU1442, ADAU1445, and ADAU1446 differ only in ASRC functionality and packaging. The ADAU1442/ADAU1445 contain 16 channels of ASRCs and are packaged in TQFP packages, whereas the ADAU1446 contains no ASRCs and is packaged in an LQFP . The ADAU1442 can handle nine clock domains, the ADAU1445 can handle three clock domains, and the ADAU1446 can handle one clock domain. The ADAU1442/ADAU1445/ADAU1446 can be controlled in one of two operational modes: the settings of the chip can be loaded and dynamically updated through the SPI/I 2C® port, or the DSP can self-boot from an external EEPROM in a system with no microcontroller. There is also a bank of multipurpose (MP) pins that can be used as general-purpose digital I/Os or as inputs to the 4-channel auxiliary control ADC. The ADAU1442/ADAU1445/ADAU1446 are supported by the SigmaStudio graphical development environment. This software includes audio processing blocks such as FIR and IIR filters, dynamics processors, mixers, low level DSP functions, and third-party algorithms for fast development of custom signal flows. Table 1. Device ASRC Channels ASRC Clock Domains Package ADAU1442 16 8 TQFP ADAU1445 16 2 TQFP ADAU1446 0 N/A LQFP

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 5 of 92 SPECIFICATIONS I/O pins set to 2 mA drive setting, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ANALOG PERFORMANCE AVDD = 3.3 V ± 10%. Auxiliary Analog Inputs Resolution 10 Bits Full-Scale Analog Input AVDD V Integral Nonlinearity (INL) −2.3 +2.3 LSB Differential Nonlinearity (DNL) −2.0 +2.0 LSB Gain Error −2.0 +2.0 LSB Input Impedance 200 kΩ Sample Rate fCORE/896 kHz 4:1 multiplexed input, each channel at fCORE/3584. For fCORE = 172.032 MHz, each channel is sampled at 48 kHz. POWER Supply Voltage Analog Voltage (AVDD) 2.97 3.3 3.63 V Digital Voltage (DVDD) 1.62 1.8 1.98 V PLL Voltage (PVDD) 2.97 3.3 3.63 V IOVDD Voltage (IOVDD) 2.97 3.3 3.63 V Supply Current Analog Current (AVDD) 2 mA PLL Current (PVDD) 10 mA I/O Current (IOVDD) 10 mA Depends greatly on the num- ber of active serial ports, clock pins, and characteristics of external loads. Digital Current (DVDD) ADAU1442 Typical Program 335 mA Test program includes 16 channels I/O, 10-band EQ per channel, all ASRCs active. Minimal Program 115 mA Test program includes 2 channels I/O, 10-band EQ per channel. ADAU1445 Typical Program 270 mA Test program includes 16 channels I/O, 10-band EQ per channel, all ASRCs active. Minimal Program 115 mA Test program includes 2 channels I/O, 10-band EQ per channel. ADAU1446 Typical Program 135 mA Test program includes 16 channels I/O, 10-band EQ per channel, all ASRCs active. Minimal Program 110 Test program includes 2 channels I/O, 10-band EQ per channel. ASYNCHRONOUS SAMPLE RATE CONVERTERS1 Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz. I/O Sample Rate 6 192 kHz

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 6 of 92 Parameter Min Typ Max Unit Test Conditions/Comments I/O Sample Rate Ratio 1:8 7.75:1 THD + N −133 −120 dB CRYSTAL OSCILLATOR Transconductance 40 mS REGULATOR2 DVDD Voltage 1.65 1.75 1.85 V Maximum 500 mA load. 1 To calculate the group delay, refer to the SRC Group Delay section. 2 Regulator specifications are calculated using an NJT4030P transistor from On Semiconductor in the circuit. core clock fCORE = 172.032 MHz, I/O pins set to 2 mA drive setting, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments ANALOG PERFORMANCE AVDD = 3.3 V ± 10%. Auxiliary Analog Inputs Resolution 10 Bits Full-Scale Analog Input AVDD V Integral Nonlinearity (INL) −2.3 +2.3 LSB Differential Nonlinearity (DNL) −2.0 +2.0 LSB Gain Error −2.0 +2.0 LSB Input Impedance 200 kΩ Sample Rate fCORE/896 kHz 4:1 multiplexed input, each channel at fCORE/3584. For fCORE = 172.032 MHz, each channel is sampled at 48 kHz. DIGITAL I/O Input Voltage, High (VIH) 0.7 × IOVDD V Digital input pins except SPDIFI. Input Voltage, Low (VIL) 0.3 × IOVDD V Digital input pins except SPDIFI.1 Input Leakage, High (IIH) at 3.3 V −2 +2 μA Digital input pins except MCLK and SPDIFI. −2 +8 μA MCLK. 60 140 μA SPDIFI. Input Leakage, Low (IIL) at 0 V −85 −10 μA All other pins. −2 +2 μA CLKMODEx, RSVD, PLLx, RESET. −8 +2 μA MCLK. −140 −60 μA SPDIFI. High Level Output Voltage (VOH) 0.85 × IOVDD V IOH = 1 mA. Low Level Output Voltage (VOL) 0.1 × IOVDD V IOL = 1 mA. Input Capacitance (CI) 5 pF Guaranteed by design. Multipurpose Pins Output Drive 2 mA These pins are not designed for static current draw and should not drive LEDs directly. POWER Supply Voltage Analog Voltage (AVDD) 2.97 3.3 3.63 V Digital Voltage (DVDD) 1.62 1.8 1.98 V PLL Voltage (PVDD) 2.97 3.3 3.63 V IOVDD Voltage (IOVDD) 2.97 3.3 3.63 V Supply Current Analog Current (AVDD) 2 mA

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 7 of 92 Parameter Min Typ Max Unit Test Conditions/Comments PLL Current (PVDD) 10 mA I/O Current (IOVDD) 10 mA Depends greatly on the num- ber of active serial ports, clock pins, and characteristics of external loads. Maximum Digital Current (DVDD) ADAU1442 460 mA Test program includes 24 channels I/O, fully utilized program RAM. ADAU1445 365 mA Test program includes 24 channels I/O, fully utilized program RAM. ADAU1446 315 mA Test program includes 24 channels I/O, fully utilized program RAM. Power Dissipation AVDD, DVDD, PVDD During Operation of ADAU1442 960 mW All supplies at nominal +10%, IOVDD is not included in measurement. AVDD, DVDD, PVDD During Operation of ADAU1445 780 mW All supplies at nominal +10%, IOVDD is not included in measurement. AVDD, DVDD, PVDD During Operation of ADAU1446 675 mW All supplies at nominal +10%, IOVDD is not included in measurement. Reset, All Supplies 94 mW ASYNCHRONOUS SAMPLE RATE CONVERTERS2 Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz. I/O Sample Rate 6 192 kHz I/O Sample Rate Ratio 1:8 7.75:1 THD + N −133 −120 dB CRYSTAL OSCILLATOR Transconductance 40 mS REGULATOR3 DVDD Voltage 1.65 1.75 1.85 V Maximum 500 mA load. 1 SPDIFI input voltage range exceeds the requirements of the S/PDIF specification. 2 To calculate the group delay, refer to the SRC Group Delay section. 3 Regulator specifications are calculated using an NJT4030P transistor from On Semiconductor in the circuit.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 8 of 92 DIGITAL TIMING SPECIFICATIONS TA = −40°C to +105°C, DVDD = 1.8 V , IOVDD = 3.3 V . Table 4. Parameter1 Min Max Unit Description MASTER CLOCK fMP 2.822 24.576 MHz Master clock (MCLK) frequency. See the Master Clock and PLL section. tMP 40.69 354.36 ns Master clock (MCLK) period. See the Master Clock and PLL section. tMD 25 75 % Master clock (MCLK) duty cycle. CLKOUT Jitter 250 ps Cycle-to-cycle rms average. CORE CLOCK fCORE 172.032 MHz DSP core clock frequency. SERIAL PORT fBCLK 24.576 MHz BCLK frequency. tBCLK 40.69 ns BCLK period. tBIL 30 ns BCLKx low pulse width, slave mode. tBIH 30 ns BCLKx high pulse width, slave mode. tLIS 20 ns LRCLKx setup to BCLKx input rising edge, slave mode. tLIH 20 ns LRCLKx hold from BCLKx input rising edge, slave mode. tSIS 10 ns SDATA_INx setup to BCLKx input rising edge. tSIH 10 ns SDATA_INx hold from BCLKx input rising edge. tTS 5 ns BCLKx output falling edge to LRCLKx output timing skew. tSODS 30 ns SDATA_OUTx delay in slave mode from BCLKx output falling edge. tSODM 30 ns SDATA_OUTx delay in master mode from BCLKx output falling edge. SPI PORT fCCLK write 32 MHz CCLK frequency.2 fCCLK read 16 MHz CCLK frequency.2 tCCPL 20 ns CCLK pulse width low. tCCPH 20 ns CCLK pulse width high. tCLS 0 ns CLATCH setup to CCLK rising edge. tCLH 35 ns CLATCH hold from CCLK rising edge. tCLPH 20 ns CLATCH pulse width high. tCLDLY 20 ns Minimum delay between CLATCH low pulses. tCDS 0 ns CDATA setup to CCLK rising edge. tCDH 35 ns CDATA hold from CCLK rising edge. tCOV 40 ns COUT valid output delay from CCLK falling edge. I2C PORT fSCL 400 kHz SCL clock frequency. tSCLH 0.6 μs SCL pulse width high. tSCLL 1.3 μs SCL pulse width low. tSCS 0.6 μs Start and repeated start condition setup time. tSCH 0.6 μs Start condition hold time. tDS 100 ns Data setup time. tDH 0.9 μs Data hold time. tSCLR 300 ns SCL rise time. tSCLF 300 ns SCL fall time. tSDR 300 ns SDA rise time. tSDF 300 ns SDA fall time. tBFT 1.3 μs Bus-free time between stop and start. MULTIPURPOSE PINS AND RESET fMP fS/2 Hz MPx maximum switching rate. tMPIL 1.5 × 1/fS,NORMAL μs MPx pin input latency until high/low value is read by core. Guaranteed by design. tRLPW 10 ns RESET low pulse width. 1 All timing specifications are given for the default (I2S) states of the serial audio input ports and the serial audio output ports (see Table 26 and Table 30). 2 Maximum SPI CCLK clock frequency is dependent on current drive strength and capacitive loads on the circuit board.

soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance

1. THE EXPOSED PAD DOES NOT HAVE AN INTERNAL ELECTRICAL CONNECTION TO THE INTEGRATED CIRCUIT,

BUT SHOULD BE CONNECTED TO THE GROUND PLANE OF THE PCB FOR PROPER HEAT DISSIPATION. Figure 7. Pin Configuration Table 7. Pin Function Descriptions ground plane. DGND pins should be decoupled to a DVDD pin with a 100 nF capacitor. pin is variable because it is dependent on the loads of the digital outputs. 5 SDATA_IN2 D_IN Serial Data Port 2 Input. When not used, this pin can be left disconnected.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 13 of 92 Pin No. Mnemonic Type1 Description 6 BCLK2 D_IO Bit Clock, Input Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. 7 LRCLK2 D_IO Frame Clock, Input Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. 8 SDATA_IN1 D_IN Serial Data Port 1 Input. When not used, this pin can be left disconnected. 9 BCLK1 D_IO Bit Clock, Input Clock Domain 1. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 1 is set up as a master or slave. When not used, this pin can be left disconnected. 10 LRCLK1 D_IO Frame Clock, Input Clock Domain 1. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 1 is set up as a master or slave. When not used, this pin can be left disconnected. 11 SDATA_IN0 D_IN Serial Data Port 0 Input. When not used, this pin can be left disconnected. 12 BCLK0 D_IO Bit Clock, Input Clock Domain 0. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 0 is set up as a master or slave. When not used, this pin can be left disconnected. 15 LRCLK0 D_IO Frame Clock, Input Clock Domain 0. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 0 is set up as a master or slave. When not used, this pin can be left disconnected. 16 MP11 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 17 MP10 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 18 MP9 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 19 MP8 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 20 ADDR0 D_IN Address 0 for I2C and SPI. In I2C mode, this pin, in combination with ADDR1, allows up to four ADAU1442/ADAU1445/ADAU1446 devices to be used on the same I2C bus. In SPI mode, setting ADDR0 either low or high allows up to two ICs to be used with a common SPI latch signal. 21 CLATCH D_IN SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction may take a different number of CCLK cycles to complete, depending on the address and read/write bits that are sent at the beginning of the SPI transaction. When not used, this pin should be tied to ground, preferably with a 10 kΩ pull-down resistor. 22 SCL/CCLK D_IN Serial Clock/Continuous Clock. In I2C mode, this pin functions as SCL and is always an open collector input, except when in self-boot mode, where it is an open collector output (I2C master). The line connected to this pin should have a 2.0 kΩ pull-up resistor. In SPI mode, this pin functions as CCLK and is an input pin that can be either run continuously or gated off between SPI transactions. 23 SDA/COUT D_IO Serial Data/Continuous Output. In I2C mode, this pin functions as SDA and is a bidirectional open collector. The line connected to the SDA pin should have a 2.0 kΩ pull-up resistor. In SPI mode, this pin functions as COUT and is used for reading back registers and memory locations. The COUT pin is three-stated when an SPI read is not active. 24 ADDR1/CDATA D_IN Address 1/Continuous Data. In I2C mode, this pin functions as ADDR1 and, in combination with ADDR0, sets the I2C address of the IC. This allows up to four ADAU1442/ADAU1445/ADAU1446 devices to be used on the same I2C bus. In SPI mode, this pin functions as CDATA and is the SPI data input. 25, 37, 50, 75, 87, 100 DVDD PWR 1.8 V Digital Supply. This can be supplied externally or generated from a 3.3 V supply with the on-board 1.8 V regulator. Each DVDD pin should be decoupled to DGND with a 100 nF capacitor. 28 SELFBOOT D_IN Self-Boot Select. Allows the ADAU1442/ADAU1445/ADAU1446 to be controlled by the control port or to perform a self-boot. Setting this pin high (that is, to 1) initiates a self-boot operation when the ADAU1442/ADAU1445/ADAU1446 are brought out of a reset. This pin can be tied directly to a voltage source or ground or pulled up/down with a resistor. 29 CLKMODE1 D_IN Output Clock Mode 1. With CLKMODE0, this pin sets the frequency of the CLKOUT signal. 30 CLKMODE0 D_IN Output Clock Mode 0. With CLKMODE1, this pin sets the frequency of the CLKOUT signal. 31 RSVD D_IN Reserved. Tie this pin to ground, preferably with a 10 kΩ pull-down resistor. 32 PLL2 D_IN PLL Mode Select Pin 2. 33 MP7 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 14 of 92 Pin No. Mnemonic Type1 Description 34 MP6 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 35 MP5 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 36 MP4 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 40 VDRIVE A_OUT Regulator Drive. Supplies the drive current for the 1.8 V regulator. The base of the voltage regulator’s external PNP transistor is driven from VDRIVE. 41 XTALO A_OUT Crystal Oscillator Output. A 100 Ω damping resistor should be connected between this pin and the crystal. This output should not be used to directly drive a clock to another IC; the CLKOUT pin exists for this purpose. If the crystal oscillator is not used, the XTALO pin can be left unconnected. 42 XTALI A_IN Crystal Oscillator Input. This pin provides the master clock for the ADAU1442/ADAU1445/ADAU1446. If the ADAU1442/ADAU1445/ADAU1446 generate the master clock in the system, this pin should be connected to the crystal oscillator circuit. If the ADAU1442/ADAU1445/ADAU1446 are slaves to an external master clock, this pin should be connected to the master clock signal generated by another IC. 43 PLL_FILT A_OUT Phase-Locked Loop Filter. Two capacitors and a resistor must be connected to this pin as shown in Figure 11. 44 PVDD PWR Phase-Locked Loop Supply. Provides the 3.3 V power supply for the PLL. This should be decoupled to PGND with a100 nF capacitor. 45 PGND PWR Phase-Locked Loop Ground. Ground for the PLL supply. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor. 46 SPDIFI D_IN S/PDIF Input. Accepts digital audio data in the S/PDIF format. When not used, this pin can be left disconnected. 47 SPDIFO D_OUT S/PDIF Output. Outputs digital audio data in the S/PDIF format. When not used, this pin can be left disconnected. 48 AVDD PWR Analog Supply. 3.3 V analog supply for the auxiliary ADC. This pin should be decoupled to AGND with a 100 nF capacitor. 49 AGND PWR Analog Ground. Ground for the analog supply. This pin should be decoupled to AVDD with a 100 nF capacitor. 53 CLKOUT D_OUT Master Clock Output. Used to output a master clock to other ICs in the system. Set using the CLKMODEx pins. When not used, this pin can be left disconnected. 54 RESET D_IN Reset. Active-low reset input. Reset is triggered on a high-to-low edge and exited on a low-to-high edge. For detailed information about initialization, see the Power-Up Sequence section. A reset event sets all RAMs and registers to their default values.

55 MP3/ADC3 D_IO,

A_IN Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 3. When not used, this pin can be left disconnected.

56 MP2/ADC2 D_IO,

A_IN Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 2. When not used, this pin can be left disconnected.

57 MP1/ADC1 D_IO,

A_IN Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 1. When not used, this pin can be left disconnected.

58 MP0/ADC0 D_IO,

A_IN Multipurpose, General-Purpose IO/Auxiliary ADC Input 0. When not used, this pin can be left disconnected. 59 PLL1 D_IN Phase-Locked Loop Mode Select Pin 1. 60 PLL0 D_IN Phase-Locked Loop Mode Select Pin 0. 61 SDATA_OUT8 D_OUT Serial Data Port 0 Output. When not used, this pin can be left disconnected. 64 BCLK11 D_IO Bit Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. 65 LRCLK11 D_IO Frame Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 15 of 92 Pin No. Mnemonic Type1 Description 66 SDATA_OUT7 D_OUT Serial Data Port 7 Output. When not used, this pin can be left disconnected. 67 BCLK10 D_IO Bit Clock, Output Clock Domain 10. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 10 is set up as a master or slave. When not used, this pin can be left disconnected. 68 LRCLK10 D_IO Frame Clock, Output Clock Domain 10. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 10 is set up as a master or slave. When not used, this pin can be left disconnected. 69 SDATA_OUT6 D_OUT Serial Data Port 6 Output. When not used, this pin can be left disconnected. 70 BCLK9 D_IO Bit Clock, Output Clock Domain 9. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 9 is set up as a master or slave. When not used, this pin can be left disconnected. 71 LRCLK9 D_IO Frame Clock, Output Clock Domain 9. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 9 is set up as a master or slave. When not used, this pin can be left disconnected. 72 SDATA_OUT5 D_OUT Serial Data Port 5 Output. When not used, this pin can be left disconnected. 73 SDATA_IN8 D_IN Serial Data Port 8 Input. When not used, this pin can be left disconnected. 74 BCLK8 D_IO Bit Clock, Input/Output Clock Domain 8. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 8 is set up as a master or slave. When not used, this pin can be left disconnected. 78 LRCLK8 D_IO Frame Clock, Input/Output Clock Domain 8. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 8 is set up as a master or slave. When not used, this pin can be left disconnected. 79 SDATA_OUT4 D_OUT Serial Data Port 4 Output. When not used, this pin can be left disconnected. 80 SDATA_IN7 D_IN Serial Data Port 7 Input. When not used, this pin can be left disconnected. 81 BCLK7 D_IO Bit Clock, Input/Output Clock Domain 7. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 7 is set up as a master or slave. When not used, this pin can be left disconnected. 82 LRCLK7 D_IO Frame Clock, Input/Output Clock Domain 7. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 7 is set up as a master or slave. When not used, this pin can be left disconnected. 83 SDATA_OUT3 D_OUT Serial Data Port 3 Output. When not used, this pin can be left disconnected. 84 SDATA_IN6 D_IN Serial Data Port 6 Input. When not used, this pin can be left disconnected. 85 BCLK6 D_IO Bit Clock, Input/Output Clock Domain 6. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 6 is set up as a master or slave. When not used, this pin can be left disconnected. 86 LRCLK6 D_IO Frame Clock, Input/Output Clock Domain 6. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 6 is set up as a master or slave. When not used, this pin can be left disconnected. 90 SDATA_OUT2 D_OUT Serial Data Port 2 Output. When not used, this pin can be left disconnected. 91 SDATA_IN5 D_IN Serial Data Port 5 Input. When not used, this pin can be left disconnected. 92 BCLK5 D_IO Bit Clock, Input/Output Clock Domain 5. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 5 is set up as a master or slave. When not used, this pin can be left disconnected. 93 LRCLK5 D_IO Frame Clock, Input/Output Clock Domain 5. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 5 is set up as a master or slave. When not used, this pin can be left disconnected. 94 SDATA_OUT1 D_OUT Serial Data Port 1 Output. When not used, this pin can be left disconnected. 95 SDATA_IN4 D_IN Serial Data Port 4 Input. When not used, this pin can be left disconnected.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 16 of 92 Pin No. Mnemonic Type1 Description 96 BCLK4 D_IO Bit Clock, Input/Output Clock Domain 4. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 4 is set up as a master or slave. When not used, this pin can be left disconnected. 97 LRCLK4 D_IO Frame Clock, Input/Output Clock Domain 4. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 4 is set up as a master or slave. When not used, this pin can be left disconnected. 98 SDATA_OUT0 D_OUT Serial Data Port 0 Output. When not used, this pin can be left disconnected. 99 SDATA_IN3 D_IN Serial Data Port 3 Output. When not used, this pin can be left disconnected. 1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_OUT = digital output, D_IO = digital input/output.

SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS. Figure 8. System Block Diagram

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 18 of 92 OVERVIEW The ADAU1442/ADAU1445/ADAU1446 are each a 24-channel audio DSP with an integrated S/PDIF receiver and transmitter, flexible serial audio ports, up to 16 channels of asynchronous sample rate converters (ASRCs), flexible audio routing, and user interface capabilities. Signal processing capabilities include equalization, crossover, bass enhancement, multiband dynamics processing, delay compensation, speaker compensation, and stereo image widening. These algorithms can be used to compensate for the real-world limitations of speakers, amplifiers, and listening environments, resulting in an improvement in the perceived audio quality. An on-board oscillator can be connected to an external crystal to generate the master clock. A phase-locked loop (PLL) allows the ADAU1442/ADAU1445/ADAU1446 to be clocked from a variety of clock frequencies. The PLL can accept inputs of 64 × f S, 128 × fS, 256 × fS, 384 × fS, or 512 × fS to generate the internal master clock of the core, where fS is the sampling rate of audio in normal-rate pro- cessing mode. In dual- or quad-rate mode, these multipliers are halved or quartered, respectively. System sample rates include, but are not limited to, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz. Each ADAU1442/ADAU1445/ADAU1446 operates from a 1.8 V digital power supply and a 3.3 V analog supply. An on-board voltage regulator can be used to operate the chip from a single 3.3 V supply. The ADAU1442/ADAU1445/ADAU1446 have a sophisticated control port that supports complete read and write capability of all memory locations, excluding read-only addresses. Control registers are provided to offer complete control of the chip’s configuration and serial modes. Handshaking is included for ease of memory uploads and downloads. The ADAU1442/ ADAU1445/ADAU1446 can be configured for either SPI or I control. Program RAM, parameter RAM, and register contents can be saved in an external EEPROM, from which the ADAU1442/ ADAU1445/ADAU1446 can self-boot on startup. The ADAU1442/ADAU1445/ADAU1446 serial ports operate with digital audio I/Os in the I 2S, left-justified, right-justified, or TDM- compatible mode. The flexible serial data ports allow for direct interconnection to a variety of ADCs, DACs, and general-purpose DSPs. The combination of an on-board S/PDIF transmitter and receiver and 16 channels of ASRCs allows for easy compatibility with an extensive number of external devices, and a system with up to nine sampling rates. The flexible audio routing matrix (FARM) is a system of multi- plexers used to distribute the audio signals in the ADAU1442/ ADAU1445/ADAU1446 among the serial inputs and outputs, audio core, and ASRCs. FARM can easily be configured by setting the appropriate registers. The ADAU1442, ADAU1445, and ADAU1446 are distinguished by the number of on-board ASRCs and maximum sample rates. The ADAU1442 contains eight 2-channel ASRCs, the ADAU1445 contains two 8-channel ASRCs, and the ADAU1446 has no ASRCs. Two sets of serial ports at the input and output can operate in a special flexible TDM mode, which allows the user to independently assign byte-specific locations to audio streams at varying bit depths. This mode ensures compatibility with codecs using similar flexible TDM streams. The core of the ADAU1442/ADAU1445/ADAU1446 is a 28-bit DSP (or a 56-bit DSP when using double-precision mode) optimized for audio processing, and it can process audio at sample rates of up to 192 kHz. The program and parameter RAMs can be loaded with a custom audio processing signal flow built with the SigmaStudio graphical programming software from Analog Devices, Inc. The values stored in the parameter RAM control individual signal processing blocks, such as IIR and FIR equalization filters, dynamics processors, audio delays, and mixer levels. A software safeload feature allows for transparent parameter updates and prevents clicks on the output signals. Reliability features such as a CRC and program counter watchdog help ensure that the system can detect and recover from any errors related to memory corruption. S/PDIF signals can be routed through an ASRC for processing in the DSP or can be sent directly to output on MP pins for recovery of the embedded audio signal. Other components of the embedded signal, including status and user bits, are not lost and can be output on the MP pins as well. Multipurpose (MP) pins are available for providing a simple user interface without the need for an external microcontroller. Twelve pins are available to input external control signals and output flags or controls to other devices in the system. Four of these can alternatively be assigned to an auxiliary ADC for use with analog controls such as potentiometers or system voltages. As inputs, MP pins can be connected to push buttons, switches, rotary encoders, potentiometers, or other external control circuitry to control the internal signal processing program. When con- figured as outputs, these pins can be used to drive LEDs (with a buffer), to output flags to a microcontroller, to control other ICs, or to connect to other external circuitry in an application. The SigmaStudio software is used to program and control the ADAU1442/ADAU1445/ADAU1446 through the control port. Along with designing and tuning a signal flow, the software can configure all of the DSP registers in real time and download a new program and parameter into the external self-boot EEPROM. SigmaStudio’s easy-to-use graphical interface allows anyone with audio processing knowledge to easily design a DSP signal flow and port it to a target application without the need for writing line-level code. At the same time, the software provides enough flexibility and programmability for an experienced DSP programmer to have in-depth control of the design. In SigmaStudio, the user can add signal processing cells from the library by dragging and dropping cells, connect them together in a flow, compile the design, and load the program and parameter files into the ADAU1442/ADAU1445/ ADAU1446 memory through the control port. The complicated tasks of linking, compiling, and downloading the project are all handled automatically by the software.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 19 of 92 Signal processing algorithms available in the provided libraries include

• Single- and double-precision biquad filter
• Mono and multichannel dynamics processors with peak or rms detection
• Mixer and splitter
• Tone and noise generator
• Fixed and variable gain
• Loudness
• Delay
• Stereo enhancement
• Dynamic bass boost
• Noise and tone source
• Level detector
• MP pin control and conditioning New processing algorithms are always being developed. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices for information about licensing these algorithms. Several power-saving mechanisms have been designed into the ADAU1442/ADAU1445/ADAU1446, including programmable pad strength for digital I/O pins and the ability to block the master clock from reaching unused subsystems. The ADAU1442/ADAU1445/ADAU1446 are fabricated on a single monolithic integrated circuit for operation over the −40°C to +105°C temperature range. The ADAU1442 and ADAU1445 are housed in a 100-lead TQFP package, with an exposed pad to assist in heat dissipation, and the ADAU1446, due to its lower power consumption, is housed in a 100-lead LQFP package.

pins. The PLL divider settings are described in Table 9.

12.288 MHz and the PLL divider is set to 4 (PLL = 0, PLL1 = 1,

initialized; therefore, the total boot time may be shorter. turned on and off as needed to reduce power consumption. the Master Clock and PLL Modes and Settings section.

1. Power on the IC and bring it out of reset. The order of the

power supplies (DVDD, IOVDD, and AVDD) does not matter.

1. Wait at least 10.667 ms for the initialization to complete if the
2. Enable the master clocks of all modules to be used (see the

Master Clock and PLL Modes and Settings section).

1. Set the DSP core rate select register (0xE220) to 0x001C.

This disables the start pulse to the core.

1. Deassert the core run bit (see the DSP Core Modes and
2. Set the serial input modes (see the Serial Input Port Modes

Registers (Address 0xE000 to Address 0xE008) section).

1. Set the serial output modes (see the Serial Output Port
2. Set the routing matrix modes (see details of Address 0xE080
3. Write the parameter RAM (Address 0x0000 to Address
4. Write the program RAM (Address 0x2000 to Address
5. Write the nonmodulo data RAM (Addresses vary based on

the SigmaStudio project file).

1. Write all other necessary control registers, such as ASRCs

and S/PDIF (Address 0xE221 to Address 0xE24C).

1. Set the DSP core rate select register (0xE220) to the desired

contains a list of valid settings.

1. Assert the core run bit (see the DSP Core Modes and

Table 8. Power-Up Time

the resonant frequency of the crystal should be 64 × fS,QUAD. resonance device operating at its fundamental frequency. crystal oscillator circuit recommended for proper operation. Figure 9. Crystal Oscillator Circuit with a voltage swing of approximately 2.2 V at the XTALI pin. assumed to be approximately 2 pF to 5 pF. helping to avoid crystal start-up problems. the capacitance value for C1 and C2 is 22 pF . without also resetting the ADAU1442/ADAU1445/ADAU1446. changed while RESET is held low. though it may be lower in some applications.

Table 9. PLL Modes then fS,DUAL is 96 kHz and fS,QUAD is 192 kHz. 2 The PLL divider is set by the PLLx pins. Figure 10. Master Clock Signal Flow

in the schematic can be connected to the PVDD supply of the chip. Figure 11. PLL Loop Filter pins must be set (see Table 10). Table 10. CLKOUT Modes determines the sample rate of signals processed inside the core. the core clock is 896 × fS,QUAD. set this register may compromise future register writes. Table 11. Bit Descriptions of Register 0xE280

8 Enable MCLK to auxiliary ADCs 0

7 Enable MCLK to S/PDIF transmitter 0

6 Enable MCLK to S/PDIF receiver 0

5 Enable MCLK to DSP core 0

4 Enable MCLK to Stereo ASRC[7:4]2 0

3 Enable MCLK to Stereo ASRC[3:0]2 0

2 Enable MCLK to serial outputs 0

1 Enable MCLK to serial inputs 0

0 Enable MCLK to flexible audio routing

2 See the Flexible Audio Routing Matrix—Input Side section for more information.

Table 12. Bit Descriptions of Register 0xE220 used by any of the serial ports or S/PDIF receiver.

Figure 12. Voltage Regulator Design where GDS is the group delay in seconds.

cation). A data transfer is always terminated by a stop condition. or a single stop condition followed by a single start condition. Figure 15 shows the sequence of a single-word write operation. issue an acknowledge by pulling SDA low. Figure 16 shows the sequence of a burst mode write operation. register or memory area with a 2-byte word length. Figure 17. Note that, even though this is a read operation, the the subaddress must be written to set up the internal address. Figure 18 shows the sequence of a burst mode read operation. appropriate number of bytes.

111 ADR

Figure 13. I2C Write Clocking

ADAU1446 cannot self-boot in SPI mode. the settings on them are ignored. discrete message is one of the four types defined in Table 17. program RAM, parameter RAM, and control registers. ADAU1446 IC in the hardware configuration window. Table 16. Functions of the Control Port Pins Table 17. EEPROM Message Types

port modes and serial input port modes control registers. converter to be processed in the core. a 50/50 duty cycle clock or as a bit-wide pulse. ADAU1445/ADAU1446 in master mode is limited to 25 MHz. port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but are truncated internally. clock domain corresponding to their channel number. Table 18. Serial Input and Output Port TDM Capabilities 1 The device will not work in this mode. are used to output data from the SigmaDSP to the external DAC.

Table 19. Configurations for Standard Audio Data Formats

0 TO 2 3 TO 8

9 TO 11BCLK9/LRCLK9

Figure 21. Overview of Serial Data Input/Output Ports

Figure 22 to Figure 26 show timing diagrams for standard audio data formats. Figure 22. I2S Mode—16 Bits to 24 Bits per Channel Figure 23. Left-Justified Mode—16 Bits to 24 Bits per Channel Figure 24. Right-Justified Mode—16 Bits to 24 Bits per Channel

32 BCLKs

256 BCLKs

Figure 25. TDM Mode Figure 26. TDM Mode with Pulse Frame Clock

remaining six can be assigned to clock either input or output ports. domains contain a total of 24 clock signals. and BCLK pins output clock signals to external slave ICs. (see Table 20 for more details). Table 20. Master Mode Clock Domain Assignment

0 LRCLK0, BCLK0 SDATA_IN0

1 LRCLK1, BCLK1 SDATA_IN1

2 LRCLK2, BCLK2 SDATA_IN2

3 LRCLK3, BCLK3 SDATA_IN3 or SDATA_OUT31

4 LRCLK4, BCLK4 SDATA_IN4 or SDATA_OUT41

5 LRCLK5, BCLK5 SDATA_IN5 or SDATA_OUT51

6 LRCLK6, BCLK6 SDATA_IN6 or SDATA_OUT61

7 LRCLK7, BCLK7 SDATA_IN7 or SDATA_OUT71

8 LRCLK8, BCLK8 SDATA_IN8 or SDATA_OUT81

9 LRCLK9, BCLK9 SDATA_OUT0

10 LRCLK10, BCLK10 SDATA_OUT1

11 LRCLK11, BCLK11 SDATA_OUT2

1 Depends on the setting of the clock pad multiplexer register (Address 0xE240).

0 TO 2 3 TO 8 9 TO 11MASTER/SLAVE

Figure 27. Simplified Serial Clock Domain Assignment

Table 21. Bit Descriptions of Register 0xE221 pulses coming from the serial ports in slave mode. Table 22. Bit Descriptions of Register 0xE240

5 Clock Domain 8 0

4 Clock Domain 7 0

3 Clock Domain 6 0

2 Clock Domain 5 0

1 Clock Domain 4 0

0 Clock Domain 3 0

1 0 = input clock domain, 1 = output clock domain. corresponds with an output clock domain. Figure 28. Clock Pad Multiplexer

• Packed TDM4 mode
• Left-justified or delay by 1
• Word length of 16 bits See Figure 29 for a timing diagram of the packed TDM4 mode. This figure is shown with a negative BCLK polarity, a negative LRCLK polarity, and an MSB delay of 1. LRCLKx (1 PERIOD) BCLKx (64 PERIODS) SDATA_INx, SDATA_OUTx (4 CHANNELS)

16 BITS16 BITS 16 BITS 16 BITS

Figure 29. Packed TDM4 Mode

16-, 20-, and 24-bit audio signals for input to the audio processor. to drive in master mode or to be driven in slave mode. signals (SDATA_IN0 to SDATA_IN8). multiplexed to Clock Domains[8:3] as either inputs or outputs. configuration is also valid in master mode. respects this (for example, two TDM16 streams is not a valid entry). Table 23. Input Clock Domain Multiplexing

0 LRCLK0, BCLK0 N/A

1 LRCLK1, BCLK1 N/A

2 LRCLK2, BCLK2 N/A

3 LRCLK3, BCLK3 Set Bit 0 to 0

4 LRCLK4, BCLK4 Set Bit 1 to 0

5 LRCLK5, BCLK5 Set Bit 2 to 0

6 LRCLK6, BCLK6 Set Bit 3 to 0

7 LRCLK7, BCLK7 Set Bit 4 to 0

8 LRCLK8, BCLK8 Set Bit 5 to 0

Table 24. Input Clock Domain Assignments in Master Mode

3 TO 8

Figure 30. Input Serial Port Clock Multiplexing

domain (that is, SDATA3 uses LRCLK3 and BCLK3). serial data can only be 16 bits wide. Table 25. Addresses of Serial Input Port Modes Registers

57344 E000 Serial Input Port 0 modes 16 bits (2 bytes)

57345 E001 Serial Input Port 1 modes 16 bits (2 bytes)

57346 E002 Serial Input Port 2 modes 16 bits (2 bytes)

57347 E003 Serial Input Port 3 modes 16 bits (2 bytes)

57348 E004 Serial Input Port 4 modes 16 bits (2 bytes)

57349 E005 Serial Input Port 5 modes 16 bits (2 bytes)

57350 E006 Serial Input Port 6 modes 16 bits (2 bytes)

57351 E007 Serial Input Port 7 modes 16 bits (2 bytes)

57352 E008 Serial Input Port 8 modes 16 bits (2 bytes)

Table 26. Bit Descriptions of Serial Input Port Modes Registers

15 Clock output enable1 0

14 Frame sync type 0

9 Serial input BCLK polarity 0

8 Serial input LRCLK polarity 0

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 40 of 92 Bit Position Description Default [7:6] Word length 00 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = flexible TDM mode3 [5:3] MSB position 000 000 = I2S (delayed by 1) 001 = left justified (delayed by 0) 010 = delayed by 8 011 = delayed by 12 100 = delayed by 16 [2:0] TDM type 000 000 = TDM2 (stereo) 001 = TDM4 010 = TDM8 or flexible TDM mode3 011 = TDM16 100 = packed TDM4 1 Bit 15 and Bits[13:10] must be used in conjunction to set the port as a master or slave. 2 The default depends on the address: 0xE000 = 0001, 0xE001 = 0010, 0xE002 = 0011, 0xE003 = 0100, 0xE004 = 0101, 0xE005 = 0110, 0xE006 = 0111, 0xE007 = 1000, and 0xE008 = 1001. 3 To activate flexible TDM mode, both Bits[7:6] and Bits[2:0] must be set. Clock Output Enable Bit (Bit 15) This bit controls the serial port’s respective bit clock as well as the left and right clocks. When this bit is set to 1, the clock pins are set to output. When this bit is set to 0, the clock pins are not output clocks. In Register 0xE000 to Register 0xE008, Bit 15 and Bits[13:10] must be used in conjunction to set the port as a master or slave. Clock domains are assigned to input or output serial ports with the clock pad multiplexer register (Address 0xE240). For more information, see the Clock Pad Multiplexer section. Frame Sync Type Bit (Bit 14) This bit sets the type of LRCLK signal that is used. When this bit is set to 0, the clock signal is a square wave. When this bit is set to 1, the signal is a narrow pulse. Clock Domain Master/Slave Select Bits (Bits[13:10]) These bits determine whether the serial port outputs its clocks as a master or slave to an available clock domain. If a serial port is set to be a master, the clock output enable bit (Bit 15) must be set to 1. If a serial port is set as a slave, the clock output enable bit must be set to 0. In both cases, the corresponding clock pad multiplexer must be set to the serial input domain if it is assign- able. For more information, see the Clock Pad Multiplexer section. Note that an arbitrary number of serial ports can be slaves to a single clock domain, but a single serial port can only be a master to one clock domain. The values for f S,NORMAL, fS,DUAL, and fS,QUAD are 48 kHz, 96 kHz, and 192 kHz, respectively, for a 172.032 MHz core clock signal. Serial Input BCLK Polarity Bit (Bit 9) The polarity of BCLKx determines whether LRCLKx and SDATA_INx change on a rising (+) or falling (−) edge of the BCLKx signal. Standard I 2S signals use negative BCLK polarity. Serial Input LRCLK Polarity Bit (Bit 8) The polarity of LRCLKx determines whether the left stereo channel is initiated on a rising (+) or falling (−) edge of the LRCLKx signal. Standard I2S signals use negative LRCLK polarity.

Figure 31. Serial Input BCLK Polarity Figure 32. Serial Input LRCLK Polarity These bits set the position of the MSB in the data stream. be set for flexible TDM mode (that is, set to 010). left-justified mode); and for packed TDM4, 64 BCLK cycles. data signals (SDATA_IN0 to SDATA_IN8). are multiplexed to Clock Domains[8:3] as either inputs or outputs. configuration is also valid in master mode. Table 27. Output Clock Domain Multiplexing

0 LRCLK9, BCLK9 N/A

1 LRCLK10, BCLK10 N/A

2 LRCLK11, BCLK11 N/A

3 LRCLK3, BCLK3 Set Bit 0 to 1

4 LRCLK4, BCLK4 Set Bit 1 to 1

5 LRCLK5, BCLK5 Set Bit 2 to 1

6 LRCLK6, BCLK6 Set Bit 3 to 1

7 LRCLK7, BCLK7 Set Bit 4 to 1

8 LRCLK8, BCLK8 Set Bit 5 to 1

described in Table 28 are used. Table 28. Output Clock Domain Assignments in Master Mode and the left channel always precedes the right channel. 2S position) and the data width is restricted to 16 bits. MSB delay-by-16 mode, the serial data can only be 16 bits wide. For information on TDM capabilities, refer to Table 18. Figure 33. Output Serial Port Clock Multiplexing

Table 29. Addresses of Serial Output Port Modes Registers

57408 E040 Serial Output Port 0 modes 16 bits (2 bytes)

57409 E041 Serial Output Port 1 modes 16 bits (2 bytes)

57410 E042 Serial Output Port 2 modes 16 bits (2 bytes)

57411 E043 Serial Output Port 3 modes 16 bits (2 bytes)

57412 E044 Serial Output Port 4 modes 16 bits (2 bytes)

57413 E045 Serial Output Port 5 modes 16 bits (2 bytes)

57414 E046 Serial Output Port 6 modes 16 bits (2 bytes)

57415 E047 Serial Output Port 7 modes 16 bits (2 bytes)

57416 E048 Serial Output Port 8 modes 16 bits (2 bytes)

57417 E049 High speed slave interface mode 1 bit (2 bytes)

Table 30. Bit Descriptions of Serial Output Port Modes Registers

9 Serial output BCLK polarity 0

8 Serial output LRCLK polarity 0

1 Bit 15 and Bits[13:10] must be used in conjunction to set the port as a master or slave. 3 Excluding when the serial port is configured in flexible TDM mode, it will always output 24-bit data. 4 To activate flexible TDM mode, both Bits[7:6] and Bits[2:0] must be set.

ports with the clock pad multiplexer register (Address 0xE240). For more information, see the Clock Pad Multiplexer section. set to 1, the signal is a narrow pulse. 172.032 MHz core clock signal. BCLKx signal. Standard I2S signals use negative BCLK polarity. These bits set the position of the MSB in the data stream. also be set for flexible TDM mode (that is, set to 010). Table 31. Bit Descriptions of Register 0xE049

0 High speed slave interface mode 0

22 MHz, the high speed slave interface mode must be enabled. Figure 34. Serial Output BCLK Polarity Figure 35. Serial Output LRCLK Polarity

S/PDIF I/O, serial I/O, ASRCs, and DSP via the routing matrix. one connections can be made between any input and any output. The signal routing is fully implemented in hardware.

0 TO 2 3 TO 8 9 TO 11

Figure 36. Routing Matrix Block Diagram

ports according to the number of channels desired in the stream. For clarification, see Figure 48. to SDATA_OUT1, and Output Channels[13:10] to SDATA_OUT2. both the DSP and to the FARM output sides. outputs are not hardwired to the output channels. Figure 47. Flexible Audio Routing Matrix—Output Side

Figure 48. Automatic Output Channel Assignment Example Table 32. Addresses of Flexible Audio Routing Matrix Modes Registers

57472 E080 ASRC input select, Pair 0 (Channel 0, Channel 1) 16 bits (2 bytes)

57473 E081 ASRC input select, Pair 1 (Channel 2, Channel 3) 16 bits (2 bytes)

57474 E082 ASRC input select, Pair 2 (Channel 4, Channel 5) 16 bits (2 bytes)

57475 E083 ASRC input select, Pair 3 (Channel 6, Channel 7) 16 bits (2 bytes)

57476 E084 ASRC input select, Pair 4 (Channel 8, Channel 9) 16 bits (2 bytes)

57477 E085 ASRC input select, Pair 5 (Channel 10, Channel 11) 16 bits (2 bytes)

57478 E086 ASRC input select, Pair 6 (Channel 12, Channel 13) 16 bits (2 bytes)

57479 E087 ASRC input select, Pair 7 (Channel 14, Channel 15) 16 bits (2 bytes)

57480 E088 ASRC output rate select, Pair 0 (Channel 0, Channel 1) 16 bits (2 bytes)

57481 E089 ASRC output rate select, Pair 1 (Channel 2, Channel 3) 16 bits (2 bytes)

57482 E08A ASRC output rate select, Pair 2 (Channel 4, Channel 5) 16 bits (2 bytes)

57483 E08B ASRC output rate select, Pair 3 (Channel 6, Channel 7) 16 bits (2 bytes)

57484 E08C ASRC output rate select, Pair 4 (Channel 8, Channel 9) 16 bits (2 bytes)

57485 E08D ASRC output rate select, Pair 5 (Channel 10, Channel 11) 16 bits (2 bytes)

57486 E08E ASRC output rate select, Pair 6 (Channel 12, Channel 13) 16 bits (2 bytes)

57487 E08F ASRC output rate select, Pair 7 (Channel 14, Channel 15) 16 bits (2 bytes)

57488 E090 Serial output select, Pair 0 (Channel 0, Channel 1) 16 bits (2 bytes)

57489 E091 Serial output select, Pair 1 (Channel 2, Channel 3) 16 bits (2 bytes)

57490 E092 Serial output select, Pair 2 (Channel 4, Channel 5) 16 bits (2 bytes)

57491 E093 Serial output select, Pair 3 (Channel 6, Channel 7) 16 bits (2 bytes)

57492 E094 Serial output select, Pair 4 (Channel 8, Channel 9) 16 bits (2 bytes)

57493 E095 Serial output select, Pair 5 (Channel 10, Channel 11) 16 bits (2 bytes)

57494 E096 Serial output select, Pair 6 (Channel 12, Channel 13) 16 bits (2 bytes)

57495 E097 Serial output select, Pair 7 (Channel 14, Channel 15) 16 bits (2 bytes)

57496 E098 Serial output select, Pair 8 (Channel 16, Channel 17) 16 bits (2 bytes)

57497 E099 Serial output select, Pair 9 (Channel 18, Channel 19) 16 bits (2 bytes)

57498 E09A Serial output select, Pair 10 (Channel 20, Channel 21) 16 bits (2 bytes)

57499 E09B Serial output select, Pair 11 (Channel 22, Channel 23) 16 bits (2 bytes)

pair from either the serial input channels or the DSP core. can receive a separate data input. ASRC[7:4]) takes its input rate from Stereo ASRC 4 input. Table 33. Bit Descriptions of ASRC Input Select Pairs[7:0] Registers

outputs from FARM are the Stereo ASRC[7:0] inputs. Figure 49. ASRC Input Select

Table 34. Bit Descriptions of ASRC Output Rate Select Pairs[7:0] Registers These bits select the output conversion rate for the eight ASRCs. serial port) or by the core’s fS,NORMAL, fS,DUAL, or fS,QUAD clock signals. ASRCs can have a separate data output. for the Stereo ASRC[7:5] outputs.

Table 35. Bit Descriptions of Serial Output Select Pairs[11:0] Registers

any of the DSP serial or ASRC outputs. Figure 50. Serial Output Select Pair

the flexible audio routing matrix. Table 36. Addresses of ASRC Modes Registers

57601 E101 Stereo ASRC[3:0] lock

57603 E103 Stereo ASRC[3:0] mute

57665 E141 Stereo ASRC[7:4] lock

57667 E143 Stereo ASRC[7:4] mute

Table 37. Bit Descriptions of Register 0xE101

11 Stereo ASRC 3 (Channel 6, Channel 7)

10 Stereo ASRC 2 (Channel 4, Channel 5)

9 Stereo ASRC 1 (Channel 2, Channel 3)

8 Stereo ASRC 0 (Channel 0, Channel 1)

3 Stereo ASRC 3 (Channel 6, Channel 7) mute 0

2 Stereo ASRC 2 (Channel 4, Channel 5) mute 0

1 Stereo ASRC 1 (Channel 2, Channel 3) mute 0

0 Stereo ASRC 0 (Channel 0, Channel 1) mute 0

muted. This function is controlled by a single 12-bit register. lock bits are set to 1, and the outputs are automatically muted. ASRC will not cause its lock bit to change from 0 back to 1. affect system operation in any way. Table 38. Bit Descriptions of Register 0xE103

0 Stereo ASRC[3:0] (Channels[7:0]) mute ramp

Stereo ASRC[3:0] (Channels[7:0]) mute with a volume ramp. affect system operation in any way. Table 39. Bit Descriptions of Register 0xE141

11 Stereo ASRC 7 (Channel 14, Channel 15)

10 Stereo ASRC 6 (Channel 12, Channel 13)

9 Stereo ASRC 5 (Channel 10, Channel 11)

8 Stereo ASRC 4 (Channel 8, Channel 9)

3 Stereo ASRC 7 (Channel 14, Channel 15) mute 0

2 Stereo ASRC 6 (Channel 12, Channel 13) mute 0

1 Stereo ASRC 5 (Channel 10, Channel 11) mute 0

0 Stereo ASRC 4 (Channel 8, Channel 9) mute 0

muted. This function is controlled by a single 12-bit register. lock bits are set to 1, and the outputs are automatically muted. ASRC will not cause its lock bit to change from 0 back to 1. affect system operation in any way. Table 40. Bit Descriptions of Register 0xE143

0 Stereo ASRC[7:4] (Channels[15:8]) mute

Stereo ASRC[7:4] (Channels[15:8]) mute with a volume ramp. mute only occurs on a loss of lock. affect system operation in any way.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 60 of 92 DSP CORE The DSP core performs calculations on audio data as specified by the instruction codes stored in program RAM. Because SigmaStudio generates the instructions, it is not necessary to have a detailed knowledge of the DSP core to use the SigmaDSP , but a brief description is provided in this section. Architecture The core consists of a simple 28-/56-bit multiply-accumulate unit (MAC) with two sources: a data source and a coefficient source. The data source can come from the data RAM, a ROM table of commonly used constant values, or the audio inputs to the core. The coefficient source can come from the parameter RAM, a ROM table of commonly used constant values. The two sources are multiplied in a 28-bit fixed-point multiplier, and then the signal is input to the 56-bit adder; the result is usually stored in one of three 56-bit accumulator registers. The accumulators can be output from the core (in 28-bit format) or can optionally be written back into the data or parameter RAMs. The SigmaDSP core is designed specifically for audio processing and, therefore, includes several features intended for maximizing efficiency. These include hardware decibel conversion and audio- specific ROM constants. Signal Processing The ADAU1442/ADAU1445/ADAU1446 are designed to provide all signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is designed using SigmaStudio software from Analog Devices. This software allows graphical entry and real-time control of all signal processing functions. Many of the signal processing functions are coded using full, 56-bit, double-precision arithmetic. The serial port input and output word lengths are 24 bits, but four extra headroom bits are used in the processor to allow internal gains of up to 24 dB without clipping. Additional gains can be achieved by initially scaling down the input signal in the DSP signal flow. COEFFICIENT SOURCE (PARAMETER RAM, ROM CONSTANTS, ...) DATA OPERATIONS (ACCUMULATORS (3), dB CONVERSION, BIT OPERATORS, BIT SHIFTER, ...) DATA SOURCE (DATA RAM, ROM CONSTANTS, INPUTS, ...) OUTPUTS TRUNCATOR TRUNCATOR56 2828 07696-052 Figure 51. Simplified Core Architecture

DSP systems commonly use a standard numeric format. and B is the number of bits to the right of the decimal point. shown in the Numerical Format: 5.23 section. gains of up to 24 dB without encountering internal clipping. each point in the data flow in both binary and decibel levels. Figure 52. Numeric Precision and Clipping Structure (TBD) SigmaStudio can be found at the Analog Devices website. every time a new audio frame is clocked into the core. next audio frame to clock into the core. counter to implement simple branching and looping structures. output is corrupted, and a reset is necessary. error when a user exceeds the allowable limit. Table 41. Descriptions of Register 0xE228

0 Core run bit 0

This single-bit register initiates the run signal to start the core. (0xE220) to 0x001C. This disables the start pulse to the core. core. Table 12 contains a list of valid settings. 0) during operation, the serial outputs jump immediately to 0. minimizing pops and clicks on the outputs.

Table 42. Register Details of CRC Registers

57856 E200 CRC Ideal

16 MSBs of the

57857 E201 CRC Ideal

16 LSBs of the CRC

57858 E202 CRC enable 1-bit CRC enable,

program) and then setting it high again.

• CRC Ideal Value 1 is the 16 MSBs of the CRC code.
• CRC Ideal Value 2 is the 16 LSBs of the CRC code.
• CRC enable is a 1-bit enable. The CRC error sticky register is a single-bit read-only register at Address 57893 (Address 0xE225) that acts as the CRC error flag. It can optionally be sent to an MP pin. For example, it can connect to an interrupt pin on an external microcontroller, which triggers a rewrite of the corrupted memory. The register is reset when the CRC enable register goes low. CRC Error Sticky Register (Address 0xE225)

Table 43. Bit Description of Register 0xE225

0 CRC error sticky (read only) 0

error. It is reset to 0 when the CRC enable is reset to 0.

Table 44. Register Details of Watchdog Registers

57872 E210 Watchdog enable 1-bit enable register for watchdog timer 0

57873 E211 Watchdog Value 1 16 MSBs of the watchdog maximum count value 0

57874 E212 Watchdog Value 2 16 LSBs of the watchdog maximum count value 0

by setting the single-bit register at Location 57872 high.

• Watchdog enable is a 1-bit enable.
• Watchdog Value 1 is the 16 MSBs of the watchdog maximum count value.
• Watchdog Value 2 is the 16 LSBs of the watchdog maximum count value.

Table 45. Bit Descriptions of Register 0xE210

0 Watchdog enable 0

Table 46. Bit Descriptions of Register 0xE226

0 Watchdog error sticky (read only) 0

This single-bit watchdog error flag goes high when an error occurs. connect to an interrupt pin on a microcontroller in the system. It resets to 0 when the watchdog enable is reset to 0. Table 47. Bit Descriptions of Register 0xE227

0 A watchdog error mutes the core

automatically mute the core. The default value is off.

Table 48. Register Details of Program RAM executed in the span of a single frame for normal rate signals. with no-operation (NOP) commands. Table 49. Bit Descriptions of Register 0xE229 is reset. The register is updated on every start pulse. program counter peak value may be inaccurate. Table 50. Register Details of Parameter RAM project-specific parameters start at Address 0x0008. Table 51. Register Details of Data RAM operation is performed to avoid an undefined startup state. code into projects by default. Table 52. Bit Descriptions of Register 0xE21F [13:0] Nonmodulo data memory start. value should not be modified by the user.

unaltered at the output and is reintegrated into the audio stream. ADAU1446 have better protection against clock jitter. below 200 Hz, and a minimum signal voltage of 200 mV . On/Off Switch Register (Address 0xE0C1) section. assignment of signals is shown in Table 53. Table 53. S/PDIF to MP Pin Assignments 1 The MP0 to MP3 pins are not applicable and can be used normally. S/PDIF stream are low, except for the validity bit, which is high. because the high validity bit indicates an error. Figure 53. S/PDIF Receiver and Transmitter

Table 54. Addresses of S/PDIF Modes Registers

57536 E0C0 S/PDIF receiver—read

57537 E0C1 S/PDIF transmitter—

57538 E0C2 S/PDIF read channel

57539 E0C3 S/PDIF read channel

57540 E0C4 S/PDIF read channel

57541 E0C5 S/PDIF read channel

57542 E0C6 S/PDIF read channel

57543 E0C7 S/PDIF word length

57544 E0C8 Auxiliary outputs—set

57545 E0C9 S/PDIF lock bit

57546 E0CA Set hot enable 16 bits (2 bytes)

57547 E0CB Read enable auxiliary

57548 E0CC S/PDIF loss-of-lock

Table 55. Bit Descriptions of Register 0xE0C0

11 Virtual LRCLK

10 Block start

9 Channel status

8 User data

Table 56. Bit Descriptions of Register 0xE0C1

0 S/PDIF transmitter—on/off switch 0

Table 57. Addresses of S/PDIF Read Channel Status Register

57538 E0C2 Byte 0

57539 E0C3 Byte 1

57540 E0C4 Byte 2

57541 E0C5 Byte 3

57542 E0C6 Byte 4

Table 58. Bit Descriptions of Register 0xE0C7 the least significant byte, if required.

00 = au ays offxiliary outputs are alw . 01 = au ays xiliary outputs are alw on. Table 60. Bit Descriptions of Register 0xE0C9

0 S/PDIF input lock bit (read only)

0 Hot enable bit 0

1. Bit Descriptions of Register 0xE0CB

0 Read enable auxiliary output (read only)

0 S/PDIF loss-of-lock behavior 0

tegrity well andards of the AES/EBU specification. register should be used only when audio recovery is required.

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 68 of 92 xE241) Table 64. Bit Descriptions of Register 0xE241

2 Output mode 0

1 Group 2 enable 0

• Bit 0 switches Group 1 on and off.
• Bit 1 switches Group 2 on and off.
• Bit 2 switches between I2S and TDM modes. When S/PDIF to I2S mode is active, the pins described in Table 53 When TDM mode is active, Slot 0 and Slot 4 contain the audio annel status, data, and validity bits (see Table 65). The bits are streamed e a onized to the audio data. Only the SBs e used, as shown in Table 65. The corre- onding TD re 54. ble 65. Fu

Description

are used. 1 = Group 2 on data, and Slot 1 contains the streamed block start, ch user in real tim nd are synchr seven M of Slot 1 ar sp M format is shown in more detail in Figu Ta nction of Decoded Bits in Figure 54 0 0 Group 1 enable 0 = Group 1 off 1 = Group 1 on The S/PDIF receiver can be set to send the stereo audio stream and the auxiliary S/PDIF bits in I2S or TDM format on eight of Bit Position

31 Block start (high for first 16 samples)

30 Channel status of right channel

the 12 MP pins. The eight outputs are divided into two groups: Group 1 converts S/PDIF to I2S (LRCLK, BCLK, and SDATA signals), and Group 2 decodes the channel status and user data bits (virtual LRCLK, user data, channel status, validity bit, and block start signal). Channel status of left channel

28 User data bit, right channel

27 User data bit, left channel

26 Validity bit, right channel

25 Validity bit, left channel

[24:0] Not used FRAME LRCLKx 0123 RIG BITS 4567 HT AUDIOLEFT AUDIO DECODE

24 BITS: RIGHT AUDIO

7 DECODED

BITS24 BITS: LEFT AUDIO Figure 54. S/PDIF TD

ach of the 12 m pose pins is controlled by a 4-b mode. f selectable tim een 0.3 μs and 40 μs. ach of these registers is four bytes long and is in 5.23 format. Using Hardware Controls with SigmaDSP GPIO Pins. Table 66. Addresses of Multipurpose Pin Control Registers driven directly from the DSP program in 5.23 format.

57860 E204 Multipurpose pin control, MP0

57861 E205 Multipurpose pin control, MP1

57862 E206 Multipurpose pin control, MP2

57863 E207 Multipurpose pin control, MP3

57864 E208 Multipurpose pin control, MP4

57865 E209 Multipurpose pin control, MP5

57866 E20A Multipurpose pin control, MP6

57867 E20B Multipurpose pin control, MP7

57868 E20C Multipurpose pin control, MP8

57869 E20D Multipurpose pin control, MP9

57870 E20E Multipurpose pin control, MP10

57871 E20F Multipurpose pin control, MP11

Table 67. Bit Settings of Multipurpose Pin Control Registers Table 68. Addresses of Multipurpose Pin Value Registers

gnals for audio applications. (48 kHz when based on a 172.032 MHz core clock) per channel. hysteresis is available to reduce the effects of noise on the input. filtering modes can be set as described in Table 70. Table 69. it Descriptio Table 70. S

01 ADC data filtered

10 Filtered with 1-bit hysteresis

Table 71. Bit Descriptions of Bit Clock Pad Strength Register

11 BCLK11 0

10 BCLK10

9 BCLK9 0

8 BCLK8 0

7 BCLK7 0

6 BCLK6 0

5 BCLK5 0

4 BCLK4 0

3 BCLK3 0

2 BCLK2 0

1 BCLK1 0

0 BCLK0 0

adequate for most applications. The 6 mA setting should be used only when the integrity of the signal is compromised. Table 72. Bit Descriptions of Frame Clock Pad Stren

11 LRCLK11 0

10 LRCLK10 0

9 LRCLK9 0

8 LRCLK8 0

7 LRCLK7 0

6 LRCLK6 0

5 LRCLK5 0

4 LRCLK4 0

3 LRCLK3 0

2 LRCLK2 0

1 LRCLK1 0

0 LRCLK0 0

for most applications. The 6 mA setting should be used only when the integrity of the signal is compromised. Table 73. Bit Descriptions of Multipurpose Pin Pad Strength Regi

11 MP11 0

10 MP10 0

9 MP9 0

8 MP8 0

7 MP7 0

6 MP6 0

5 MP5 0

4 MP4 0

3 MP3 0

2 MP2 0

1 MP1 0

0 MP0 0

applications. The 6 mA setting should be used only when the integrity of the signal is compromised. Table 74. Bit Descriptions of Serial Data Out Pad Strength Register

8 S UT8 DATA_O 0

7 S UT7 DATA_O 0

6 S OUT6 DATA_ 0

5 S OUT5 DATA_ 0

4 S OUT4 DATA_ 0

3 S OUT3 DATA_ 0

2 S OUT2 DATA_ 0

1 S OUT1 DATA_ 0

0 S OUT0 DATA_ 0

grity of the signal is compromised. Table 75. Bit Descriptions of Other Pad Strength Register

6 SCL/CCLK 0

5 CLATCH 0

4 ADDR1/CDATA 0

3 ADDR0 0

2 SDA/COUT 0

1 SPDIFO 0

0 CLKOUT 0

Table 76. Addresses of Serial Input Flexible TDM Interface M

57728 E180 Flexible TDM to Input Channel 0 16 bits (2 bytes)

57729 E181 Flexible TDM to Input Channel 1 16 bits (2 bytes)

57730 E182 Flexible TDM to Input Channe l 2 16 bits (2 bytes)

57731 E183 Flexible TDM to Input Channel 3 16 bits (2 bytes)

57732 E184 Flexible TDM to Input Channel 4 16 bits (2 bytes)

57733 E185 Flexible TDM to Input Channel 5 16 bits (2 bytes)

57734 E186 Flexible TDM to Input Channel 6 16 bits (2 bytes)

57735 E187 Flexible TDM to Input Channel 7 16 bits (2 bytes)

57736 E188 Flexible TDM to Input Channel 8 16 bits (2 bytes)

57737 E189 Flexible TDM to Input Channel 9 16 bits (2 bytes)

57738 E18A Flexible TDM to Input Channel 10 16 bits (2 bytes)

57739 E18B Flexible TDM to Input Channel 11 16 bits (2 bytes)

57740 E18C Flexible TDM to Input Channel 12 16 bits (2 bytes)

57741 E18D Flexible TDM to Input Channel 13 16 bits (2 bytes)

57742 E18E Flexible TDM to Input Channel 14 16 bits (2 bytes)

57743 E18F Flexible TDM to Input Channe l 15 16 bits (2 bytes)

57744 E190 Flexible TDM to Input Channel 16 16 bits (2 bytes)

57745 E191 Flexible TDM to Input Channel 17 16 bits (2 bytes)

57746 E192 Flexible TDM to Input Channel 18 16 bits (2 bytes)

57747 E193 Flexible TDM to Input Channel 19 16 bits (2 bytes)

57748 E194 Flexible TDM to Input Channel 20 16 bits (2 bytes)

57749 E195 Flexible TDM to Input Channel 21 16 bits (2 bytes)

57750 E196 Flexible TDM to Input Channel 22 16 bits (2 bytes)

57751 E197 Flexible TDM to Input Channel 23 16 bits (2 bytes)

Table 77. Bit Descriptions of Flexible TDM to Input Channel Modes Registers

8 MSB position 1

Automatic Output nt section). and does not use t interface mode. sponding ts must to 11 (TDM8 or flexible TDM). starts w Chann d increases sequentially. mode o t side i n in Figure 58. Figure 57. Flexible TDM Interface Mode—Output Streams

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 79 of 92 MS MS M MS M L S OUTPUT CHANNELS (24 CH) 0, 1 0 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 FLEXIBLE AUDI OUT O ROUTING PUT SIDE MATRIX 07696 rface Mode rs (Address 0x des R -059 —Output Routing Example Figure 58. Flexible TDM Inte Serial Output Flexible TDM Interface Modes Registe E1C0 to Address 0xE1DF) egisters Table 78. Addresses of Serial Output Flexible TDM Interface Mo Address Decimal Hex Name Read/Write Word Length

57792 E1C0 TDM Slot 0 and TDM Slot 1 (SDA TA_OUT0) 16 bits (2 bytes)

57793 E1C1 TDM Slot 2 and TDM Slot 3 (SDATA_OUT0) 16 bits (2 bytes)

57794 E1C2 TDM Slot 4 and TDM Slot 5 (SD ATA_OUT0) ytes) 16 bits (2 b

57795 E1C3 TDM Slot 6 and TDM Slot 7 (SD ATA_OUT0) 16 bits (2 bytes)

57796 E1C4 TDM Slot 8 and TDM Slot 9 (SDATA_OUT0) 16 bits (2 bytes)

57797 E1C5 TDM Slot 10 and TDM Slot 11 (SD ATA_OUT0) 16 bits (2 bytes)

57798 E1C6 TDM Slot 12 and TDM Slot 13 (SD ATA_OUT0) 16 bits (2 bytes)

57799 E1C7 TDM Slot 14 and TDM Slot 15 (SDATA_OUT0) 16 bits (2 bytes)

57800 E1C8 TDM Slot 16 and TDM Slot 17 (SDATA_OUT0) 16 bits (2 bytes)

57801 E1C9 TDM Slot 18 and TDM Slot 19 (SDATA_OUT0) 16 bits (2 bytes)

57802 E1CA TDM Slot 20 and TDM Slot 21 (SDATA_OUT0) 16 bits (2 bytes)

57803 E1CB TDM Slot 22 and TDM Slot 23 (SDATA_OUT0) 16 bits (2 bytes)

57804 E1CC TDM Slot 24 and TDM Slot 25 (SDATA_OUT0) 16 bits (2 bytes)

57805 E1CD TDM Slot 26 and TDM Slot 27 (SDATA_OUT0) 16 bits (2 bytes)

57806 E1CE TDM Slot 28 an 16 bits (2 bytes) d TDM Slot 29 (SDATA_OUT0)

57807 E1CF TDM Slot 30 and TDM Slot 31 (SDATA_OUT0) 1 16 bits (2 bytes)

57808 E1D0 TDM Slot 32 and TDM Slot 33 (SDATA_OUT1) 16 bits (2 bytes)

57809 E1D1 TDM Slot 34 and TDM Slot 35 (SDATA_OUT1) 16 bits (2 bytes)

57810 E1D2 TDM Slot 36 and TDM Slot 37 (SDATA_OUT1) 16 bits (2 bytes)

57811 E1D3 TDM Slot 38 and TDM Slot 39 (SDATA_OUT1) 16 bits (2 bytes)

57812 E1D4 TDM Slot 40 and TDM Slot 41 (SDATA_OUT1) 16 bits (2 bytes)

57813 E1D5 TDM Slot 42 and TDM Slot 43 (SDATA_OUT1) 16 bits (2 bytes)

57814 E1D6 TDM Slot 44 and TDM Slot 45 (SDATA_OUT1) 16 bits (2 bytes)

57815 E1D7 TDM Slot 46 and TDM Slot 47 (SDATA_OUT1) 16 bits (2 bytes)

57816 E1D8 TDM Slot 48 and TDM Slot 49 (SDATA_OUT1) 16 bits (2 bytes)

57817 E1D9 TDM Slot 50 and TDM Slot 51 (SDATA_OUT1) 16 bits (2 bytes)

57818 E1DA TDM Slot 52 and TDM Slot 53 (SDATA_OUT1) 16 bits (2 bytes)

57819 E1DB TDM Slot 54 and TDM Slot 55 (SDATA_OUT1) 16 bits (2 bytes)

57820 E1DC TDM Slot 56 and TDM Slot 57 (SDATA_OUT1) 16 bits (2 bytes)

57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 16 bits (2 bytes)

57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 16 bits (2 bytes)

57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) 1 16 bits (2 bytes)

1 Slot 31 and Slot 63 can only be used to hold the MS byte of an 8-bit channel and cannot be used in conjunction with other slots to hold more than eight bits of data. Table 79. Bit Descriptions of Serial Output Flexible TDM Interface Modes Registers—Upper Slot1

15 MSB position 1

Table 80. Bit D erial Output Flexible TDM Interface Mode er Slot 1

7 MSB p 1 osition

1 Bits[7:0

by default in SigmaStudio as described in Table 81. ddress 0x0007 designate written. en it is written, a s ggered on the next frame. uously update the parameter’s value until it reac s the target. need to be programmed manually. into each algorithm and cannot be modified by e user. have five parameters or fewer. Figure 59. Example of Volume Slew

Table 82. ADAU1442/ADAU1445/ADAU1446 RAM and Reg Table 83. Program RAM Registers Table 84. Parameter RAM Registers Table 85. Data RAM Registers

Table 86. Serial Input Port Modes Registers

57346 E0 Serial Input Port 2 modes 16 bits (2 bytes) 02

57347 E003 Seria t Port 3 modes 16 bits (2 bytes) l Inpu

57348 E004 l Inp des 16 bits (2 bySeria ut Port 4 mo tes)

57349 E005 Serial Inp 5 modes 16 bits (2 byut Port tes)

57350 E006 Serial Inp 6 modes 16 bits (2 byut Port tes)

57351 E007 Serial Inp 7 modes 16 bits (2 byut Port tes)

57352 E008 Serial Input P t 8 modes 16 bits (2 byor tes)

Table 87. Serial Port Mo egisters

57408 E040 Serial Output Port es 0 mod 16 bits (2 bytes)

57409 E041 Serial Output Port es 1 mod 16 bits (2 bytes)

57410 E042 Serial Output Port es 16 bits (2 bytes) 2 mod

57412 E044 Serial Output Por t 4 modes 16 bits (2 bytes)

57414 E046 Serial O utput Port 6 modes 16 bits (2 bytes)

57415 Serial Output Port 7 modes 16 bits (2 bytes) E047

57416 E048 rial Output Po es 1Se rt 8 mod 6 bits (2 bytes)

57417 E049 ve 1High speed sla interface mode 6 bit (2 bytes)

Table 88. Flexible Audio Routing Matrix Modes Registers

57472 E080 input select, Channel 1) ) ASRC Pair 0 (Channel 0, 16 bits (2 bytes

57476 E08 SRC input select, Pair 4 (Channel 8, Channel 9) 16 bits (2 bytes) 4 A

57477 E085 ASRC input select, Pair 5 el 10, Channel 11) (Chann 16 bits (2 bytes)

57478 E086 ASRC input select, Pair 6 , Channel 13) bytes) (Channel 12 16 bits (2

57491 E093 erial outpu air 3 (Channel 6, Channel 7) 16 bS t select, P its (2 bytes)

57492 E094 erial outpu hannel 9) 16 bS t select, Pair 4 (Channel 8, C its (2 bytes)

57493 E095 erial outpu Channel 11) 16 bS t select, Pair 5 (Channel 10, its (2 bytes)

57494 E096 erial outpu Channel 13) 16 bS t select, Pair 6 (Channel 12, its (2 bytes)

57495 E097 erial outpu Channel 15) 16 bS t select, Pair 7 (Channel 14, its (2 bytes)

57496 E098 erial outpu Channel 17) 16 bS t select, Pair 8 (Channel 16, its (2 bytes)

57497 E099 erial outpu Channel 19) 16 bS t select, Pair 9 (Channel 18, its (2 bytes)

57498 E09A rial outpu , Channel 21) 16 bSe t select, Pair 10 (Channel 20 its (2 bytes)

57499 E09B erial outpu , Channel 23) 16 bS t select, Pair 11 (Channel 22 its (2 bytes)

Table 89. S/PDIF Modes Registers

57536 E S/ eiver—read auxiliary output 0C0 PDIF rec 16 bits (2 bytes)

57537 E S/ tch 0C1 PDIF transmitter—on/off swi 16 bits (2 bytes)

57538 E S/ e 0 0C2 PDIF read channel status, Byt 16 bits (2 bytes)

57539 E S/ e 1 0C3 PDIF read channel status, Byt 16 bits (2 bytes)

57540 E S/ e 2 0C4 PDIF read channel status, Byt 16 bits (2 bytes)

57541 E S/ e 3 0C5 PDIF read channel status, Byt 16 bits (2 bytes)

57542 E S/ e 4 0C6 PDIF read channel status, Byt 16 bits (2 bytes)

57543 E S/0C7 PDIF word length control 16 bits (2 bytes)

57544 E Au ode 0C8 xiliary outputs—set enable m 16 bits (2 bytes)

57545 E S/0C9 PDIF lock bit detection 16 bits (2 bytes)

57546 E Se tes) 0CA t hot enable 16 bits (2 by

57547 E0CB Read enable auxiliary output 16 bits (2 bytes)

57548 E0CC S/PDIF loss-of-lock behavior 16 bits (2 bytes)

Table 90. ASRC es Reg

57601 E101 16 bitStereo ASRC[3:0] lock status and mute s (2 bytes)

57603 E103 16 bitStereo ASRC[3:0] mute ramp disable s (2 bytes)

57665 E141 16 bitStereo ASRC[7:4] lock status and mute s (2 bytes)

57667 E143 16 bitStereo ASRC[7:4] mute ramp disable s (2 bytes)

Table 91. Serial Input Flexi

57728 E180 16 bFlexible TDM to Input Channel 0 its (2 bytes)

57729 E181 16 bFlexible TDM to Input Channel 1 its (2 bytes)

57730 E182 16 bFlexible TDM to Input Channel 2 its (2 bytes)

57731 E183 16 bFlexible TDM to Input Channel 3 its (2 bytes)

57732 E184 16 bFlexible TDM to Input Channel 4 its (2 bytes)

57733 E185 16 bFlexible TDM to Input Channel 5 its (2 bytes)

57734 E186 16 bFlexible TDM to Input Channel 6 its (2 bytes)

57735 E187 16 bFlexible TDM to Input Channel 7 its (2 bytes)

57736 E188 16 bFlexible TDM to Input Channel 8 its (2 bytes)

57737 E189 16 bFlexible TDM to Input Channel 9 its (2 bytes)

57738 E18A 16 bFlexible TDM to Input Channel 10 its (2 bytes)

57739 E18B 16 bFlexible TDM to Input Channel 11 its (2 bytes)

57740 E18C 16 bFlexible TDM to Input Channel 12 its (2 bytes)

57741 E18D 16 bFlexible TDM to Input Channel 13 its (2 bytes)

57742 E18E 16 bFlexible TDM to Input Channel 14 its (2 bytes)

57743 E18F 16 bFlexible TDM to Input Channel 15 its (2 bytes)

57744 E190 16 bFlexible TDM to Input Channel 16 its (2 bytes)

57749 E195 le TDM to Input Channel 21 16 Flexib bits (2 bytes)

57750 E196 16 Flexible TDM to Input Channel 22 bits (2 bytes)

57751 E197 16 Flexible TDM to Input Channel 23 bits (2 bytes)

Table 92. Serial t Flex

57792 E1C0 TDM Slot 0 and TDM Slot 1 (SDATA_OUT0) 16 bits (2 bytes)

57794 E1C2 TDM Slot 4 and TDM Slot 5 (SDATA_OUT0) 16 bits (2 bytes)

57795 E1C3 TDM Slot 6 and TDM Slot 7 (SDATA_OUT0) 16 bits (2 bytes)

57797 E1C5 TDM Slot 10 and TDM Slot 11 (SDATA_OUT0) 16 bits (2 bytes)

57798 E1C6 TDM Slot 12 and TDM Slot 13 (SDATA_OUT0) 16 bits (2 bytes)

57801 C9 TDM Slot 18 and TDM Slot 19 (SDATA_OUT0) 16 bits (2 bytes) E1

57802 E d TDM Slot 21 (SDATA_OUT0) 1CA TDM Slot 20 an 16 bits (2 bytes)

57803 E UT0) s) 1CB TDM Slot 22 and TDM Slot 23 (SDATA_O 16 bits (2 byte

57804 E s) 1CC TDM Slot 24 and TDM Slot 25 (SDATA_OUT0) 16 bits (2 byte

57805 E UT0) s) 1CD TDM Slot 26 and TDM Slot 27 (SDATA_O 16 bits (2 byte

57806 E s) 1CE TDM Slot 28 and TDM Slot 29 (SDATA_OUT0) 16 bits (2 byte

57807 E1CF TDM Slot 30 and TDM Slot 31 (SDATA_OUT0) 16 bits (2 bytes)

57809 E1D1 TDM Slot 34 and TDM Slot 35 (SDAT A_OUT1) 16 bits (2 bytes)

57810 D2 TDM Slot 36 and TDM Slot 37 (SDATA_OUT1) 16 bits (2 bytes) E1

57812 E1D4 TDM Slot 40 and TDM Slot 41 (SDATA_OUT1) ) 16 bits (2 bytes

57813 E1D5 TDM Slot 42 and TDM Slot 43 (SDATA_OUT1) ) 16 bits (2 bytes

57814 E1D6 TDM Slot 44 and TDM Slot 45 (SDATA_OUT1) ) 16 bits (2 bytes

57815 E1D7 TDM Slot 46 and TDM Slot 47 (SDATA_OUT1) ) 16 bits (2 bytes

57816 E1D8 TDM Slot 48 and TDM Slot 49 (SDATA_OUT1) ) 16 bits (2 bytes

57817 E1D9 TDM Slot 50 and TDM Slot 51 (SDATA_OUT1) ) 16 bits (2 bytes

57818 E1DA TDM Slot 52 and TDM Slot 53 (SDATA_OUT1) ) 16 bits (2 bytes

57819 E1DB TDM Slot 54 and TDM Slot 55 (SDATA_OUT1) ) 16 bits (2 bytes

57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) ) 16 bits (2 bytes

57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) ) 16 bits (2 bytes

57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) ) 16 bits (2 bytes

Table 93. Other M egiste

57856 E20 C 1 s) 0 yclic Redundancy Check Ideal Value 16 bits (2 byte

57857 E20 C 2 s) 1 yclic Redundancy Check Ideal Value 16 bits (2 byte

57858 E20 C s) 2 yclic redundancy check enable 16 bits (2 byte

57860 E20 M s) 4 ultipurpose pin control, MP0 16 bits (2 byte

57861 E20 M s) 5 ultipurpose pin control, MP1 16 bits (2 byte

57862 E20 M s) 6 ultipurpose pin control, MP2 16 bits (2 byte

57863 E20 M s) 7 ultipurpose pin control, MP3 16 bits (2 byte

57864 E20 M s) 8 ultipurpose pin control, MP4 16 bits (2 byte

57865 E209 Multipur pose pin control, MP5 16 bits (2 bytes)

57866 E20A Multipurpose pin control, MP6 16 bits (2 bytes)

57867 E20B Multipurpose pin control, MP7 16 bits (2 bytes)

57868 E20C Multipurpose pin control, MP8 16 bits (2 bytes)

57569 Multipurpose pin control, MP9 16 bits (2 bytes) E20D

57870 E2 M pose pin control, MP10 0E ultipur 16 bits (2 bytes)

57871 E2 M 0F ultipurpose pin control, MP11 16 bits (2 bytes)

57872 E2 W 10 atchdog enable 16 bits (2 bytes)

57873 E2 W 11 atchdog Value 1 16 bits (2 bytes)

57874 E2 W 12 atchdog Value 2 16 bits (2 bytes)

57887 E2 M 1F odulo data memory 16 bits (2 bytes)

57888 E2 D 20 SP core rate select 16 bits (2 bytes)

57889 E2 D 21 ejitter window 16 bits (2 bytes)

57892 E2 A 24 DC filter mode 16 bits (2 bytes)

57893 E2 C 25 yclic redundancy check error sticky 16 bits (2 bytes)

57894 E2 W 26 atchdog error sticky 16 bits (2 bytes)

57895 E2 C 27 RC and watchdog mute 16 bits (2 bytes)

57896 E2 C 28 ore run 16 bits (2 bytes)

57897 E2 P 29 rogram counter peak count 16 bits (2 bytes)

57920 E2 C 40 lock pad multiplexer 16 bits (2 bytes)

57921 E2 E 41 nable S/PDIF to I S output 2 16 bits (2 bytes)

57927 E2 B 47 it clock pad strength 16 bits (2 bytes)

57928 E248 F rame clock pad strength 16 bits (2 bytes)

57929 E249 Multipur pose pin pad strength 16 bits (2 bytes)

57930 E2 S 4A erial data output pad strength 16 bits (2 bytes)

57932 E2 O 4C ther pad strength 16 bits (2 bytes)

57984 E2 M 80 aster clock enable switch 16 bits (2 bytes)

Figure 63. Recommended Power Supply Bypass Capacitor Connections

Figure 64. Self-Boot Application Schematic

ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 90 of 92 ADAU1442/ADAU1445/ADAU1446 100 LRCLK2 SDATA_IN1 BCLK1 LRCLK1 SDATA_IN0 BCLK0 DGND IOVDD LRCLK0 MP11 MP10 MP9 MP8 ADDR0 CLATCH SCL/CCLK SDA/COUT ADDR1/CDATA DVDD DGND IOVDD BCLK3 LRCLK3 SDATA_IN2 BCLK2 SDATA_OUT6 LRCLK10 BCLK10 SDATA_OUT7 LRCLK11 BCLK11 IOVDD DGND SDATA_OUT8 PLL0 PLL1 MP0/ADC0 MP1/ADC1 MP2 /ADC2 MP3/ADC3 RESET CLKOUT IOVDD DGND DVDD BCLK8 SDATA_IN8 SDATA_OUT5 LRCLK9 BCLK9 DVDD SDATA_IN3 SDATA_OUT0 LRCLK4 BCLK4 SDATA_IN4 SDATA_OUT1 LRCLK5 BCLK5 SDATA_IN5 SDATA_OUT2 IOVDD DGND DVDD LRCLK6 BCLK6 SDATA_IN6 SDATA_OUT3 LRCLK7 BCLK7 SDATA_IN7 SDATA_OUT4 LRCLK8 IOVDD DGND DGND IOVDD SELFBOOT CLKMODE1 CLKMODE0 RSVD PLL2 MP7 MP6 MP5 MP4 DVDD DGND IOVDD VDRIVE XTALO XTALI PLL_FILT PVDD PGND SPDIFI SPDIFO AVDD AGND DVDD 100nF IOVDD D3V3 RESET IOVDD DVDD IOVDD DVDD IOVDD IOVDD 100nF 100nF 07696-063 100nF 100nF 100nF100nF 10μF10μF10μF10μF 100nF AVDDD3V3 DVDD D3V3 PVDD IOVDD DVDD SCL SDA I2C BUS BULK BYPASS CAPACITORS DVDDIOVDD 100nF100nF 100nF 100nF 100nF 100nF100nF 33nF 1.8nF 22pF DVDD PVDD AVDD DVDD IOVDD D3V3 IOVDD 22pF 1kΩ 10kΩ 1.5kΩ 100nF PVDD 2.2kΩ2.2kΩ 12.288MHz REGULATOR PLL LOOP FILTER DVDD 2Figure 65. I C Control Application Schematic

Figure 66. SPI Control Application Schematic

14.00 BSC SQ

0.08 MAX

0.50 BSC

Figure 67. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

1.60 MAX

Figure 68. 100-Lead Thin Quad Flat Package [LQFP] Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. registered trademarks are the prop erty of their respective owners.