ADAU1382

ADAU1382 AD | Alldatasheet

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Technical content

Low Noise Stereo Codec with Recording and Playback Processing ADAU1382

FEATURES

24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Built-in sound engine for audio processing Wind noise filter Automatic level control (ALC) 5-band equalizer, including notch filter Sampling rates from 8 kHz to 96 kHz Stereo pseudo differential microphone input Optional stereo digital microphone input pulse-density modulation (PDM) Stereo line output PLL supporting a range of input clock rates Analog and digital I/O 1.8 V to 3.3 V Software control via SigmaStudio graphical user interface Software-controllable, clickless mute Software register and hardware pin standby mode 32-lead, 5 mm × 5 mm LFCSP

APPLICATIONS

The ADAU1382 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1382 ideal for battery-powered audio applications. A configurable sound engine provides enhanced record and playback processing to improve overall audio quality. The record path includes two digital stereo microphone inputs and an analog stereo input path. The analog inputs can be configured for either a pseudo differential or a single-ended stereo source. A dedicated analog beep input signal can be mixed into any output path. The ADAU1382 includes a stereo line output and speaker driver, which makes the device capable of supporting dynamic speakers. The serial control bus supports the I 2C® or SPI protocols, and the serial audio bus is programmable for I2S, left-justified, right- justified, or TDM mode. A programmable PLL supports flexible clock generation for all standard rates and available master clocks from 11 MHz to 20 MHz. FUNCTIONAL BLOCK DIAGRAM PGA PGA LEFT ADC RIGHT ADC LEFT DAC RIGHT DAC PGA BEEP PDN MICBIAS LMIC/LMICN/ MICD1 LMICP RMIC/RMICN/ MICD2 RMICP AOUTL AOUTR SPP SPN PLL SOUND ENGINE DECIMATION FILTERS WIND NOISE NOTCH FILTER EQUALIZER DIGITAL VOLUME CONTROL AUTOMATIC LEVEL CONTROL OUTPUT MIXER MCKI REGULATOR CM IOVDD DGND DVDDOUT AVDD1 AGND1 AVDD2 AGND2 SERIAL DATA INPUT/OUTPUT PORTSADC_SDATA/ GPIO1 BCLK/GPIO2 LRCLK/GPIO3 DAC_SDATA/ GPIO0 I2C/SPI CONTROL PORTADDR0/CDATA ADDR1/CLATCH SCL/CCLK SDA/COUT ADAU1382 MICROPHONE BIAS 08427-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

Rev. 0 | Page 2 of 84 TABLE OF CONTENTS Clock Management, Internal Regulator, and PLL Control ... 44

Rev. 0 | Page 3 of 84

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 4 of 84 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V , digital supply = 1.5 V , unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.288 MHz (fS = 48 kHz, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 2 mA; high level input voltage = 0.7 × IOVDD; and low level input voltage = 0.3 × IOVDD. All power management registers are set to their default states. RECORD SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Noninverting Inputs PGA (LMICP , RMICP) All gain settings 500 kΩ Inverting Inputs PGA (LMICN, RMICN) 0 dB gain 62 kΩ 6 dB gain 32 kΩ 10 dB gain 22 kΩ 14 dB gain 14 kΩ 17 dB gain 10 kΩ 20 dB gain 8 kΩ 26 dB gain 5 kΩ 32 dB gain 4 kΩ Beep Input PGA 0 dB 20 kΩ 6 dB 9 kΩ 10 dB 6 kΩ 14 dB 3.5 kΩ −23 dB 50 kΩ 20 dB 2 kΩ 26 dB 2 kΩ 32 dB 2 kΩ SINGLE-ENDED MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 94 99.2 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 92 96.5 dB Total Harmonic Distortion + Noise −3 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −90 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 100 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 97 dB

Rev. 0| Page 5 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Left/Right Microphone PGA Gain Range AVDD = 3.3 V 0 32 dB Left/Right Microphone PGA Mute Attenuation AVDD = 3.3 V; mute set by Register 0x400E, Bit 1, and Register 0x400F, Bit 1 −98 dB Interchannel Gain Mismatch AVDD = 3.3 V 50 mdB Offset Error AVDD = 3.3 V 0.25 mV Gain Error AVDD = 3.3 V −1 % Interchannel Isolation AVDD = 3.3 V −98 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −55 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −55 dB DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 94 99.2 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 92 96.5 dB Total Harmonic Distortion + Noise −3 dBFS AVDD = 1.8 V −84 dB AVDD = 3.3 V −85 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 100 dB No Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 97 dB Left/Right Microphone PGA Mute Attenuation AVDD = 3.3 V; mute set by Register 0x400E, Bit 1, and Register 0x400F, Bit 1 −98 dB Interchannel Gain Mismatch AVDD = 3.3 V 50 mdB Offset Error AVDD = 3.3 V 0.25 mV Gain Error AVDD = 3.3 V −1 % Interchannel Isolation AVDD = 3.3 V −85 dB Common-Mode Rejection Ratio AVDD = 3.3 V, 100 mV rms, 1 kHz −60 dB AVDD = 3.3 V, 100 mV rms, 20 kHz −45 dB BEEP TO LINE OUTPUT PATH Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Total Harmonic Distortion + Noise −3 dBFS input, measured at AOUTL pin, beep gain set to 0 dB AVDD = 1.8 V −88 dB AVDD = 3.3 V −88 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 102 dB

Rev. 0 | Page 6 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 102 dB Beep Input Mute Attenuation AVDD = 3.3 V; mute set by Register 0x4008, Bit 3 −90 dB Offset Error AVDD = 3.3 V 10 mV Gain Error AVDD = 3.3 V −0.3 dB Interchannel Gain Mismatch 30 mdB Beep Input PGA Gain Range AVDD = 3.3 V −23 +32 dB Beep Playback Mixer Gain Range AVDD = 3.3 V −15 +6 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −58 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −72 dB MICROPHONE BIAS Microphone bias enabled Bias Voltage 0.65 × AVDD AVDD = 1.8 V, low bias 1.17 V AVDD = 3.3 V, low bias 2.145 V 0.90 × AVDD AVDD = 1.8 V, high bias 1.62 V AVDD = 3.3 V, high bias 2.97 V Bias Current Source AVDD = 3.3 V, high bias, high performance 5 mA Noise in the Signal Bandwidth AVDD = 3.3 V, 20 Hz to 20 kHz High bias, high performance 39 nV√Hz High bias, low performance 78 nV√Hz Low bias, high performance 25 nV√Hz Low bias, low performance 35 nV√Hz AVDD = 1.8 V, 20 Hz to 20 kHz High bias, high performance 35 nV√Hz High bias, low performance 45 nV√Hz Low bias, high performance 23 nV√Hz Low bias, low performance 23 nV√Hz OUTPUT SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS DAC Resolution All DACs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB DAC TO LINE OUTPUT PATH Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Line Output Mute Attenuation, DAC to Mixer Path Muted AVDD = 3.3 V; mute set by Register 0x401C, Bit 5, and Register 0x401E, Bit 6 −85 dB Line Output Mute Attenuation, Line Output Muted AVDD = 3.3 V; mute set by Register 0x4025, Bit 1, and Register 0x4026, Bit 1 −85 dB

Rev. 0| Page 7 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 94 103 dB No Filter (RMS) AVDD = 1.8 V 97 dB AVDD = 3.3 V 92 100 dB Total Harmonic Distortion + Noise −3 dBFS dB AVDD = 1.8 V −88 dB AVDD = 3.3 V −88 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 103 dB No Filter (RMS) AVDD = 1.8 V 97 dB AVDD = 3.3 V 100 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −55 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −63 dB Gain Error AVDD = 3.3 V −1 dB Interchannel Gain Mismatch AVDD = 3.3 V 50 mdB Offset Error AVDD = 3.3 V 10 mV DAC TO SPEAKER OUTPUT PATH PO = output power Differential Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/1.65 V rms AVDD = 1.8 V 1.1 (3.12) V rms (V p-p) AVDD = 3.3 V 2.0 (5.66) V rms (V p-p) Total Harmonic Distortion + Noise 4 Ω Load AVDD = 1.8 V, PO = 50 mW −60 dB AVDD = 3.3 V, PO = 175 mW −60 dB 8 Ω Load AVDD = 1.8 V, PO = 50 mW −60 dB AVDD = 3.3 V, PO = 175 mW −60 dB AVDD = 3.3 V, PO = 330 mW −60 dB AVDD = 3.3 V, PO = 440 mW −16 dB Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 100 dB AVDD = 3.3 V 94 105 dB No Filter (RMS) AVDD = 1.8 V 98 dB AVDD = 3.3 V 92 103 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 100 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 98 dB AVDD = 3.3 V 103 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V,100 mV p-p at 217 Hz −55 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −55 dB Differential Offset Error AVDD = 3.3 V 2 mV Mono Mixer Mute Attenuation, DAC to Mixer Path Muted Mute set by Register 0x401F, Bit 0 −90 dB BEEP TO SPEAKER OUTPUT PATH PO = output power Differential Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/1.65 V rms AVDD = 1.8 V 1.1 (3.12) V rms (V p-p) AVDD = 3.3 V 2.0 (5.66) V rms (V p-p)

Rev. 0 | Page 8 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Total Harmonic Distortion + Noise 8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW −60 dB AVDD = 3.3 V, PO = 175 mW −60 dB Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 97 dB AVDD = 3.3 V 103 dB No Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 100 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 98 dB AVDD = 3.3 V 103 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 101 dB Power Supply Rejection Ratio CM capacitor = 10 μF 100 mV p-p at 217 Hz −57 dB 100 mV p-p at 1 kHz −60 dB Differential Offset Error 2 mV Mono Mixer Mute Attenuation, Beep to Mixer Path Muted Mute set by Register 0x401F, Bit 0 −90 dB REFERENCE (CM PIN) Common-Mode Reference Output AVDD/2 V POWER SUPPLY SPECIFICATIONS AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the sound engine processing path enabled. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit AVDD1, AVDD2 1.8 3.3 3.65 V IOVDD 1.63 3.3 3.65 V Digital I/O Current (IOVDD = 3.3 V) 20 pF capacitive load on all digital pins Slave Mode, Analog I/O,

12.288 MHz External MCLK Input

fS = 48 kHz 0.20 mA f S = 96 kHz 0.35 mA f S = 8 kHz 0.04 mA Master Mode, MCKO Disabled fS = 48 kHz 1.25 mA f S = 96 kHz 2.50 mA f S = 8 kHz 0.22 mA Digital I/O Current (IOVDD = 1.8 V) 20 pF capacitive load on all digital pins Slave Mode, Analog I/O, f S = 48 kHz 0.10 mA f S = 96 kHz 0.18 mA f S = 8 kHz 0.02 mA Master Mode, MCKO Disabled fS = 48 kHz 0.68 mA f S = 96 kHz 1.33 mA f S = 8 kHz 0.12 mA Analog Current (AVDD) See Table 4

measurements are given in units of mA rms. Table 4. Mixer Boost and Power Management Conditions 1 Set by Register 0x4009, Bits[4:1], and Register 0x4029, Bits[5:2]. 2 Set by Register 0x4009, Bits[6:5].

Rev. 0 | Page 10 of 84 Parameter Mode Factor Min Typ Max Unit DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typ value is for 48 kHz 0.4535 × fS 22 kHz 96 kHz mode, typ value is for 96 kHz 0.3646 × fS 35 69 kHz Pass-Band Ripple 48 kHz mode, typ value is for 48 kHz ±0.01 dB 96 kHz mode, typ value is for 96 kHz ±0.05 dB Transition Band 48 kHz mode, typ value is for 48 kHz 0.5 × fS 24 kHz 96 kHz mode, typ value is for 96 kHz 0.5 × fS 48 kHz Stop Band 48 kHz mode, typ value is for 48 kHz 0.5465 × fS 26 kHz 96 kHz mode, typ value is for 96 kHz 0.6354 × fS 61 kHz Stop-Band Attenuation 48 kHz mode, typ value is for 48 kHz 70 dB 96 kHz mode, typ value is for 96 kHz 70 dB Group Delay 48 kHz mode, typ value is for 48 kHz 25/fS 521 μs 96 kHz mode, typ value is for 96 kHz 11/fS 115 μs DIGITAL INPUT/OUTPUT SPECIFICATIONS −25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V , unless otherwise specified. Table 6. Parameter Conditions/Comments Min Typ Max Unit HIGH LEVEL INPUT VOLTAGE (VIH) 0.7 × IOVDD V LOW LEVEL INPUT VOLTAGE (VIL) IOVDD ≥ 2.97 V 0.3 × IOVDD V 1.8 V ≤ IOVDD ≤ 2.97 V 0.2 × IOVDD V IOVDD < 1.8 V 0.1 × IOVDD V INPUT LEAKAGE IIH at VIH = 2.4 V ±0.17 μA I IL at VIL = 0.8 V ±0.17 μA I IL of MCKI −7 μA I IH with internal pull-up ±0.7 μA I IL with internal pull-down −7 μA I IH with internal pull-up 5 μA I IL with internal pull-down ±0.18 μA HIGH LEVEL OUTPUT VOLTAGE (VOH) For low drive strength, IOH = 2 mA and IOL = 2 mA at IOVDD = 3.3 V, IOH = 0.6 mA and IOL = 0.6 mA at IOVDD = 1.8 V; for high drive strength, IOH = 3 mA and IOL = 3 mA at IOVDD = 3.3 V, IOH = 0.9 mA and IOL = 0.9 mA at IOVDD = 1.8 V IOVDD − 0.4 V LOW LEVEL OUTPUT VOLTAGE (VOL) For low drive strength, IOH = 2 mA and IOL = 2 mA at IOVDD = 3.3 V, IOH = 0.6 mA and IOL = 0.6 mA at IOVDD = 1.8 V; for high drive strength, IOH = 3 mA and IOL = 3 mA at IOVDD = 3.3 V, IOH = 0.9 mA and IOL = 0.9 mA at IOVDD = 1.8 V 0.4 V INPUT CAPACITANCE 5 pF

−25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V , unless otherwise specified. Table 7. Digital Timing tMP 50 90.9 ns Master clock (MCLK) period (that is, period of the signal input to MCKI). tBIL 10 ns BCLK pulse width low. tBIH 10 ns BCLK pulse width high. tLIS 5 ns LRCLK setup. Time to BCLK rising. tLIH 5 ns LRCLK hold. Time from BCLK rising. tSIS 5 ns DAC_SDATA setup. Time to BCLK rising. tSIH 5 ns DAC_SDATA hold. Time from BCLK rising. tSODM 70 ns ADC_SDATA delay. Time from BCLK falling in master mode. fCCLK,R 5 MHz CCLK frequency, read operation, IOVDD = 1.8 V ± 10%. fCCLK,R 10 MHz CCLK frequency, read operation, IOVDD = 3.3 V ± 10%. fCCLK,W 25 MHz CCLK frequency, write operation, IOVDD = 1.8 V ± 10%. fCCLK,W 25 MHz CCLK frequency, write operation, IOVDD = 3.3 V ± 10%. tCCPL 10 ns CCLK pulse width low. tCCPH 10 ns CCLK pulse width high. tCLS 10 ns CLATCH setup. Time to CCLK rising. tCLH 5 ns CLATCH hold. Time from CCLK rising. tCLPH 10 ns CLATCH pulse width high. tCDS 5 ns CDATA setup. Time to CCLK rising. tCDH 5 ns CDATA hold. Time from CCLK rising. tCOD 70 COUT delay from CCLK edge to valid data, IOVDD = 1.8 V ± 10%. 40 ns COUT delay from CCLK edge to valid data, IOVDD = 3.3 V ± 10%. tSCS 0.6 μs Setup time; relevant for repeated start condition. tSCH 0.6 μs Hold time. After this period, the first clock is generated. tBFT 0.6 μs Bus-free time. Time between stop and start. DIGITAL MICROPHONE RL = 1 MΩ, CL = 14 pF. tDCF 10 ns Digital microphone clock fall time. tDCR 10 ns Digital microphone clock rise time. tDDV 22 30 ns Digital microphone delay time for valid data. tDDH 0 12 ns Digital microphone delay time for data three-stated.

resistance. All characteristics are for a 4-layer board. Table 9. Thermal Resistance

23 AGND2

22 SPP

20 SPN

19 AVDD2

18 MCKO

17 MCKI

1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE

Figure 7. 32-Lead LFCSP Pin Configuration Table 10. Pin Function Descriptions connected between this pin and ground to reduce crosstalk between the ADCs and DACs. 2 PDN A_IN Power-Down. Setting this pin to 0 powers down the chip. Resides in AVDD1 domain. 4 AVDD1 PWR Analog Power Supply. Should be equivalent to AVDD2. DGND with a 100 nF capacitor. 7 GPIO D_IO Dedicated General-Purpose Input/Output. 8 SCL/CCLK D_IN I2C Clock/SPI Clock. 9 SDA/COUT D_IO I2C Data/SPI Data Output. 10 ADDR0/CDATA D_IN I2C Address 0/SPI Data Input. 11 ADDR1/CLATCH D_IN I2C Address 1/SPI Latch Signal. should be decoupled to DGND with a 100 nF capacitor. 13 DAC_SDATA/GPIO0 D_IO DAC Serial Input Data/General-Purpose Input and Output. 14 ADC_SDATA/GPIO1 D_IO ADC Serial Output Data/General-Purpose Input and Output. 15 BCLK/GPIO2 D_IO Serial Data Port Bit Clock/General-Purpose Input and Output. 16 LRCLK/GPIO3 D_IO Serial Data Port Frame Clock/General-Purpose Input and Output. 17 MCKI D_IN Master Clock Input.

Rev. 0 | Page 16 of 84 Pin No. Mnemonic Type1 Description 18 MCKO D_OUT Master Clock Output. 19 AVDD2 PWR Analog Power Supply. Should be equivalent to AVDD1. 20 SPN A_OUT Speaker Amplifier Negative Signal Output. 21 NC No Connect. 22 SPP A_OUT Speaker Amplifier Positive Signal Output. 23 AGND2 PWR Speaker Amplifier Ground. 24 NC No Connect. 25 AOUTR A_OUT Line Output Amplifier, Right Channel. 26 AOUTL A_OUT Line Output Amplifier, Left Channel. 27 RMIC/RMICN/MICD2 A_IN Right Channel Input from Single-Ended Source/Right Channel Input from Negative Pseudo Differential Source/Digital Microphone Input 2. 28 RMICP A_IN Right Channel Input from Positive Pseudo Differential Source. 29 LMICP A_IN Left Channel Input from Positive Pseudo Differential Source. 30 LMIC/LMICN/MICD1 A_IN Left Channel Input from Single-Ended Source/Left Channel Input from Negative Pseudo Differential Source/Digital Microphone Input 1. 31 BEEP A_IN Beep Signal Input. 32 MICBIAS PWR Microphone Bias. THERM_PAD (Exposed Pad) Exposed Pad. The exposed pad is connected internally to the ADAU1382 grounds. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. 1 A_OUT = analog output, A_IN = analog input, PWR = power, D_IO = digital input/output, D_OUT = digital output, and D_IN = digital input.

Figure 22. System Block Diagram with Differential Inputs

Figure 23. System Block Diagram with Analog Microphone Inputs

Figure 24. System Block Diagram with Single-Ended Stereo Line Inputs

Figure 25. System Block Diagram with Stereo Digital Microphone Inputs

Rev. 0 | Page 24 of 84 THEORY OF OPERATION The ADAU1382 is a low power audio codec with an integrated, fixed-function audio processing sound engine. It is an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo DAC each have a dynamic range (DNR) performance of at least 96.5 dB and a total harmonic distortion plus noise (THD + N) performance of at least −90 dB. The serial data port is compatible with I 2S, left- justified, right-justified, and TDM modes for interfacing to digital audio data. The operating voltage range is 1.8 V to 3.65 V , with an on-board regulator generating the internal digital supply voltage. The record path includes very flexible input configurations that can accept differential or single-ended analog microphone inputs as well as two stereo digital microphone inputs. There is also a beep input pin (BEEP) dedicated to analog beep signals that are common in digital still camera applications. A microphone bias pin that can power electrets-type microphones is also available. Each input signal has its own programmable gain amplifier (PGA) for input volume adjustment. An automatic level control (ALC) is built into the sound engine to maintain a constant input re- cording volume. The ADCs and DACs are high quality, 24-bit Σ-Δ converters that operate at selectable 64× or 128× oversampling rates. The base sampling rate of the converters is set by the input clock rate and can be further scaled with the converter control register settings. The converters can operate at sampling frequencies from 8 kHz to 96 kHz. The ADCs and DACs also include very fine-step digital volume controls. The playback path allows input signals and DAC outputs to be mixed into speaker and/or line outputs. The speaker driver is capable of driving 400 mW into an 8 Ω load. The fixed-function sound engine contains a digital audio processing flow optimized for digital still camera stereo audio processing. However, the flexibility offered by the built-in sound engine allows this codec to be used for a wide variety of low power applications. Signal processing blocks included in the sound engine include the following:

• Wind noise filter
• Programmable multiband equalizer
• Configurable notch filter
• Automatic level control
• Digital volume control
• Multiplexers for signal routing The ADAU1382 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 11 MHz to 20 MHz. The ADAU1382 is provided in a small, 32-lead, 5 mm × 5 mm lead frame chip scale package (LFCSP) with an exposed bottom pad.

Bit 0, core clock enable, is set to 1. the internal functional blocks of the ADAU1382. PLL control, Bit 1, PLL lock, are set to 1. times are provided in Table 11. Table 11. PLL Lock Time controller, and Bit 0, sound engine, must be enabled. engine. For more information, see the Sound Engine section. in power saving, normal, or enhanced performance operation. section for more information. specifications and graphs of the filters. sequence is IOVDD first, AVDD2 second, and AVDD1 last.

Figure 28. Clock Routing Diagram Table 13. Clock Control Register (Register 16384, 0x4000) sets the core clock divider to f/4 when using the PLL.

3 Clock source select 0: direct from MCKI pin (default)

rate that is set in Register 16407 (0x4017), Converter Control 0. serial port control sampling rate.

Table 14. Base Sampling Rate Divisions for fS = 48 kHz Table 15. Base Sampling Rate Divisions for fS = 44.1 kHz input frequencies in the range of 11 MHz to 20 MHz. single continuous write to the control port. Figure 29. PLL Block Diagram In integer mode, the values set for N and M are ignored. (R + (N/M)) multiple of the PLL output. 48 kHz sampling rates can be found in Table 16 and Table 17. Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz1 1 Desired core clock = 11.2896 MHz, PLL output = 45.1584 MHz. Table 17. Fractional PLL Parameter Settings for fS = 48 kHz1 1 Desired core clock = 12.288 MHz, PLL output = 49.152 MHz. values and MCLK frequencies.

(0x4017), Converter Control 0, Bits[2:0], converter sampling rate. Table 18 and Table 19 depict example sampling rate settings. The (1 × 256) case is the base sampling rate. Table 18. Sampling Rates for 256 × 48 kHz Core Clock

12.288 MHz (1 × 256) 48 kHz

Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock

Figure 33. Differential Input Configuration (ADCs) with selectable oversampling rates of either 64× or 128×. full-scale value result in clipping and distortion. ADC digital attenuator, for right channel digital volume control. Bit 5, high-pass filter select, where it can be enabled or disabled.

Figure 37. I2C Write to ADAU1382 Clocking

0 ADDR0ADDR1

Figure 38. I2C Read from ADAU1382 Clocking

ADAU1382 can be taken out of SPI mode only by a full reset. (Logic 1) or a write (Logic 0). Table 23. SPI Address Byte Format word to a full 2-byte length. SPI operation to the parameter memory is shown in Figure 43. device at higher data rates than reading data out of the device.

• The ADAU1382 must have finished its initialization, including power-on reset, PLL lock, and self-boot.
• The core clock must be enabled (Register 16384 (0x4000), clock control, Bit 0, core clock enable, set to 1).
• The memory controller must be powered (Register 16512 (0x4080), Digital Power-Down 0, Bit 6, memory controller, set to 1).
• The sound engine must be powered (Register 16512 (0x4080), Digital Power-Down 0, Bit 0, sound engine, set to 1).

Table 24. Generic Control Word Format

first format, unless otherwise configured in the control registers. (0x4018), Converter Control 1. always be both master or both slave. either as a 50% duty cycle clock or as a bit-wide pulse. to properly align the LRCLK signal to the serial data stream. Figure 45. TDM Pulse Mode LRCLK Capacitor Alignment The ADAU1382 TDM implementation is a TDM audio stream. ance during periods when it is not transmitting data. Table 25. Serial Output Port Master/Slave Mode Capabilities Table 26. Data Format Configurations

64 Delayed from LRCLK edge

64 Aligned with LRCLK edge

Figure 46. I2S Mode—16 Bits to 24 Bits per Channel Figure 47. Left-Justified Mode—16 Bits to 24 Bits per Channel Figure 48. Right-Justified Mode—16 Bits to 24 Bits per Channel

32 BCLKs

256 BCLKs

Figure 49. TDM Mode Figure 50. TDM Mode with Pulse Word Clock

Rev. 0 | Page 40 of 84 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the general- purpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial data/GPIO pin configuration. The GPIO pins can be used as either inputs or outputs. These pins are readable and can be set either through the control interface or directly by the sound engine. When set as inputs, these pins can be used with push-button switches or rotary encoders to control sound engine program settings. Digital outputs can be used to drive LEDs or external logic to indicate the status of internal signals and control other devices. Examples of this use include indicating signal overload, signal present, and button press confirmation. When set as an output, each pin can typically drive 2 mA. This is enough current to directly drive some high efficiency LEDs. Standard LEDs require about 20 mA of current and can be driven from a GPIO output with an external transistor or buffer. Because of issues that may arise from simultaneously driving or sinking a large current on many pins, care should be taken in the application design to avoid connecting high efficiency LEDs directly to many or all of the GPIO pins. If many LEDs are required, use an external driver. When the GPIO pins are set as open-collector outputs, they should be pulled up to a maximum voltage of what is set on IOVDD. The configuration of the GPIO functions is set up in Register 16582 to Register 16586 (0x40C6 to 0x40CA), GPIO pin control. GPIOs Set from Control Port The GPIO pins can also be set to be directly controlled from the I 2C/SPI control port. When the pins are set into this mode, five memory locations are enabled for the GPIO pin settings (see Table 68). The physical settings on the GPIO pins mirror the settings of the LSB of these 4-byte-wide memory locations.

The processing flow is outlined in Figure 51. signal processing parameter values, such as filter coefficients. time during operation of the sound engine. Figure 51. Sound Engine Signal Processing Flow

Rev. 0| Page 43 of 84 CONTROL REGISTER MAP All registers except the PLL control register are 1-byte write and read registers. Table 27. Address Hex Decimal Name 0x4000 16384 Clock control 0x4001 16385 Regulator control 0x4002 16386 PLL control (48-bit register) 0x4008 16392 Digital microphone and analog beep control 0x4009 16393 Record power management 0x400E 16398 Record gain left PGA 0x400F 16399 Record gain right PGA 0x4010 16400 Microphone bias control and beep enable 0x4015 16405 Serial Port Control 0 0x4016 16406 Serial Port Control 1 0x4017 16407 Converter Control 0 0x4018 16408 Converter Control 1 0x4019 16409 ADC control 0x401A 16410 Left ADC attenuator 0x401B 16411 Right ADC attenuator 0x401C 16412 Playback mixer left control 0x401E 16414 Playback mixer right control 0x401F 16415 Playback mono mixer control 0x4020 16416 Playback clamp amplifier control 0x4025 16421 Left line output mute 0x4026 16422 Right line output mute 0x4027 16423 Playback speaker output control 0x4028 16424 Beep zero-crossing detector control 0x4029 16425 Playback power management 0x402A 16426 DAC control 0x402B 16427 Left DAC attenuator 0x402C 16428 Right DAC attenuator 0x402D 16429 Serial Port Pad Control 0 0x402E 16430 Serial Port Pad Control 1 0x402F 16431 Communication Port Pad Control 0 0x4030 16432 Communication Port Pad Control 1 0x4031 16433 MCKO control 0x4080 16512 Digital Power-Down 0 0x4081 16513 Digital Power-Down 1 0x40C6 to 0x40CA 16582 to 16586 GPIO pin control 0x03E8 to 0x03EC 1000 to 1004 GPIO pin value registers 0x40E9 to 0x40EA 16617 to 16618 Nonmodulo registers 0x40EB 16619 Sound engine frame rate 0x40F2 16626 Serial input route control 0x40F3 16627 Serial output route control 0x40F4 16628 Serial data/GPIO pin configuration 0x40F6 16630 Sound engine run 0x40F8 16632 Serial port sampling rate

tionally, the MCKO (master clock output) pin can be configured. MCKO pin can be used to provide digital microphones with a clock. This bit enables or disables the MCKO pin. the PLL is always 1024 × fS, and Bits[2:1] should be set to 11. the Bits[2:1], Input Master Clock Frequency section. This bit enables the internal master clock to start the IC. Table 28. Clock Control Register

7 Reserved

4 MCKO enable 0

3 Clock source select 0

0 Core clock enable 0

Table 29. Core Clock Output for fS = 44.1 kHz Table 30. Core Clock Output for fS = 48 kHz

output level when the device begins to process audio is 1.5 V . for either fractional or integer-N type MCLK inputs. back divider. This is concatenated with Denominator LSB, M[7:0]. back divider. This is concatenated with Denominator MSB, M[15:8]. back divider. This is concatenated with Numerator LSB, N[7:0]. back divider. This is concatenated with Numerator MSB, N[15:8]. PLL operation. This value must be between 2 and 8. This selects the type of PLL operation, fractional or integer-N. addition of the integer part (R) and fractional part (N/M).

12.288 MHz, and f

In this case, the input divider is X = 1. uses the parameters to emulate the required 12.288 MHz clock. PLL type bit must be set for integer-N. indicates that the PLL has locked to the input master clock. Table 31. Regulator Control Register

0 Reserved

Table 32. PLL Control Register

15 Reserved

8 PLL type 1

1 PLL lock (read only) 1

0 PLL enable 1

Table 34. Fractional PLL Parameter Settings for fS = 48 kHz (fS = 48 kHz, Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz)

This bit mutes the beep input. Table 35. Digital Microphone and Analog Beep Control Register

3 Beep input mute 0

a 2 μA, and extreme power saving has a base current of 1.5 μA. with the trade-off of higher power consumption. THD + N performance at 3.3 V AVDD1. Table 36. Record Power Management Register

These bits set the left channel analog microphone input PGA gain. the PGA is switched to common mode. This bit mutes the left channel input PGA. Table 37. Record Gain Left PGA Register

2 Single-ended left input enable 0

1 Record path left mute 0

0 Left PGA enable 0

These bits set the right channel analog microphone input PGA gain. the PGA is switched to common mode. This bit mutes the entire right channel input PGA. This bit enables the right channel PGA. Table 38. Record Gain Right PGA Register

2 Single-ended right input enable 0

1 Record path right mute 0

0 Right PGA enable 0

This bit enables the beep signal, which is input to the BEEP pin. Setting this bit to 0 mutes the beep signal for all output paths. by offering more current to the microphone. AVDD1. A higher bias contributes to a higher microphone gain. The maximum current that can be drawn from MICBIAS is 5 mA. This bit enables the MICBIAS output. Table 39. Microphone Bias Control and Beep Enable Register

4 Beep input enable 0

3 Microphone high performance 0

2 Microphone gain 0

1 Reserved

0 Microphone bias enable 0

50% duty cycle waveform or a pulse synchronization waveform. wide to guarantee proper data transfer. (see Figure 56). Standard I2S signals use negative BCLK polarity. 2S signals use negative LRCLK polarity. when it is not outputting data. Table 40. Serial Port Control 0 Register

5 LRCLK mode 0

4 BCLK polarity 0

3 LRCLK polarity 0

0 Serial data port mode 0

of different settings for these bits. a setting of 0, and Figure 63 shows a setting of 1. shows a setting of 0, and Figure 63 shows a setting of 1. configuration. In Figure 64, M stands for MSB, and L stands for LSB. exceed the boundaries of the frame clock period. stream with 64 BCLK cycles per frame. Table 41. Serial Port Control 1 Register

4 ADC channel position in TDM 0

3 DAC channel position in TDM 0

2 MSB position 0

quality but increases power consumption. quality but increases power consumption. relative to the sound engine’s audio sample rate. Table 42. Converter Control 0 Register

4 DAC oversampling ratio 0

3 ADC oversampling ratio 0

Table 43. Converter Control 1 Register

frequency scales linearly with fS. This bit must be enabled to use the digital microphone inputs. can be enabled or disabled individually. Table 44. ADC Control Register

6 Invert input polarity 0

5 High-pass filter select 0

4 Digital microphone data polarity swap 0

3 Digital microphone channel swap 0

2 Digital microphone input select 0

control from 0 dB to −95.625 dB, in increments of 0.375 dB. control from 0 dB to −95.625 dB, in increments of 0.375 dB. Table 45. Left ADC Attenuator Register Table 46. Right ADC Attenuator Register

engine or a slew mute using the DAC attenuator. 3 dB at a time in order to avoid audible artifacts on the output. engine or a slew mute using the DAC attenuator. 3 dB at a time in order to avoid audible artifacts on the output. Table 47. Playback Mixer Left Control Register

5 Left DAC mute 0

Table 48. Playback Mixer Right Control Register

6 Right DAC mute 0

5 Reserved

the DAC. Use of this bit does not result in power savings. the DAC. Use of this bit does not result in power savings. These bits set the gain of the beep output signal in mono mode. the timeout occurs, whichever comes first. This bit mutes the mono line output. The playback clamp amp is an amplifier on the line output path. the line outputs are reenabled. depending on operating conditions, but saves several microamps. This bit enables or disables the clamp amp. It is enabled by default. Table 49. Playback Mono Mixer Control Register

7 Left DAC mute 0

0 Mono output mute (active low) 0

Table 50. Playback Clamp Amplifier Control Register

1 Clamp amplifier power saving mode 1

0 Clamp amplifier control 0

Table 51. Left Line Output Mute Register

1 Left line output mute (active low) 0

Table 52. Right Line Output Mute Register

1 Right line output mute (active low) 0

initialization and not altered during operation of the system. up and power-down sequences shown in Figure 35 and Figure 36. right playback beep gain, and mono playback beep gain). Table 53. Playback Speaker Output Control Register

0 Speaker output enable 0

Table 54. Beep Zero-Crossing Detector Control Register

0 Zero-crossing detector enable 1

audio quality but also uses the most current. the playback mixers and amplifiers. This bit enables the playback mixers and amplifiers. This bit enables the playback mixers and amplifiers. Table 55. Playback Power Management Register

1 Back-end right enable 0

0 Back-end left enable 0

the mixed mono signal on both the left and right outputs. preemphasized signal is input to the DACs. These bits allow the DACs to be individually enabled or disabled. Disabling unused DACs can result in significant power savings. Table 56. DAC Control Register

5 Invert input polarity 0

2 DAC de-emphasis filter enable 0

control from 0 dB to −95.625 dB, in increments of 0.375 dB. control from 0 dB to −95.625 dB, in increments of 0.375 dB. Table 57. Left DAC Attenuator Register Table 58. Right DAC Attenuator Register

Table 59. Serial Port Pad Control 0 Register

2 mA when IOVDD = 3.3 V , or 0.75 mA when IOVDD = 1.8 V . 2 mA when IOVDD = 3.3 V , or 0.75 mA when IOVDD = 1.8 V . Table 60. Serial Port Pad Control 1 Register

3 ADC_SDATA pin drive strength 0

2 DAC_SDATA pin drive strength 0

1 LRCLK pin drive strength 0

0 BCLK pin drive strength 0

Table 61. Communication Port Pad Control 0 Register

2 mA when IOVDD = 3.3 V , or 0.75 mA when IOVDD = 1.8 V . Table 62. Communication Port Pad Control 1 Register

3 CDATA pin drive strength 0

2 CLATCH pin drive strength 0

1 SCL/CCLK pin drive strength 0

0 SDA/COUT pin drive strength 0

2 mA when IOVDD = 3.3 V , or 0.75 mA when IOVDD = 1.8 V . This bit enables or disables a weak pull-up device on the pad. The effective resistance of the pull-up is nominally 240 kΩ. This bit enables or disables a weak pull-down device on the pad. The effective resistance of the pull-down is nominally 240 kΩ. Table 63. MCKO Control Register

2 MCKO pin drive strength 0

1 MCKO pull-up enable (active low) 0

0 MCKO pull-down enable 1

access via the control port. transfer—disables the serial ports. path, which goes from the sound engine to the serial port output. passed through the ADAU1382. process audio and change parameter values. Table 64. Digital Power-Down 0 Register

7 ADC engine 0

6 Memory controller 0

5 Clock domain transfer (when using the serial ports) 0

4 Serial ports 0

3 Serial output routing 0

2 Serial input routing 0

1 Serial port, ADC, DAC, and frame pulse clock generator 0

0 Sound engine 0

the output. This bit should be set to 1 at all times. Setting this bit to 0 disables the digital microphone input. Setting this bit to 0 disables the DACs. Table 65. Digital Power-Down 1 Register

3 Output precharge 1

2 Zero-crossing detector 1

1 Digital microphone 0

0 DAC engine 0

serial data/GPIO pin configuration. Pin 7 is a dedicated GPIO. should be set as 1011 or 1100 (outputs set by the sound engine). configured as 1001 or 1010 (outputs set by the I2C/SPI port). the control port. The corresponding addresses are listed in Table 68. Table 66. GPIO Pin Control Register Table 67. GPIO Pin Functions

0000 Input without debounce

0100 Input with debounce (5 ms)

0101 Input with debounce (10 ms)

0110 Input with debounce (20 ms)

0111 Input with debounce (40 ms)

1000 Input controlled by I2C/SPI port

1001 Output set by I2C/SPI port with pull-up

1010 Output set by I2C/SPI port without pull-up

1011 Output set by engine with pull-up

1100 Output set by engine without pull-up

1101 Reserved

1110 Output CRC error (sticky)

1111 Output watchdog error (sticky)

Table 68. Addresses of GPIO Pin Value Registers

to finish processing the current frame before halting. Table 69. Nonmodulo Registers Table 70. Sound Engine Frame Rate Register

These bits select which serial data input channels are routed to the DACs (see Figure 71). Table 71. Serial Input Route Control Register 1 Lx = left side of Channel x; Rx = right side of Channel x.

These bits select where the ADC outputs are routed in the serial data stream (see Figure 71). Table 72. Serial Output Route Control Register 1 Lx = left side of Channel x; Rx = right side of Channel x. Figure 71. Serial Port Routing Control

remain LRCLK, BCLK, or serial port data pins, respectively. the sound engine goes into standby mode.

1. Set the sound engine frame rate in Register 16619 to
2. Set the sound engine run bit in Register 16630 to 0x00.
3. Set the sound engine frame rate in Register 16619 to an
4. Set the sound engine run bit in Register 16630 to 0x01.

sampling rates should be equal. Table 73. Serial Data/GPIO Pin Configuration Register

3 GPIO0 0

2 GPIO1 0

1 GPIO2 0

0 GPIO3 0

Table 74. Sound Engine Run Register

0 Sound engine run 0

Table 75. Serial Port Sampling Rate Register

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

3.50 REF

0.60 MAX

0.25 MIN

Figure 72. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 84 of 84 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D08427-0-10/09(0)