ADAU1361_V01 AD | Alldatasheet
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Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL Rev. E DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►24-bit stereo audio ADC and DAC: >98 dB SNR ►Sampling rates from 8 kHz to 96 kHz ►Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V ►6 analog input pins, configurable for single-ended or differential inputs ►Flexible analog input/output mixers ►Stereo digital microphone input ►Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone output driver ►PLL supporting input clocks from 8 MHz to 27 MHz ►Analog automatic level control (ALC) ►Microphone bias reference voltage ►Analog and digital I/O: 1.8 V to 3.65 V ►I2C and SPI control interfaces ►Digital audio serial data I/O: stereo and time-division multiplexing (TDM) modes ►Software-controllable clickless mute ►Software power-down ►32-lead, 5 mm × 5 mm LFCSP ►−40°C to +85°C operating temperature range
APPLICATIONS
►Smartphones/multimedia phones ►Digital still cameras/digital video cameras ►Portable media players/portable audio players ►Phone accessories products GENERAL DESCRIPTION The ADAU1361 is a low power, stereo audio codec that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The ADAU1361 is ideal for battery-powered audio and telephony applications. The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1361 includes a stereo digital microphone input. The ADAU1361 includes five high power output drivers (two differ- ential and three single-ended), supporting stereo head-phones, an earpiece, or other output transducer. AC-coupled or capless config- urations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio. The serial control bus supports the I2C and SPI protocols. The seri- al audio bus is programmable for I2S, left-/right-justified, and TDM modes. A programmable PLL supports flexible clock generation for all standard integer rates and fractional main clocks from 8 MHz to 27 MHz. FUNCTIONAL BLOCK DIAGRAM Figure 1.
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REVISION HISTORY
8/2024—Rev. D to Rev. E
analog.com Rev. E | 3 of 78 Supply voltage (AVDD) = 3.3 V, TA = 25°C, main clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V, unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC performance excludes mixers and PGA ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Single-Ended Line Input −12 dB gain 83 kΩ 0 dB gain 21 kΩ 6 dB gain 10.5 kΩ PGA Inverting Inputs −12 dB gain 84.5 kΩ 0 dB gain 53 kΩ 35.25 dB gain 2 kΩ PGA Noninverting Inputs All gains 105 kΩ SINGLE-ENDED LINE INPUT Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 99 dB No Filter (RMS) AVDD = 1.8 V 91 dB AVDD = 3.3 V 96 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −90 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 99 dB No Filter (RMS) AVDD = 1.8 V 91 dB AVDD = 3.3 V 96 dB Gain per Step 3 dB Total Gain Range −12 +6 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −12 % Interchannel Isolation 68 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 65 dB 100 mV p-p @ 1 kHz 67 dB
Table 1. (Continued)
analog.com Rev. E | 7 of 78 TYPICAL CURRENT CONSUMPTION Main clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2. Table 3. Operating Voltage Audio Path Clock Generation Typical AVDD Current Consumption (mA) AVDD = IOVDD = 3.3 V Record stereo differential to ADC Direct MCLK 5.24 Integer PLL 6.57 DAC stereo playback to line output (10 kΩ) Direct MCLK 5.55 Integer PLL 6.90 DAC stereo playback to headphone (16 Ω) Direct MCLK 55.5 Integer PLL 56.8 DAC stereo playback to headphone (32 Ω) Direct MCLK 30.9 Integer PLL 32.25 DAC stereo playback to capless headphone (32 Ω) Direct MCLK 56.75 Integer PLL 58 Record aux stereo bypass to line output (10 kΩ) Direct MCLK 1.9 Integer PLL 3.3 AVDD = IOVDD = 1.8 V Record stereo differential to ADC Direct MCLK 4.25 Integer PLL 5.55 DAC stereo playback to line output (10 kΩ) Direct MCLK 4.7 Integer PLL 5.7 DAC stereo playback to headphone (16 Ω) Direct MCLK 30.81 Integer PLL 32 DAC stereo playback to headphone (32 Ω) Direct MCLK 18.3 Integer PLL 19.5 DAC stereo playback to capless headphone (32 Ω) Direct MCLK 32.6 Integer PLL 33.7 Record aux stereo bypass to line output (10 kΩ) Direct MCLK 1.9 Integer PLL 3.07 TYPICAL POWER MANAGEMENT MEASUREMENTS Main clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC input @ 0 dBFS. In Table 4, the mixer boost and power management conditions are set for MXBIAS[1:0], ADCBIAS[1:0], HPBIAS[1:0], and DACBIAS[1:0]. RBIAS[1:0] and PBIAS[1:0] do not have an extreme power saving mode and are therefore set for power saving mode in the extreme power saving rows in Table 4. Table 4. Operating Voltage Power Management SettingMixer Boost Setting Typical AVDD Current Consumption (mA) Typical ADC THD + N (dB) Typical Line Output THD + N (dB) AVDD = IOVDD = 3.3 V Normal (default) Normal operation 9.6 −91 −92.5 Boost Level 1 9.75 −91.5 −92.5 Boost Level 2 9.92 −91.5 −92.5 Boost Level 3 10.25 −91.5 −92.5 Extreme power saving Normal operation 7.09 −84.5 −87 Boost Level 1 7.19 −84.8 −87.1 Boost Level 2 7.29 −84.8 −87.1 Boost Level 3 7.49 −85 −87.1
Table 4. (Continued)
Table 5. (Continued) Table 7. Digital Timing tMP 74 488 ns MCLK period, 256 × fS mode. tMP 37 244 ns MCLK period, 512 × fS mode. tMP 24.7 162.7 ns MCLK period, 768 × fS mode. tMP 18.5 122 ns MCLK period, 1024 × fS mode. tBIL 5 ns BCLK pulse width low. tBIH 5 ns BCLK pulse width high. tLIS 5 ns LRCLK setup. Time to BCLK rising. tLIH 5 ns LRCLK hold. Time from BCLK rising. tSIS 5 ns DAC_SDATA setup. Time to BCLK rising. tSIH 5 ns DAC_SDATA hold. Time from BCLK rising. fCCLK 10 MHz CCLK frequency. tCCPL 10 ns CCLK pulse width low.
Table 7. Digital Timing (Continued) tCCPH 10 ns CCLK pulse width high. tCLS 5 ns CLATCH setup. Time to CCLK rising. tCLH 10 ns CLATCH hold. Time from CCLK rising. tCLPH 10 ns CLATCH pulse width high. tCDS 5 ns CDATA setup. Time to CCLK rising. tCDH 5 ns CDATA hold. Time from CCLK rising. tCOD 50 ns COUT three-stated. Time from CLATCH rising. tSCS 0.6 µs Setup time; relevant for repeated start condition. tSCH 0.6 µs Hold time. After this period, the first clock is generated. tBFT 0.6 µs Bus-free time. Time between stop and start. DIGITAL MICROPHONE RLOAD = 1 MΩ, CLOAD = 14 pF. tDCF 10 ns Digital microphone clock fall time. tDCR 10 ns Digital microphone clock rise time. tDDV 22 30 ns Digital microphone delay time for valid data. tDDH 0 12 ns Digital microphone delay time for data three-stated. Figure 2. Serial Input Port Timing
ing conditions for extended periods may affect product reliability. Table 9. Thermal Resistance damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 7. Pin Configuration Table 10. Pin Function Descriptions decoupled to DGND with a 100 nF capacitor and a 10 μF capacitor. 2 MCLK D_IN External Main Clock Input. the address and read/write bit that are sent at the beginning of the SPI transaction. 4 JACKDET/MICIN D_IN Detect Insertion/Removal of Headphone Plug (JACKDET).Digital Microphone Stereo Input (MICIN). 5 MICBIAS A_OUT Bias Voltage for Electret Microphone. 6 LAUX A_IN Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2. circuits, as long as they are not drawing current from CM (for example, the noninverting input of an op amp). decoupled locally to AVDD with a 100 nF capacitor. 10 LINP A_IN Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2. 11 LINN A_IN Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2. 12 RINP A_IN Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2. 13 RINN A_IN Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2. 14 RAUX A_IN Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2. 15 ROUTP A_OUT Right Line Output, Positive. Biased at AVDD/2. 16 ROUTN A_OUT Right Line Output, Negative. Biased at AVDD/2. 17 LOUTN A_OUT Left Line Output, Negative. Biased at AVDD/2. 18 LOUTP A_OUT Left Line Output, Positive. Biased at AVDD/2. 19 RHP A_OUT Right Headphone Output. Biased at AVDD/2. 20 LHP A_OUT Left Headphone Output. Biased at AVDD/2. 21 MONOOUT A_OUT Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono output. decoupled locally to AVDD with a 100 nF capacitor. decoupled locally to AGND with a 100 nF capacitor.
Table 10. Pin Function Descriptions (Continued) require an external supply. DVDDOUT should be decoupled to DGND with a 100 nF capacitor and a 10 μF capacitor. decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 μF capacitors. 26 ADC_SDATA D_OUT ADC Serial Output Data. 27 DAC_SDATA D_IN DAC Serial Input Data. 28 BCLK D_IO Serial Data Port Bit Clock. 29 LRCLK D_IO Serial Data Port Frame Clock. 30 ADDR1/CDATA D_IN I2C Address Bit 1 (ADDR1). three-state when an SPI read is not active. the Exposed Pad PCB Design section for more information. 1 A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, D_OUT = digital output, PWR = power.
Figure 25. System Block Diagram
Figure 26. System Block Diagram with Analog Microphones
Figure 27. System Block Diagram with Digital Microphones and SSM2306 Class-D Speaker Driver
analog.com Rev. E | 21 of 78 The ADAU1361 is an audio codec that offers high quality audio, low power, and small package size. The stereo ADC and stereo DAC each have an SNR of at least +98 dB and a THD + N of at least −90 dB. The serial data port is compatible with I2S, left-justified, right-justified, and TDM modes for interfacing to digital audio data. The operating voltage range is 1.8 V to 3.65 V, with an on-board regulator generating the internal digital supply voltage. The record signal path includes very flexible input configurations that can accept differential and single-ended analog microphone inputs as well as a digital microphone input. A microphone bias pin provides seamless interfacing to electret microphones. Input configurations can accept up to six single-ended analog signals or variations of stereo differential or stereo single-ended signals with two additional auxiliary single-ended inputs. Each input signal has its own programmable gain amplifier (PGA) for volume adjustment and can be routed directly to the playback path output mixers, bypassing the ADCs. An automatic level control (ALC) can also be implemented to keep the recording volume constant. The ADCs and DACs are high quality, 24-bit Σ-Δ converters that operate at selectable 64× or 128× oversampling ratios. The base sampling rate of the converters is set by the input clock rate and can be further scaled with the converter control register settings. The converters can operate at sampling frequencies from 8 kHz to 96 kHz. The ADCs and DACs also include very fine-step digital volume controls. The playback path allows input signals and DAC outputs to be mixed into various output configurations. Headphone drivers are available for a stereo headphone output, and the other output pins are capable of differentially driving an earpiece speaker. Capless headphone outputs are possible with the use of the mono output as a virtual ground connection. The stereo line outputs can be used as either single-ended or differential outputs and as an optional mix-down mono output. The ADAU1361 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 8 MHz to 27 MHz. The ADAU1361 is provided in a small, 32-lead, 5 mm × 5 mm LFCSP with an exposed bottom pad.
to the proper initiation of the system.
- Apply power to the ADAU1361.
- Lock the PLL to the input clock (if using the PLL).
- Load the register settings.
documented in the register map (see the Control Registers section). Figure 28. Power-On Reset Sequence times are provided in Table 11. Table 11. PLL Lock Times ation. See the Control Registers section for more information. for graphs of these filters. internal regulator. This regulator generates a 1.5 V supply internally. be connected between this pin and DGND. decoupled to DGND with a 100 nF capacitor and a 10 μF capacitor. enable bit (COREN) is asserted. core clock to all the internal blocks of the ADAU1361.
STARTUP, INITIALIZATION, AND POWER analog.com Rev. E | 23 of 78 PLL Lock Acquisition During the lock acquisition period, only Register R0 (Address 0x4000) and Register R1 (Address 0x4002) are accessible through the control port. Because all other registers require a valid main clock for reading and writing, do not attempt to access any other register. Any read or write is prohibited until the core clock enable bit (COREN) and the lock bit are both asserted. To program the PLL during initialization or reconfiguration of the clock setting, the following procedure must be followed: 1. Power down the PLL. 2. Reset the PLL control register. 3. Start the PLL. 4. Poll the lock bit. 5. Assert the core clock enable bit after the PLL lock is acquired. The PLL control register (Register R1, Address 0x4002) is a 48-bit register where all bits must be written with a single continuous write to the control port.
Figure 29. Clock Tree Diagram Address 0x4000) determines the clock source. clock rate and the base sampling frequency, fS. the desired base sampling frequency. Table 12. Clock Control Register (Register R0, Address 0x4000)
3 CLKSRC 0: Direct from MCLK pin (default) 1: PLL clock
0 COREN 0: Core clock disabled (default)1: Core clock
the base sampling frequency. Table 13. 48 kHz Base Sampling Rate Divisions Table 13. 48 kHz Base Sampling Rate Divisions (Continued) Table 14. 44.1 kHz Base Sampling Rate Divisions The PLL uses the MCLK as a reference to generate the core clock. frequencies in the range of 8 MHz to 27 MHz. continuous write to the control port. Figure 30. PLL Block Diagram In integer mode, the values set for N and M are ignored.
sampling rates can be found in Table 16 and Table 17. Table 15. PLL Control Register (Register R1, Address 0x4002)
8 Type PLL operation mode
1 Lock PLL lock (read-only bit)
0 PLLEN PLL enable
Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS) Table 17. Fractional PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
Table 17. Fractional PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS) (Continued) Table 18. Integer PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
analog.com Rev. E | 29 of 78 boost provides two different voltage biases: 0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-mance bit increases supply current to the microphone bias circuit to decrease rms input noise. The MICBIAS pin can also be used to cleanly supply voltage to digital microphones or analog microphones with separate power supply pins. ANALOG-TO-DIGITAL CONVERTERS The ADAU1361 uses two 24-bit Σ-Δ analog-to-digital con-verters (ADCs) with selectable oversampling ratios of 64× or 128× (select- ed by Bit 3 in Register R17, Address 0x4017). ADC Full-Scale Level The full-scale input to the ADCs (0 dBFS) depends on AVDD. At AVDD = 3.3 V, the full-scale input level is 1.0 V rms. This full-scale analog input outputs a digital signal at −1.38 dBFS. This gain offset is built into the ADAU1361 to prevent clipping. The full-scale input level scales linearly with the level of AVDD. For single-ended and pseudo-differential signals, the full-scale val- ue corresponds to the signal level at the pins, 0 dBFS. The full differential full-scale input level is measured after the differential amplifier, which corresponds to −6 dBFS at each pin. Signal levels above the full-scale value cause the ADCs to clip. Digital ADC Volume Control The digital ADC volume can be attenuated using Register R20 (left input digital volume register, Address 0x401A) and Register R21 (right input digital volume register, Address 0x401B). High-Pass Filter By default, a high-pass filter is used in the ADC path to remove dc offsets; this filter can be enabled or disabled in Register R19 (ADC control register, Address 0x4019). At fS = 48 kHz, the corner frequency of this high-pass filter is 2 Hz.
Figure 43. Playback Signal Path analog output pins are biased at AVDD/2. output is inverted. The DACs are noninverting. ►Mix signals from the record path and the DACs. ►Mix or swap the left and right channels. ►Mix a mono signal or generate a common-mode output. path can be boosted or cut before the playback mixer. 0x4024). The headphone outputs can drive a load of at least 16 Ω. click suppression register, Address 0x4028).
(playback pop/click suppression register, Address 0x4028). time, the POPMODE bit can be set to low power mode. outputs after the changes are made. output impedance of the line outputs is approximately 1 kΩ. ROUTN should be left unconnected. The volume controls for these outputs range from −57 dB to +6 dB. and differential output signals to achieve up to 6 dBV (2.0 V rms). Figure 47. Differential Line Output Configuration
pulling the CLATCH pin low three times. 0x4000) and Register R1 (Address 0x4002). Table 20. Control Port Pin Functions written immediately without sending its two-byte address. ADAU1361, and a read returns a single byte 0x00. Table 21. The address resides in the first seven bits of the I2C write. Table 21. ADAU1361 I2C Address and Read/Write Byte Format be higher than IOVDD (1.8 V to 3.3 V). the bus at this point and return to the idle condition. the timing of an I2C write, and Figure 49 shows an I2C read.
a 4-channel TDM stream to interface to external ADCs or DACs. converter control registers, Address 0x4015 to Address 0x4018). connected between the LRCLK pin and ground (see Figure 56). properly align the LRCLK signal to the serial data stream. Figure 56. LRCLK Capacitor Alignment, TDM Pulse Mode In TDM mode, the ADAU1361 can be a main for fS up to 48 kHz. Table 24 lists the modes in which the serial output port can function. Table 24. Serial Output Port Main/Subordinate Mode Capabilities Table 25. Data Format Configurations
16 BCLKs
1 BCLK
Figure 57. I2S Mode—16 Bits to 24 Bits per Channel Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel
Table 26. Register Map
Table 26. Register Map (Continued) All registers except for the PLL control register are 1-byte write and read registers. Table 27. Clock Control Register 3 CLKSRC Clock source select. 0 = direct from MCLK pin (default). [2:1] INFREQ[1:0] Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is automatically set to 1024 × fS. 0 COREN Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled). 0 = core clock disabled (default).
0 M[15:8]
1 M[7:0]
2 N[15:8]
3 N[7:0]
4 Reserved R[3:0] X[1:0] Type
5 Reserved Lock PLLEN
Table 28. PLL Control Register 0 [7:0] M[15:8] PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number. 1 [7:0] M[7:0] PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
Table 28. PLL Control Register (Continued) 2 [7:0] N[15:8] PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number. 3 [7:0] N[7:0] PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number. 4 [6:3] R[3:0] PLL integer setting. 4 [2:1] X[1:0] PLL input clock divider. 4 0 Type Type of PLL. When set to integer mode, the values of M and N are ignored. 5 1 Lock PLL lock. This read-only bit is flagged when the PLL has finished locking. Table 29. Digital Microphone/Jack Detection Control Register [7:6] JDDB[1:0] Jack detect debounce time.
Table 29. Digital Microphone/Jack Detection Control Register (Continued) configures the pin for a digital microphone input.
00 Jack detect off (default)
01 Jack detect on
10 Digital microphone input
11 Reserved
0 JDPOL Jack detect polarity. Detects high or low signal. 0 = detect high signal (default). performance with the trade-off of higher power consumption. Table 30. Record Power Management Register
00 Normal operation (default)
01 Boost Level 1
10 Boost Level 2
11 Boost Level 3
[4:3] ADCBIAS[1:0] ADC bias control. Sets the bias current for the ADCs based on the mode of operation selected.
01 Extreme power saving
10 Enhanced performance
11 Power saving
[2:1] RBIAS[1:0] Record path bias control. Sets the bias current for the PGAs and mixers in the record path.
01 Reserved
This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1.
Table 31. Record Mixer Left (Mixer 1) Control 0 Register [6:4] LINPG[2:0] Gain for a left channel single-ended input from the LINP pin, input to Mixer 1.
000 Mute (default)
[3:1] LINNG[2:0] Gain for a left channel single-ended input from the LINN pin, input to Mixer 1.
0 MX1EN
Left channel mixer enable in the record path. Referred to as Mixer 1. 0 = mixer disabled (default). This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the record path. The left channel record mixer is referred to as Mixer 1. Table 32. Record Mixer Left (Mixer 1) Control 1 Register
00 Mute (default)
[2:0] MX1AUXG[2:0] Left single-ended auxiliary input gain from the LAUX pin in the record path, input to Mixer 1.
Table 32. Record Mixer Left (Mixer 1) Control 1 Register (Continued) This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as Mixer 2. Table 33. Record Mixer Right (Mixer 2) Control 0 Register [6:4] RINPG[2:0] Gain for a right channel single-ended input from the RINP pin, input to Mixer 2. [3:1] RINNG[2:0] Gain for a right channel single-ended input from the RINN pin, input to Mixer 2.
0 MX2EN
Right channel mixer enable in the record path. Referred to as Mixer 2. 0 = mixer disabled (default). path. The right channel record mixer is referred to as Mixer 2. Table 34. Record Mixer Right (Mixer 2) Control 1 Register
Table 34. Record Mixer Right (Mixer 2) Control 1 Register (Continued) [2:0] MX2AUXG[2:0] Right single-ended auxiliary input gain from the RAUX pin in the record path, input to Mixer 2. This register enables the differential path and sets the volume control for the left differential PGA input. Table 35. Left Differential Input Volume Control Register [7:2] LDVOL[5:0] Left channel differential PGA input volume control. The left differential input uses the LINP (positive signal) and LINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 71 for a complete list of the volume settings. 1 LDMUTE Left differential input mute control. configured as two single-ended inputs with the signals routed around the PGA. This register enables the differential path and sets the volume control for the right differential PGA input.
Table 36. Right Differential Input Volume Control Register pins. Each step corresponds to a 0.75 dB increase in gain. See Table 71 for a complete list of the volume settings. 1 RDMUTE Right differential input mute control. configured as two single-ended inputs with the signals routed around the PGA. This register controls the MICBIAS pin settings for biasing electret type analog microphones. Table 37. Record Microphone Bias Control Register 3 MPERF Microphone bias is enabled for high performance or normal operation. High performance operation sources more current to the microphone. 0 = normal operation (default). 2 MBI Microphone voltage bias as a fraction of AVDD. 0 MBIEN Enables the MICBIAS output. Table 38. ALC Control 0 Register
Table 38. ALC Control 0 Register (Continued)
11 Off
of both the left and right PGA amplifiers. These bits must be off if manual control of the volume is desired.
000 Off (default)
001 Right only
010 Left only
011 Stereo
100 Reserved
101 Reserved
110 Reserved
111 Reserved
Table 39. ALC Control 1 Register doubles with every 1-bit increase.
Table 39. ALC Control 1 Register (Continued) recommended target level is between −16 dB and −10 dB to accommodate transients without clipping the ADC. Table 40. ALC Control 2 Register for music recording is 384 ms, and a typical setting for voice recording is 24 ms.
Table 40. ALC Control 2 Register (Continued) setting for music recording is 24.58 seconds, and a typical setting for voice recording is 1.54 seconds. Table 41. ALC Control 3 Register output, fade the PGA gain to the minimum gain value, or fade then mute.
00 Hold PGA constant (default)
01 Mute ADC output (digital mute)
10 Fade to PGA minimum value (analog fade)
11 Fade then mute (analog fade/digital mute)
to a −1.5 dB change. See Table 72 for a complete list of the threshold settings.
Table 42. Serial Port Control 0 Register 7 DITHEN Dither enable is applicable only for 16-bit data width modes. 5 LRMOD LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide. 0 = 50% duty cycle (default). 4 BPOL BCLK polarity sets the BCLK edge that triggers a change in audio data. This can be set for the falling or rising edge of the BCLK. [2:1] CHPF[1:0] Channels per frame sets the number of channels per LRCLK frame.
00 Stereo (default)
01 TDM 4
10 Reserved
0 = subordinate mode (default). Table 43. Serial Port Control 1 Register [7:5] BPF[2:0] Number of bit clock cycles per LRCLK audio frame. 4 ADTDM ADC serial audio data channel position in TDM mode. 3 DATDM DAC serial audio data channel position in TDM mode.
Table 43. Serial Port Control 1 Register (Continued) 2 MSBP MSB position in the LRCLK frame. [1:0] LRDEL[1:0] Data delay from LRCLK edge (in BCLK units). Table 44. Converter Control 0 Register [6:5] DAPAIR[1:0] On-chip DAC serial data selection in TDM mode.
00 First pair (default)
01 Second pair
10 Third pair
11 Fourth pair
4 DAOSR DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz. 3 ADOSR ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz. converter sampling rates set in this register.
Table 45. Converter Control 1 Register [1:0] ADPAIR[1:0] On-chip ADC serial data selection in TDM mode. Table 46. ADC Control Register 6 ADCPOL Invert input polarity. 5 HPF ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz. 4 DMPOL Digital microphone data polarity swap. 1 = swap left and right channels. left and right channels interleaved. 0 = digital microphone inputs off, ADCs enabled (default). 1 = digital microphone inputs enabled, ADCs off. [1:0] ADCEN[1:0] ADC enable.
00 Both off (default)
01 Left on
10 Right on
11 Both on
Table 47. Left Input Digital Volume Register corresponds to a 0.375 dB step with slewing between settings. See Table 73 for a complete list of the volume settings.
Table 47. Left Input Digital Volume Register (Continued) Table 48. Right Input Digital Volume Register corresponds to a 0.375 dB step with slewing between settings. See Table 73 for a complete list of the volume settings. Table 49. Playback Mixer Left (Mixer 3) Control 0 Register 6 MX3RM Mixer input mute. Mutes the right DAC input to the left channel playback mixer (Mixer 3). 5 MX3LM Mixer input mute. Mutes the left DAC input to the left channel playback mixer (Mixer 3). [4:1] MX3AUXG[3:0] Mixer input gain. Controls the left channel auxiliary input gain to the left channel playback mixer (Mixer 3).
0000 Mute (default)
Table 49. Playback Mixer Left (Mixer 3) Control 0 Register (Continued) Table 50. Playback Mixer Left (Mixer 3) Control 1 Register left playback mixer (Mixer 3). Table 51. Playback Mixer Right (Mixer 4) Control 0 Register 6 MX4RM Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4). 5 MX4LM Mixer input mute. Mutes the left DAC input to the right channel playback mixer (Mixer 4). [4:1] MX4AUXG[3:0] Mixer input gain. Controls the right channel auxiliary input gain to the right channel playback mixer (Mixer 4).
Table 51. Playback Mixer Right (Mixer 4) Control 0 Register (Continued) Table 52. Playback Mixer Right (Mixer 4) Control 1 Register right playback mixer (Mixer 4). right playback mixer (Mixer 4).
Table 53. Playback L/R Mixer Left (Mixer 5) Line Output Control Register Table 54. Playback L/R Mixer Right (Mixer 6) Line Output Control Register
Table 55. Playback L/R Mixer Mono Output (Mixer 7) Control Register [2:1] MX7[1:0] L/R mono playback mixer (Mixer 7). Mixes the left and right playback mixers (Mixer 3 and Mixer 4) with either a 0 dB or 6 dB gain boost. Additionally, this mixer can operate as a common-mode output, which is used as the virtual ground in a capless headphone configuration.
00 Common-mode output (default)
Table 56. Playback Headphone Left Volume Control Register complete list of the volume settings. 1 LHPM Headphone mute for left channel, LHP output (active low). 0 HPEN Headphone output enable. Table 57. Playback Headphone Right Volume Control Register complete list of the volume settings.
Table 57. Playback Headphone Right Volume Control Register (Continued) 1 RHPM Headphone mute for right channel, RHP output (active low). 0 HPMODE RHP and LHP output mode. These pins can be configured for either line outputs or headphone outputs. Table 58. Playback Line Output Left Volume Control Register Table 74 for a complete list of the volume settings. 1 LOUTM Line output mute for left channel, LOUTN and LOUTP outputs (active low). 0 LOMODE Line output mode for left channel, LOUTN and LOUTP outputs. These pins can be configured for either line outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output). Table 59. Playback Line Output Right Volume Control Register Table 74 for a complete list of the volume settings.
Table 59. Playback Line Output Right Volume Control Register (Continued) 1 ROUTM Line output mute for right channel, ROUTN and ROUTP outputs (active low). outputs. To drive earpiece speakers, set this bit to 1 (headphone output). Table 60. Playback Mono Output Control Register common-mode output, volume control is disabled. See Table 74 for a complete list of the volume settings. 1 MONOM Mono output mute (active low). should be set to 1 (headphone output). Table 61. Playback Pop/Click Suppression Register charged, they can be put into low power operation. circuits increases the risk of pops and clicks. [2:1] ASLEW[1:0] Analog volume slew rate for playback volume controls.
Table 61. Playback Pop/Click Suppression Register (Continued) Table 62. Playback Power Management Register [7:6] HPBIAS[1:0] Headphone bias control. [5:4] DACBIAS[1:0] DAC bias control. [3:2] PBIAS[1:0] Playback path channel bias control. 1 PREN Playback right channel enable. 0 PLEN Playback left channel enable. Table 63. DAC Control 0 Register
01 Left channel in mono mode
10 Right channel in mono mode
Table 63. DAC Control 0 Register (Continued)
11 Both channels in mono mode
5 DACPOL Invert input polarity of the DACs. 2 DEMPH DAC de-emphasis filter enable. The de-emphasis filter is designed for use with a sampling rate of 44.1 kHz only. [1:0] DACEN[1:0] DAC enable. Table 64. DAC Control 1 Register between settings. See Table 73 for a complete list of the volume settings. Table 65. DAC Control 2 Register between settings. See Table 73 for a complete list of the volume settings.
defined state when the signal source becomes three-state. Table 66. Serial Port Pad Control Register [7:6] ADCSDP[1:0] ADC_SDATA pad pull-up/pull-down configuration.
00 Pull-up
10 None (default)
11 Pull-down
[5:4] DACSDP[1:0] DAC_SDATA pad pull-up/pull-down configuration. [3:2] LRCLKP[1:0] LRCLK pad pull-up/pull-down configuration. [1:0] BCLKP[1:0] BCLK pad pull-up/pull-down configuration. defined state when the signal source becomes three-state. Table 67. Control Port Pad Control 0 Register [7:6] CDATP[1:0] CDATA pad pull-up/pull-down configuration.
Table 67. Control Port Pad Control 0 Register (Continued) [5:4] CLCHP[1:0] CLATCH pad pull-up/pull-down configuration. [3:2] SCLP[1:0] SCL/CCLK pad pull-up/pull-down configuration. [1:0] SDAP[1:0] SDA/COUT pad pull-up/pull-down configuration. useful for generating a stronger ACK pulse in I2C mode, if needed. Table 68. Control Port Pad Control 1 Register 0 SDASTR SDA/COUT pin drive strength. With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. Table 69. Jack Detect Pin Control Register 5 JDSTR JACKDET/MICIN pin drive strength.
Table 69. Jack Detect Pin Control Register (Continued) [3:2] JDP[1:0] JACKDET/MICIN pad pull-up/pull-down configuration. or bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in subordinate mode. associated dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device. dejitter window size to the default value of 3. Table 70. Dejitter Control Register [7:0] DEJIT[7:0] Dejitter window size. Table 71. R8 and R9 Volume Settings
Table 71. R8 and R9 Volume Settings (Continued)
Table 72. R14 Noise Gate Threshold Table 73. R20, R21, R37, and R38 Volume Settings
Table 73. R20, R21, R37, and R38 Volume Settings (Continued)
Table 74. R29 through R33 Volume Settings
Table 74. R29 through R33 Volume Settings (Continued)
©2009-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. E | 78 of 78 Package Drawing (Option) Package Type Package Description CP-32-4 LFCSP 32-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADAU1361BCPZ −40°C to +85°C 32-Lead LFCSP Tray, 490 CP-32-4 ADAU1361BCPZ-R7 −40°C to +85°C 32-Lead LFCSP Reel, 1500 CP-32-4 ADAU1361BCPZ-RL −40°C to +85°C 32-Lead LFCSP Reel, 5000 CP-32-4 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-ADAU1361Z Evaluation Board EVAL-ADAU1361UZ Evaluation Board ADAU1361-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).