ADATE302-02BSVZ

ADATE302-02_17 AD | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 59

Technical content

500 MHz Dual Integrated DCL with Differential

Drive/Receive, Level Setting DACs, and Per Pin PMU ADATE302-02 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.

FEATURES

3-level driver with high-Z mode and built-in clamps Precision trimmed output resistance Low leakage mode (typically <10 nA) Voltage range: −2.0 V to +6.0 V 1.0 ns minimum pulse width, 1 V terminated Comparator Window and differential comparator >1 GHz input equivalent bandwidth Load ±12 mA maximum current capability Per pin PMU Force voltage range: −2.0 V to +6.0 V 5 current ranges: 25 mA, 2 mA, 200 μA, 20 μA, and 2 μA Levels 14-bit DAC for DCL levels Typically <±5 mV INL (calibrated) 16-bit DAC for PMU levels Typically <±1.5 mV INL (calibrated) linearity in FV mode HVOUT output buffer 0 V to 13.5 V output range Packages 84-ball, 9 mm × 9 mm, flip-chip BGA 100-lead TQFP_EP

1.7 W per channel with no load

APPLICATIONS

Semiconductor test systems Board test systems Instrumentation and characterization equipment GENERAL DESCRIPTION The ADATE302-02 is a complete, single-chip solution that performs the pin electronic functions of the driver, the compa- rator, and the active load (DCL), per pin PMU, and dc levels for ATE applications. The device also contains an HVOUT driver with a VHH buffer capable of generating up to 13.5 V . The driver features three active states: data high mode, data low mode, and term mode, as well as an inhibit state. The inhibit state, in conjunction with the integrated dynamic clamp, facilitates the implementation of a high speed active termination. The output voltage range is −2.0 V to +6.0 V to accommodate a wide variety of test devices. The ADATE302-02 can be used as either a dual single-ended drive/receive channel or a single differential drive/receive channel. Each channel of the ADATE302-02 features a high speed window comparator for functional testing as well as a per pin PMU with FV or FI and MV or MI functions. All necessary dc levels for DCL functions are generated by on-chip 14-bit DACs. The per pin PMU features an on-chip 16-bit DAC for high accuracy and contains integrated range resistors to minimize external component counts. The ADATE302-02 uses a serial bus to program all functional blocks and has an on-board temperature sensor for monitoring the device temperature.

ADATE302-02* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Data Sheet

ADATE302-02: 500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per Pin PMU Data Sheet DESIGN RESOURCES
ADATE302-02 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints DISCUSSIONS View all ADATE302-02 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. A | Page 2 of 58 TABLE OF CONTENTS

REVISION HISTORY

4/09—Rev. 0 to Rev. A 6/08—Revision 0: Initial Version

Figure 1. Functional Block Diagram with One of Two Channels Shown

Rev. A | Page 4 of 58 SPECIFICATIONS defined in Table 38. All specified values are at TJ = 80°C, where TJ corresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are measured at TJ = 80°C ± 20°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of T est Levels section. TOTAL FUNCTION Table 1. Parameter Min Typ Max Unit Test Level Conditions/Comments TOTAL FUNCTION Output Leakage Current VCH = 7.0 V, VCL = −2.5 V PE Disable, Range A, B, C, D 7.5 nA CT −2.0 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; VCH = 7.0 V, VCL = −2.5 V High-Z Mode −400 +15 +400 nA P −2.0 V < VDUTx < +6.0 V; PMU disabled and PE enabled via SPI; RCVx pins active, VCH = 7.0 V, VCL = −2.5V Output Capacitance 4 pF S VTERM mode operation DUT Pin Range −2.0 +6.0 V D P O W E R S U P P L I E S Total Supply Range, VPLUS to VSS 22.5 23.25 V D Defines PSRR conditions VPLUS Supply, VPLUS 16.25 16.75 17.25 V D Defines PSRR conditions Positive Supply, VDD 9.5 10.0 10.5 V D Defines PSRR conditions Negative Supply, VSS −6.0 −5.75 −5.5 V D Defines PSRR conditions Logic Supply, VCC 3.1 3.3 3.5 V D Defines PSRR conditions Comparator Termination, VCOMP_VTTx 1 1.5 3.3 V D VPLUS Supply Current, IPLUS −1.0 +1.3 +4.0 mA P HVOUT disabled VPLUS Supply Current, IPLUS 4.0 12.7 17.0 mA P HVOUT enabled, RCVx pins active, no load, VHH = 12 V Logic Supply Current, ICC 1.0 2.7 10.0 mA P Quiescent (SPI is static) Comparator Termination Current, ICOMP_VTTx 40.0 46 70.0 mA P Positive Supply Current, IDD 140.0 190 256.0 mA P Load power down (IOH = IOL = 0 mA) 170.0 231 311.0 mA P Load active off (IOH = IOL = 12 mA) Negative Supply Current, ISS 200.0 272 406.0 mA P Load power down (IOH = IOL = 0 mA) 230.0 311 461.0 mA P Load active off (IOH = IOL = 12 mA) Total Power Dissipation 2.5 3.55 4.0 W P Load power down (IOH = IOL = 0 mA) 3.0 4.2 5.5 W P Load active off (IOH = IOL = 12 mA) TEMPERATURE MONITORS Temperature Sensor Gain 10 mV/K CT Temperature Sensor Accuracy Without Calibration over 25°C to 100°C 6 °C CT Temperature voltage available on Pin A1 at all times and on Pin K1 when selected (see Table 25 and Table 37) V R E F I N P U T Reference Input Voltage Range for DACs (VREF Pin) 4.95 5 5.05 V D Referenced to VREF_GND; not referenced to VDUTGND Input Bias Current 0.08 100 μA P Tested with 5 V applied

Rev. A | Page 5 of 58 DRIVER VH − VL ≥ 200 mV (to meet dc/ac specifications). Table 2. Parameter Min Typ Max Unit Test Level Conditions/Comments DC SPECIFICATIONS High-Speed Differential Logic Input Characteristics (DATAx, RCVx) Input Termination Resistance 92 100 108 Ω P Push 6 mA into xP pins, force 1.3 V on xN pins; measure voltage from xP to xN, calculate resistance (V/I) Input Voltage Differential 0.2 1.0 V PF Common-Mode Voltage 0.85 3.5 V PF pin left open Pin Output Characteristics Output High Range, VH −1.9 +6.0 V D Output Low Range, VL −2.0 +5.9 V D Output Term Range, VT −2.0 +6.0 V D Functional Amplitude (VH − VL) 0.0 8.0 V D Amplitude can be programmed to VH = VL, accuracy specifications apply when VH − VL ≥ 200 mV DC Output Current Limit Source 75 100 120 mA P Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure current DC Output Current Limit Sink −120 −100 −75 mA P Driver low, VL = −2.0 V, short DUTx pin to 6.0 V, measure current Output Resistance, ±50 mA 45.0 48.5 51.0 Ω P Source: driver high, VH = 3.0 V, IDUTx = 1 mA and 50 mA; sink: driver low, VL = 0.0 V, IDUTx = −1 mA and −50 mA; ΔVDUTx/ΔIDUTx ABSOLUTE ACCURACY VH tests done with VL = −2.5 V and VT = −2.5 V; VL tests done with VH = 7.5 V and VT = 7.5 V; VT tests done with VL = −2.5 V and VH = 7.5 V; unless otherwise specified VH, VL, VT Uncalibrated Accuracy −300 ±75 +300 mV P Error measured at calibration points of 0 V and 5 V VH, VL, VT Offset Tempco ±450 μV/°C CT Measured at calibration points VH, VL, VT DNL ±1 mV CT After two-point gain/offset calibration VH, VL, VT INL −10 ±2.5 +10 mV P After two-point gain/offset calibration; measured over driver output ranges VH, VL, VT Resolution 0.6 1 mV PF After two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V DUTGND Voltage Accuracy −7 ±1.3 +7 mV P Over ±0.1 V range; measured at end points of VH, VL, and VT functional range dc crosstalk on VL, VH, VT output level when other driver DACs are varied Overall Voltage Accuracy ±10 mV CT Sum of INL, crosstalk, DUTGND, and tempco over ±5°C, after gain/offset calibration VH, VL, VT DC PSRR ±15 mV/V CT Measured at calibration points AC SPECIFICATIONS Rise/Fall Times Toggle DATAx pins 0.2 V Programmed Swing 683 ps CB VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80% 1.0 V Programmed Swing 521 ps CB VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80% 1.8 V Programmed Swing 430 524 630 ps P/CB VH = 1.8 V, VL = 0.0 V, terminated; 20% to 80% 2.0 V Programmed Swing 531 ps CB VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80% 3.0 V Programmed Swing 589 ps CB VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80% 3.0 V Programmed Swing 811 ps CB VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90% 5.0 V Programmed Swing 1105 ps CB VH = 5.0 V, VL = 0.0 V, unterminated; 10% to 90% Rise to Fall Matching 6 ps CB VH = 1.0 V, VL = 0.0 V, terminated; rise to fall within one channel

Rev. A | Page 6 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments Minimum Pulse Width Toggle DATAx pins 2.0 V Programmed Swing 1.2 ns CB VH = 2.0 V, VL = 0.0 V, terminated; timing error ±27 ps 1.2 ns CB VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude degradation 1.0 ns CB VH = 2.0 V, VL = 0.0 V, terminated; less than 20% amplitude degradation Maximum Toggle Rate 500 MHz CB VH = 2.0 V, VH = 0.0 V, terminated, 18% amplitude degradation Dynamic Performance, Drive (VH to VL and VL to VH) Toggle DATAx pins Propagation Delay Time 2.1 ns CB VH = 2.0 V, VL = 0.0 V, terminated Propagation Delay Tempco 4.5 ps/°C CT VH = 1.8 V, VL = 0.0 V, terminated Delay Matching VH = 2.0 V, VL = 0.0 V, terminated Edge to Edge 41 ps CB Rising vs. falling Channel to Channel ±15 ps CB Rising vs. rising, falling vs. falling Delay Change vs. Duty Cycle ±30 ps CB VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz Overshoot and Undershoot 48 mV CB VH = 3.0 V, VL = 0.0 V, terminated Settling Time (VH to VL) Toggle DATAx pins To Within 3% of Final Value 1.2 ns CB VH = 3.0 V, VL = 0.0 V, terminated To Within 1% of Final Value 14 ns CB VH = 3.0 V, VL = 0.0 V, terminated Dynamic Performance, VTERM (VH or VL to VT and VT to VH or VL) T o g g l e R C V x p i n s Propagation Delay Time 2.7 ns CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated Delay Matching, Edge to Edge 59 ps CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling Propagation Delay Tempco 5.5 ps/°C CT VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated Transition Time, Active to VT, VT to Active 0.614 ns CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80% Dynamic Performance, Inhibit (VH or VL to/from Inhibit) T o g g l e R C V x p i n s Propagation Delay Time VH = +1.0 V, VL = −1.0 V, terminated Active to Inhibit 2.7 ns CB Inhibit to Active 3.7 ns CB Transition Time VH = +1.0 V, VL = −1.0 V, terminated; 20% to 80% Active to Inhibit 1.3 ns CB Inhibit to Active 0.4 ns CB I/O Spike 157 mV CB VH = 0.0 V, VL = 0.0 V, terminated

Rev. A | Page 7 of 58 REFLECTION CLAMP Clamp accuracy specifications apply when VCH > VCL. Table 3. Parameter Min Typ Max Unit Test Level Conditions/Comments VCH Range −1.0 +6.0 V D Uncalibrated Accuracy −200 ±45 +200 mV P Driver high-Z, sinking 1 mA; VCH error measured at calibration points of 0 V and 5 V Resolution 0.6 0.75 mV PF Driver high-Z, sinking 1 mA; after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V DNL ±1 mV CT Driver high-Z, sinking 1 mA; after two-point gain/offset calibration INL −40 ±2 +40 mV P Driver high-Z, sinking 1 mA; after two-point gain/offset calibration; measured over VCH range of −1 V to +6 V Tempco −0.5 mV/°C CT Measured at calibration points VCL Range −2 +5.0 V D Uncalibrated Accuracy −200 ±70 +200 mV P Driver high-Z, sourcing 1 mA; VCL error measured at calibration points of 0 V and 5 V Resolution 0.6 0.75 mV PF Driver high-Z, sourcing 1 mA; after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V DNL ±1 mV CT Driver high-Z, sourcing 1 mA; after two-point gain/offset calibration INL −40 ±2 +40 mV P Driver high-Z, sourcing 1 mA; after two-point gain/offset calibration; measured over VCL range of −2 V to +5 V Tempco 0.6 mV/°C CT Measured at calibration points DC CLAMP CURRENT LIMIT VCH −120 −83 −60 mA P Driver high-Z, VCH = 0 V, VCL = −2.0 V, VDUTx = 5 V VCL 60 86 120 mA P Driver high-Z, VCH = 6.0 V, VCL = 5.0 V, VDUTx = 0.0 V DUTGND VOLTAGE ACCURACY −7 ±1 +7 mV P Over ±0.1 V range; measured at the end points of VCH and VCL functional range NORMAL WINDOW COMPARATOR VOH tests done with VOL = −2.0 V , VOL tests done with VOH = 6.0 V , unless otherwise specified. Table 4. Parameter Min Typ Max Unit Test Level Conditions/Comments DC SPECIFICATIONS Input Voltage Range −2.0 +6.0 V D Differential Voltage Range ±0.1 ±8.0 V D Comparator Input Offset Voltage Accuracy, Uncalibrated −150 ±30 +150 mV P Offset measured at calibration points of 0 V and 5 V Comparator Threshold Resolution 0.61 1 mV PF After two-point gain/offset calibration; range/ number of DAC bits as measured at calibration points of 0 V and 5 V Comparator Threshold DNL ±1 mV CT After two-point gain/offset calibration Comparator Threshold INL −7 ±1.2 +7 mV P After two-point gain/offset calibration; measured over VOH, VOL range of −2.0 V to +6.0 V Comparator Input Offset Voltage Tempco ±200 μV/°C CT Measured at calibration points

Rev. A | Page 8 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments DUTGND Voltage Accuracy −7 ±0.5 +7 mV P Over ±0.1 V range; measured at end points of VOH and VOL functional range Comparator Uncertainty Range 5.3 mV CB V DUTx = 0 V, sweep comparator threshold to determine uncertainty region DC Hysteresis 0.5 mV CB V DUTx = 0 V DC PSRR ±5 mV/V CT Measured at calibration points Digital Output Characteristics Internal Pull-Up Resistance to Comparator, COMP_VTTx Pin 46 50 54 Ω P Pull 1 mA and 10 mA from Logic 1 leg and measure ΔV to calculate resistance; measured ΔV/9 mA; done for both comparator logic states VCOMP_VTTx Range 1 1.5 3.3 V D Common-Mode Voltage VCOMP_VTTx − 0.3 V CT Measured with 100 Ω differential termination V COMP_VTTx − 0.5 V COMP_VTTx V P Measured with no external termination Differential Voltage 250 mV CT Measured with 100 Ω differential termination 450 500 550 mV P Measured with no external termination Rise/Fall Time, 20% to 80% 222 ps CB Measured with each comparator leg terminated 50 Ω to GND AC SPECIFICATIONS Input transition time = 600 ps, 10% to 90%; measured with each comparator leg terminated 50 Ω to GND; unless otherwise specified Propagation Delay, Input to Output 1.4 ns CB V DUTx = 0 V to 1.0 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V Propagation Delay Tempco 4 ps/°C CT V DUTx = 0 V to 0.9 V swing, driver VTERM mode, VT = 0.0 V; VOL = VOH = 0.45 V Propagation Delay Matching VDUTx = 0 V to 1.0 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V High Transition to Low Transition 39 ps CB High to Low Comparator ±30 ps CB Propagation Delay Change with Respect to Slew Rate, 600 ps and 1 ns (10% to 90%) 19 ps CB V DUTx = 0 V to 0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.25 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.25 V Overdrive, 250 mV and 1.0 V 65 ps CB For 250 mV: VDUTx = 0 V to 0.5 V swing; for 1.0 V: VDUTx = 0 V to 1.25 V swing; driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.25 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.25 V; input transition time = 400 ps (10%/90%) Pulse Width, 1 ns, 5 ns, 10 ns, and 15 ns 27 ps CB V DUTx = 0 V to 1.0 V swing @ 32.0 MHz, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V; input transition time = 400 ps (10%/90%) Duty Cycle, 5% to 95% 11.8 ps CB V DUTx = 0 V to 1.0 V swing @ 1.0 MHz, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V, VOL = −2.0 V; low-side measurement: VOH = 6.0 V, VOL = 0.5 V; input transition time = 400 ps (10%/90%)

Rev. A | Page 9 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments Minimum Pulse Width 1 ns CB V DUTx = 0 V to 1.0 V swing, driver VTERM mode, VT = 0.0 V; less than 10% amplitude degradation measured by shmoo; input transition time = 400 ps (10%/90%) Input Equivalent Bandwidth, Terminated 1000 MHz CB V DUTx = 0 V to 1.0 V swing, driver VTERM mode, VT = 0.0 V; as measured by shmoo; input transition time = 400 ps (10%/90%) ERT High-Z Mode, 3 V, 20% to 80% 0.9 ns CB V DUTx = 0 V to 3.0 V swing, driver high-Z; as measured by shmoo DIFFERENTIAL COMPARATOR VOH tests done with VOL = −1.1 V , VOL tests done with VOH = 1.1 V , unless otherwise specified. Table 5. Parameter Min Typ Max Unit Test Level Conditions/Comments DC SPECIFICATIONS Input Voltage Range −1.5 +4.5 V D Operational Differential Voltage Range ±0.05 ±1.1 V D Maximum Differential Voltage Range ±8 V D Comparator Input Offset Voltage Accuracy, Uncalibrated −150 ±25 +150 mV P Offset measured at differential calibration points of +1 V and −1 V, with common mode = 0 V VOH, VOL Resolution 0.61 1 mV PF After two-point gain/offset calibration; range/number of DAC bits as measured at differential calibration points of +1 V and −1 V, with common mode = 0 V VOH, VOL DNL ±1 mV CT After two-point gain/offset calibration; common mode = 0 V VOH, VOL INL −7 ±1.0 +7 mV P After two-point gain/offset calibration; measured over VOH, VOL range of −1.1 V to +1.1 V, common mode = 0 V VOH, VOL Offset Voltage Tempco ±200 μV/°C CT Measured at calibration points Comparator Uncertainty Range 18 mV CB V DUTx = 0 V, sweep comparator threshold to determine uncertainty region DC Hysteresis 0.5 mV CB V DUTx = 0 V CMRR 1 mV/V P Offset measured at common-mode voltage points of −1.5 V and +4.5 V, with differential voltage = 0 V DC PSRR ±15 mV/V CT Measured at calibration points AC SPECIFICATIONS Input transition time = 600 ps, 10% to 90%, measured with each comparator leg terminated 50 Ω to GND Propagation Delay, Input to Output 1.4 ns CB V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel Propagation Delay Tempco 4 ps/°C CT V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; VOL = VOH = 0.0 V; repeat for other DUT channel Propagation Delay Matching VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel High Transition to Low Transition 27 ps CB High to Low Comparator ±32 ps CB Propagation Delay Change with Respect to VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

Rev. A | Page 10 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments VOL = 0.0 V; repeat for other DUT channel Slew Rate, 400 ps and 1 ns (10% to 90%) 25 ps CB V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel Overdrive, 250 mV and 750 mV 79 ps CB V DUT0 = 0 V, for 250 mV: VDUT1 = 0 V to 0.5 V swing; for 750 mV: VDUT1 = 0 V to 1.0 V swing, driver VTERM mode, VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel with comparator threshold = 0.25 V Pulse Width, 1 ns, 5 ns, 10 ns, and 15 ns 56 ps CB V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 32 MHz, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel Duty Cycle, 5% to 95% 16 ps CB V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 32 MHz, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel Minimum Pulse Width 1 ns CB V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V; less than 22% amplitude degradation measured by shmoo; repeat for other DUT channel Input Equivalent Bandwidth, Terminated 500 MHz CB V DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL = 0.0 V

Rev. A | Page 11 of 58 ACTIVE LOAD See Table 30 for load control information. Table 6. Parameter Min Typ Max Unit Test Level Conditions/Comments DC SPECIFICATIONS Load active on, RCVx pins active, unless otherwise noted Input Characteristics VCOM Voltage Range −1.75 +5.75 V D VDUTx Range −2.0 +6.0 V D VCOM Accuracy, Uncalibrated −200 ±25 +200 mV P IOH = IOL = 6 mA, VCOM error measured at calibration points of 0 V and 5 V VCOM Resolution 0.61 1 mV PF IOH = IOL = 6 mA, after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V VCOM DNL ±1 mV CT IOH = IOL = 6 mA, after two-point gain/offset calibration VCOM INL −7 ±2 +7 mV P IOH = IOL = 6 mA, after two-point gain/offset calibration; measured over VCOM range of −1.75 V to +5.75 V DUTGND Voltage Accuracy −7 ±1 +7 mV P Over ±0.1 V range; measured at end points of VCOM functional range Output Characteristics IOL Maximum Source Current 12 mA D Uncalibrated Offset −600.0 ±100 +600.0 μA P IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated from calibration points of 1 mA and 11 mA Uncalibrated Gain −12 ±1 +12 % P IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from calibration points of 1 mA and 11 mA Resolution 1.5 2 μA PF IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 1 mA and 11 mA DNL ±3.0 μA CT IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two- point gain/offset calibration INL −70 ±20 +70 μA P IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two- point gain/offset calibration; measured over IOL range of 0 mA to 12 mA 90% Commutation Voltage 0.25 V P IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at VDUTx = −1.0 V, measure IOL current at VDUTx = 1.75 V, ensure >90% of reference current IOH Maximum Sink Current 12 mA D Uncalibrated Offset −600.0 ±100 +600.0 μA P IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated from calibration points of 1 mA and 11 mA Uncalibrated Gain −12 ±1 +12 % P IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from calibration points of 1 mA and 11 mA Resolution 1.5 2 μA PF IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 1 mA and 11 mA DNL ±3.0 μA CT IOL = 0 mA, VCOM = 1.5V, VDUTx = 3.0 V, after two-point gain/offset calibration INL −70 ±20 +70 μA P IOL = 0 mA, VCOM = 1.5V, VDUTx = 3.0 V, after two-point gain/offset calibration; measured over IOH range of 0 mA to 12 mA 90% Commutation Voltage 0.25 V P IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOH reference at VDUTx = 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure >90% of reference current Output Current Tempco ±1.5 μA/°C CT Measured at calibration points

Rev. A | Page 12 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments AC SPECIFICATIONS Load active on, unless otherwise noted Dynamic Performance Propagation Delay, Load Active On to Load Active Off; 50%, 90% 4.1 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; measured from 50% point of RCVxP − RCVxN to 90% point of final output, repeat for drive low and high Propagation Delay, Load Active Off to Load Active On; 50%, 90% 11 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; measured from 50% point of RCVxP − RCVxN to 90% point of final output, repeat for drive low and high Propagation Delay Matching 6.9 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; active on vs. active off, repeat for drive low and high Load Spike 156 mV CB Toggle RCVx pins, DUTx terminated 50 Ω to GND, IOH = IOL = 0 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH; repeat for drive low and high Settling Time to 90% 1.6 ns CB Toggle RCVx pins, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM= −1.25 V for IOH; measured at 90% of final value PMU FV = force voltage, MV = measure voltage, FI = force current, MI = measure current, FN = force nothing. Table 7. Parameter Min Typ Max Unit Test Level Conditions/Comments FORCE VOLTAGE (FV) Current Range A ±25 mA D Current Range B ±2 mA D Current Range C ±200 μA D Current Range D ±20 μA D Current Range E ±2 μA D Force Input Voltage Range at Output For All Ranges −2.0 +6.0 V D Force Voltage Uncalibrated Accuracy for Range C −100 ±25 +100 mV P PMU enabled, FV, PE disabled, error measured at calibration points of 0 V and 5 V Force Voltage Uncalibrated Accuracy for All Ranges ±25 mV CT PMU enabled, FV, PE disabled, error measured at calibration points of 0 V and 5 V; repeat for each PMU current range Force Voltage Offset Tempco for All Ranges ±25 μV/°C CT Measured at calibration points for each PMU current range Force Voltage Gain Tempco for All Ranges ±75 ppm/°C CT Measured at calibration points for each PMU current range Forced Voltage INL −7 ±2 +7 mV P PMU enabled, FV, Range C, PE disabled, after two-point gain/ offset calibration; measured over output range of −2.0 V to +6.0 V Force Voltage Compliance vs. Current Load PMU enabled, FV, PE disabled, force −2.0 V, measure voltage while PMU sinking zero- and full-scale current; measure ΔV; force 6.0 V, measure voltage while PMU sourcing zero- and full- scale current; measure ΔV; repeat for each PMU current range Range A ±4 mV CT Range B to Range E ±1 mV CT

Rev. A | Page 13 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments Current Limit, Source and Sink Range A 108 135 180 % FS P PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS = 25 mA, 108% FS = 27 mA, 180% FS = 45 mA Range B to Range E 120 140 180 % FS P PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each PMU current range; example: Range B FS = 2 mA, 120% FS = 2.4 mA, 180% FS = 3.6 mA DUTGND Voltage Accuracy −7 ±1 +7 mV P Over ±0.1 V range; measured at end points of FV functional range MEASURE CURRENT (MI) VDUTx externally forced to 0.0 V, unless otherwise specified; ideal MEASOUT transfer functions: V MEASOUT01 [V] = (IMEASOUT01 × 5/FSR) + 2.5 + VDUTGND I(VMEASOUT01) [A] = (VMEASOUT01 − VDUTGND − 2.5) × FSR/5 Measure Current, Pin DUTx Voltage Range for All Ranges −2.0 +6.0 V D Measure Current Uncalibrated Accuracy Range A ±650 μA CT PMU enabled, FIMI, PE disabled, error at calibration points of −20 mA and 20 mA, error = (I(V MEASOUT01) − IDUTx) Range B −400 ±20 +400 μA P PMU enabled, FIMI, PE disabled, error at calibration points of −1.6 mA and 1.6 mA, error = (I(VMEASOUT01) − IDUTx) Range C ± 2.00 μA CT PMU enabled, FIMI, PE disabled, error at calibration points of ±80% FS, error = (I(V MEASOUT01) − IDUTx) Range D ±0.20 μA CT PMU enabled, FIMI, PE disabled, error at calibration points of ±80% FS, error = (I(V MEASOUT01) − IDUTx) Range E ±0.02 μA CT PMU enabled, FIMI, PE disabled, error at calibration points of ±80% FS, error = (I(V MEASOUT01) − IDUTx) Measure Current Offset Tempco Range A ±2.5 μA/°C CT Measured at calibration points Range B ±125 nA/°C CT Measured at calibration points Range C ±20 nA/°C CT Measured at calibration points Range D and Range E ±4 nA/°C CT Measured at calibration points Measure Current Gain Error, Nominal Gain = 1 Range A −3.5 % CT PMU enabled, FIMI, PE disabled, gain error from calibration points of ±80% FS Range B −20 ±2 +20 % P PMU enabled, FIMI, PE disabled, gain error from calibration points of ±1.6 mA Range C to Range E ±2 % CT PMU enabled, FIMI, PE disabled, gain error from calibration points of ±80% FS Measure Current Gain Tempco Measured at calibration points Range A ±300 ppm/°C CT Range B to Range E ±50 ppm/°C CT Measure Current INL Range A ±0.05 % FSR CT PMU enabled, FIMI, PE disabled, after two-point gain/offset calibration, measured over FSR output of −25 mA to +25 mA Range B −0.02 ±0.005 0.02 % FSR P PMU enabled, FIMI, PE disabled, after two-point gain/ offset calibration measured over FSR output of −2 mA to +2 mA Range B to Range E ±0.005 % FSR CT PMU enabled, FIMI, PE disabled, after two-point gain/offset calibration; measured over FSR output FVMI DUT Pin Voltage Rejection −0.01 0.01 % FSR/V P PMU enabled, FVMI, PE disabled, force −1 V and +5 V into load of 1 mA; measure ΔI reported at MEASOUT01 DUTGND Voltage Accuracy ±2.5 mV CT Over ±0.1 V range; measured at end points of MI functional range

Rev. A | Page 14 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments FORCE CURRENT (FI) VDUTx externally forced to 0.0 V, unless otherwise specified Ideal force current transfer function: IFORCE = (PMUDAC − 2.5) × (FSR/5) Force Current, DUTx Pin Voltage Range for All Ranges −2.0 +6.0 V D Force Current Uncalibrated Accuracy Range A −5.0 ±0.5 +5.0 mA P PMU enabled, FIMI, PE disabled, error at calibration points of −20 mA and +20 mA Range B −400 ±40 +400 μA P PMU enabled, FIMI, PE disabled, error at calibration points of −1.6 mA and +1.6 mA Range C −40 ±4 +40 μA P PMU enabled, FIMI, PE disabled, error at calibration points of ±80% FS Range D −4 ±0.4 +4 μA P PMU enabled, FIMI, PE disabled, error at calibration points of ±80% FS Range E −400 ±75 +400 nA P PMU enabled, FIMI, PE disabled, error at calibration points of ±80% FS Force Current Offset Tempco Range A ±1 μA/°C CT Measured at calibration points Range B ±80 nA/°C CT Measured at calibration points Range C to Range E ±4 nA/°C CT Measured at calibration points Forced Current Gain Error, Nominal Gain = 1 −20 ±4 +20 % P PMU enabled, FIMI, PE disabled, gain error from calibration points of ±80% FS Forced Current Gain Tempco Measured at calibration points Range A −500 ppm/°C CT Range B to Range E ±75 ppm/°C CT Force Current INL Range A −0.3 ±0.05 +0.3 % FSR P PMU enabled, FIMI, PE disabled, after two-point gain/offset calibration; measured over FSR output of −25 mA to +25 mA Range B to Range E -0.2 ±0.015 0.2 % FSR P PMU enabled, FIMI, PE disabled, after two-point gain/offset calibration; measured over FSR output Force Current Compliance vs. Voltage Load PMU enabled, FIMV, PE disabled; force positive full-scale current driving −2.0 V and +6.0 V, measure ΔI @ DUTx pin; force negative full-scale current driving −2.0 V and +6.0 V, measure ΔI @ DUTx pin Range A to Range D −0.6 ±0.06 +0.6 % FSR P Range E −1.0 +±0.1 +1.0 % FSR P MEASURE VOLTAGE Measure Voltage Range −2.0 +6.0 V D Measure Voltage Uncalibrated Accuracy −25 ±2.0 +25 mV P PMU enabled, FVMV, Range B, PE disabled, error at calibration points of 0 V and 5 V, error = (VMEASOUT01 − VDUTx) Measure Voltage Offset Tempco ±10 μV/°C CT Measured at calibration points Measure Voltage Gain Error −2 ±0.01 +2 % P PMU enabled, FVMV, Range B, PE disabled, gain error from calibration points of 0 V and 5 V Measure Voltage Gain Tempco 25 ppm/°C CT Measured at calibration points Measure Voltage INL −7 ±1 +7 mV P PMU enabled, FVMV, Range B, PE disabled, after two-point gain/offset calibration; measured over output range of −2.0 V to +6.0 V Rejection of Measure V vs. IDUTx −1.5 ±0.1 +1.5 mV P PMU enabled, FVMV, Range D, PE disabled, force 0 V into load of −10 μA and +10 μA; measure ΔV reported at MEASOUT01

Rev. A | Page 15 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments MEASOUT01 DC CHARACTERISTICS MEASOUT01 Voltage Range −2.0 +6.0 V D DC Output Current 4 mA D MEASOUT01 Pin Output Impedance 25 200 Ω P PMU enabled, FVMV, PE disabled; source resistance: PMU force

6.0 V and load with 0 mA and 4 mA; sink resistance: PMU force

−2.0 V and load with 0 mA and −4 mA; resistance = ΔV/ΔI at MEASOUT01 pin Output Leakage Current When Tristated −1 +1 μA P Tested at −2.0 V and +6.0 V Output Short-Circuit Current −25 +25 mA P PMU enabled, FVMV, PE disabled; source: PMU force 6.0 V, short MEASOUT01 to −2.0 V; sink: PMU force −2.0 V, short MEASOUT01 to 6.0 V VOLTAGE CLAMPS Low Clamp Range (VCL) −2.0 +4.0 V D High Clamp Range (VCH) 0.0 6.0 V D Positive Clamp Voltage Droop −300 +50 +300 mV P PMU enabled, FIMI, Range A, PE disabled, PMU clamps enabled, VCH = 5 V, VCL = −1 V, PMU force 1 mA and 25 mA into open; ΔV seen at DUTx pin Negative Clamp Voltage Droop −300 −50 +300 mV P PMU enabled, FIMI, Range A, PE disabled, PMU clamps enabled, VCH = 5 V, VCL = −1 V, PMU force −1 mA and −25 mA into open; ΔV seen at DUTx pin Uncalibrated Accuracy −250 ±100 +250 mV P PMU enabled, FIMI, Range B, PE disabled, PMU damps enabled, PMU force ±1 mA into open; VCH errors at calibration points of

0 V and 5 V; VCL errors at the calibration points of 0 V and 4 V

INL −70 ±5 +70 mV P PMU enabled, FIMI, Range B, PE disabled, PMU damps enabled, PMU force ±1 mA into open; after two-point gain/offset calibration; measured over PMU clamp range DUTGND Voltage Accuracy ±1 mV CT Over ±0.1 V range; measured at end points of PMU clamp functional range SETTLING/SWITCHING TIMES SCAP = 330 pF, FFCAP = 220 pF Voltage Force Settling Time to 0.1% of Final Value PMU enabled, FV, PE disabled, program PMUDAC steps of 500 mV and 5.0 V; simulation of worst case, 2000 pF load, PMUDAC step of 5.0 V Range A, 200 pF and 2000 pF Load 15 μs S Range B, 200 pF and 2000 pF Load 20 μs S Range C, 200 pF and 2000 pF Load 124 μs S Range D, 200 pF and 2000 pF Load 1015 μs S Range E, 200 pF and 2000 pF Load 3455 μs S Voltage Force Settling Time to 1.0% of Final Value PMU enabled, FV, PE disabled, start with PMUDAC programmed to 0.0 V, program PMUDAC to 500 mV Range A, 200 pF and 2000 pF Load 8.0 μs CB Range B, 200 pF and 2000 pF Load 8.0 μs CB Range C, 200 pF and 2000 pF Load 8.0 μs CB Range D, 200 pF Load 8.1 μs CB Range D, 2000 pF Load 585 μs CB Range E, 200 pF Load 8.1 μs CB Range E, 2000 pF Load 590 μs CB

Rev. A | Page 16 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments Voltage Force Settling Time to 1.0% of Final Value PMU enabled, FV, PE disabled, start with PMUDAC programmed to 0.0 V, program PMUDAC to 5.0 V Range A, 200 pF and 2000 pF Load 4.2 μs CB Range B, 200 pF Load 4.4 μs CB Range B, 2000 pF Load 7.6 μs CB Range C, 200 pF Load 6.3 μs CB Range C, 2000 pF Load 8.1 μs CB Range D, 200 pF Load 130 μs CB Range D, 2000 pF Load 280 μs CB Range E, 200 pF Load 390 μs CB Range E, 2000 pF Load 605 μs CB Current Force Settling Time to 0.1% of Final Value PMU enabled, FI, PE disabled, start with PMUDAC programmed to 0 current, program PMUDAC to FS current Range A, 200 pF in Parallel with 120 Ω 8.2 μs S Range B, 200 pF in Parallel with 1.5 kΩ 9.4 μs S Range C, 200 pF in Parallel with 15.0 kΩ 30 μs S Range D, 200 pF in Parallel with 150 kΩ 281 μs S Range E, 200 pF in Parallel with 1.5 MΩ 2668 μs S Current Force Settling Time to 1.0% of Final Value PMU enabled, FI, PE disabled, start with PMUDAC programmed to 0 current, program PMUDAC to FS current Range A, 200 pF in Parallel with 120 Ω 3.3 μs CB Range B, 200 pF in Parallel with 1.5 kΩ 4.4 μs CB Range C, 200 pF in Parallel with 15.0 kΩ 8 μs CB Range D, 200 pF in Parallel with 150 kΩ 205 μs CB Range E, 200 pF in Parallel with 1.5 MΩ 505 μs CB INTERACTION AND CROSSTALK Measure Voltage Channel-to- Channel Crosstalk ±0.125 % FSR CT PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into

0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA

into 0 V load; report ΔV of MEASOUT01 pin under test; 0.125% × 8.0 V = 10 mV Measure Current Channel-to- Channel Crosstalk ±0.01 % FSR CT PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into 0 mA current load; other channel: Range E, forcing a step of 0 V to 5 V into 0 mA current load; report ΔV of MEASOUT01 pin under test; 0.01% × 5.0 V = 0.5 mV EXTERNAL SENSE (PMUS_CHx) Table 8. Parameter Min Typ Max Unit Test Level Conditions/Comments Voltage Range −2.0 +6.0 V D Input Leakage Current −20 +20 nA P Tested at −2.0 V and +6.0 V

Rev. A | Page 17 of 58 DUTGND INPUT Table 9. Parameter Min Typ Max Unit Test Level Conditions/Comments Input Voltage Range, Referenced to GND −0.1 +0.1 V D Input Bias Current 1 100 μA P Tested at −100 mV and +100 mV SERIAL PERIPHERAL INTERFACE Table 10. Parameter Min Typ Max Unit Test Level Conditions/Comments Serial Input Logic High 1.8 VCC V PF Serial Input Logic Low 0 0.7 V PF Input Bias Current −10 +1 +10 μA P Tested at 0.0 V and 3.3 V SCLK Clock Rate 50 MHz PF SCLK Pulse Width 9 ns CT SCLK Crosstalk on DUTx Pin 8 mV CB PE disabled, PMU FV enabled and forcing 0 V Serial Output Logic High VCC − 0.4 VCC V PF Sourcing 2 mA Serial Output Logic Low 0 0.8 V PF Sinking 2 mA Update Time 10 μs D Maximum delay time required for the part to enter a stable state after a serial bus command is loaded HVOUT DRIVER Table 11. Parameter Min Typ Max Unit Test Level Conditions/Comments VHH BUFFER VHH = (VT + 1 V) × 2 + DUTGND Voltage Range 5.9 VPLUS − 3.25 V D VPLUS = 16.75 V nominal; in this condition, VHVOUT maximum = 13.5 V Output High 13.5 V P VHH mode enabled, RCVx pins active, VHH level = full scale, sourcing 15 mA Output Low 5.9 V P VHH mode enabled, RCVx pins active, VHH level = zero scale, sinking 15 mA Accuracy Uncalibrated −500 ±100 +500 mV P VHH mode enabled, RCVx pins active, VHVOUT error measured at calibration points of 7 V and 12 V Offset Tempco 1 mV/°C CT Measured at calibration points Resolution 1.21 1.5 mV PF VHH mode enabled, RCVx pins active, after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 7 V and 12 V INL −30 ±15 +30 mV P VHH mode enabled, RCVx pins active, after two-point gain/ offset calibration; measured over VHH range of 5.9 V to 13.5 V DUTGND Voltage Accuracy ±1 mV CT Over ±0.1 V range; measured at end points of VHH functional range Output Resistance 1 10 Ω P VHH mode enabled, RCVx pins active, source: VHH = 10.0 V, IHVOUT = 0 mA and 15 mA; sink: VHH = 6.5 V, IHVOUT = 0 mA and −15 mA; ΔV/ΔI DC Output Current Limit Source 60 100 mA P VHH mode enabled, RCVx pins active, VHH = 10.0 V, short HVOUT pin to 5.9 V, measure current DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCVx pins active, VHH = 6.5 V, short HVOUT pin to 14.1 V, measure current Rise Time (From VL or VH to VHH) 175 ns CB VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL = VH = 3.0 V; 20% to 80%, for DATAx high and DATAx low

Rev. A | Page 18 of 58 Parameter Min Typ Max Unit Test Level Conditions/Comments Fall Time (From VHH to VL or VH) 23 ns CB VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL = VH = 3.0 V; 20% to 80%, for DATAx high and DATAx low Preshoot, Overshoot, and Undershoot ±100 mV CB VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL = VH = 3.0 V; for DATAx high and DATAx low VL/VH BUFFER Voltage Range −0.1 +6.0 V D Accuracy Uncalibrated −500 ±100 +500 mV P VHH mode enabled, RCVx pins inactive, error measured at calibration points of 0 V and 5 V Offset Tempco 1 mV/°C CT Measured at calibration points Resolution 0.61 0.75 mV PF VHH mode enabled, RCVx pins inactive, after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V INL −20 ±4 +20 mV P VHH mode enabled, RCVx pins inactive, after two-point gain/offset calibration; measured over range of −0.1 V to +6.0 V DUTGND Voltage Accuracy ±2 mV CT Over ±0.1 V range; measured at end points of VH and VL, functional range Output Resistance 46 48 50 Ω P VHH mode enabled, RCVx pins inactive, source: VH = 3.0 V, IHVOUT = 1 mA and 50 mA; sink: VL = 2.0 V, IHVOUT = −1 mA and −50 mA; ΔV/ΔI DC Output Current Limit Source 60 100 mA P VHH mode enabled, RCVx pins inactive, VH = 6.0 V, short HVOUT pin to −0.1 V, DATAx high, measure current DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCVx pins inactive, VL = −0.1 V, short HVOUT pin to 6.0 V, DATAx low, measure current Rise Time (VL to VH) 10.0 ns CB VHH mode enabled, RCVx pins inactive, VL = 0.0 V, VH = 3.0 V, toggle DATAx pins; 20% to 80% Fall Time (VH to VL) 11.3 ns CB VHH mode enabled, RCVx pins inactive, VL = 0.0 V, VH = 3.0 V, toggle DATAx pins; 20% to 80% Preshoot, Overshoot, and Undershoot ±54 mV CB VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V, toggle DATAx pins OVERVOLTAGE DETECTOR (OVD) Table 12. Parameter Min Typ Max Unit Test Level Conditions/Comments DC CHARACTERISTICS Programmable Voltage Range −3.0 +7.0 V D Accuracy Uncalibrated −200 +200 mV P OVD offset errors measured at programmed levels of 7.0 V and −3.0 V Hysteresis 112 mV CB LOGIC OUTPUT CHARACTERISTICS Off State Leakage 10 1000 nA P Disable OVD alarm, apply 3.3 V to OVD_CHx pin, measure leakage current Maximum On Voltage @100 μA 0.2 0.7 V P Activate alarm, force 100 μA into OVD_CHx, measure active alarm voltage Propagation Delay 1.8 μs CB For OVD high: DUTx = 0 V to 6 V swing, OVD_CHx high = 3.0 V, OVD_CHx low = −3.0 V; for OVD_CHx low: DUTx = 0 V to 6 V swing, OVD_CHx high = 7.0 V, OVD_CHx low = 3.0 V

Rev. A | Page 19 of 58 16-BIT DAC MONITOR MUX Table 13. Parameter Min Typ Max Unit Test Level Conditions/Comments DC CHARACTERISTICS Programmable Voltage Range −2.5 +7.5 V D Output Resistance 16 kΩ CT PMUDAC = 0.0 V, FV, I = 0 μA, 200 μA; ΔV/ΔI

Table 15. Thermal Resistance

1 RL = 0 Ω, VDUTx continuous short-circuit condition (VH, VL, VT, high-Z, VCOM,

2 DATAxP, DATAxN, RCVxP, RCVxN, under source R = 0 Ω. 3 DATAxP to DATAxN, RCVxP, RCVxN.

Figure 2. 84-Ball BGA Pin Configuration, Bottom Side (BGA Balls Are Visible) Table 16. Pin Function Descriptions

Rev. A | Page 22 of 58 BGA Designator Mnemonic Description B3 VSS Supply −5.75 V B4 AGND Analog Ground B5 VDD Supply +10.0 V B6 VDD Supply +10.0 V B7 AGND Analog Ground B8 VSS Supply −5.75 V B9 SCAP0 PMU Stability Capacitor Connection Channel 0 (330 pF) B10 VPLUS Supply +16.75 V C1 FFCAP_1B PMU Feedforward Capacitor Connection B Channel 1 (220 pF) C2 AGND Analog Ground C3 DATA1N Driver Data Input (Negative) Channel 1 C4 VSS Supply −5.75 V C5 VDD Supply +10.0 V C6 VDD Supply +10.0 V C7 VSS Supply −5.75 V C8 DATA0N Driver Data Input (Negative) Channel 0 C9 AGND Analog Ground C10 FFCAP_0B PMU Feedforward Capacitor Connection B Channel 0 (220 pF) D1 OVD_CH1 Overvoltage Detection Flag Output Channel 1 D2 VDD Supply +10.0 V D3 DATA1P Driver Data Input (Positive) Channel 1 D8 DATA0P Driver Data Input (Positive) Channel 0 D9 VDD Supply +10.0 V D10 OVD_CH0 Overvoltage Detection Flag Output Channel 0 E1 FFCAP_1A PMU Feedforward Capacitor Connection A Channel 1 (220 pF) E2 VSS Supply −5.75 V E3 RCV1N Receive Data Input (Negative) Channel 1 E8 RCV0N Receive Data Input (Negative) Channel 0 E9 VSS Supply −5.75 V E10 FFCAP_0A PMU Feedforward Capacitor Connection A Channel 0 (220 pF) F1 AGND Analog Ground F2 AGND Analog Ground F3 RCV1P Receive Data Input (Positive) Channel 1 F8 RCV0P Receive Data Input (Positive) Channel 0 F9 AGND Analog Ground F10 AGND Analog Ground G1 COMP_QL1P Low-Side Comparator Output (Positive) Channel 1 G2 COMP_QL1N Low-Side Comparator Output (Negative) Channel 1 G3 COMP_VTT1 Comparator Supply Termination Channel 1 G8 COMP_VTT0 Comparator Supply Termination Channel 0 G9 COMP_QL0N Low-Side Comparator Output (Negative) Channel 0 G10 COMP_QL0P Low-Side Comparator Output (Positive) Channel 0 H1 COMP_QH1P High-Side Comparator Output (Positive) Channel 1 H2 COMP_QH1N High-Side Comparator Output (Negative) Channel 1 H3 AGND Analog Ground H4 VSS Supply −5.75 V H5 VDD Supply +10.0 V H6 VDD Supply +10.0 V H7 VSS Supply −5.75 V H8 AGND Analog Ground

Rev. A | Page 23 of 58 BGA Designator Mnemonic Description H9 COMP_QH0N High-Side Comparator Output (Negative) Channel 0 H10 COMP_QH0P High-Side Comparator Output (Positive) Channel 0 J1 AGND Analog Ground J2 AGND Analog Ground J3 AGND Analog Ground J4 DAC16_MON 16-Bit DAC Monitor Mux Output J5 DGND Digital Ground J6 SDIN Serial Peripheral Interface (SPI) Data In J7 RST Serial Peripheral Interface (SPI) Reset J8 AGND Analog Ground J9 AGND Analog Ground J10 AGND Analog Ground K1 MEASOUT01/TEMPSENSE Muxed Output Shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1, Temperature Sense and Temperature Sense GND Reference K2 DUTGND DUT Ground Reference K3 AGND Analog Ground K4 CS Serial Peripheral Interface (SPI) Chip Select K5 SDOUT Serial Peripheral Interface (SPI) Data Out K6 SCLK Serial Peripheral Interface (SPI) Clock K7 VCC Supply +3.3 V K8 AGND Analog Ground K9 VREF +5 V DAC Reference Voltage K10 VREF_GND DAC Ground Reference

EXPOSED PAD IS CONNEC TED TO V

Figure 3. 100-Lead TQFP_EP Pin Configuration Table 17. Pin Function Descriptions 1 NC No Connect. No physical connection to die. 2 NC No Connect. No physical connection to die. 3 TEMPSENSE Temperature Sense Output. 4 VDD/VDD_TMPSNS Temperature Sense Supply +10.0 V. 5 SCAP1 PMU Stability Capacitor Connection Channel 1 (330 pF). 6 FFCAP_1B PMU Feed Forward Capacitor Connection B Channel 1 (220 pF). 8 OVD_CH1 Overvoltage Detection Flag Output Channel 1. 9 DATA1N Driver Data Input (Negative) Channel 1. 10 DATA1P Driver Data Input (Positive) Channel 1. 11 FFCAP_1A PMU Feedforward Capacitor Connection A Channel 1 (220 pF).

Rev. A | Page 25 of 58 Pin No. Mnemonic Description 13 RCV1N Receive Data Input (Negative) Channel 1. 14 RCV1P Receive Data Input (Positive) Channel 1. 15 AGND Analog Ground. 16 COMP_QL1P Low-Side Comparator Output (Positive) Channel 1. 17 COMP_QL1N Low-Side Comparator Output (Negative) Channel 1. 18 COMP_VTT1 Comparator Supply Channel 1. 19 COMP_QH1P High-Side Comparator Output (Positive) Channel 1. 20 COMP_QH1N High-Side Comparator Output (Negative) Channel 1. 21 AGND Analog Ground. 22 AGND Analog Ground. 23 AGND Analog Ground. 24 NC No Connect. No physical connection to die. 25 NC No Connect. No physical connection to die. 26 NC No Connect. No physical connection to die. 27 NC No Connect. No physical connection to die. 28 MEASOUT01/TEMP SENSE Shared Muxed Output. Muxed output shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1, and the temperature sense and temperature sense GND reference. 29 DUTGND Device Under Test Ground Reference. 30 AGND Analog Ground. 31 AGND Analog Ground. 32 CS Serial Peripheral Interface (SPI®) Chip Select. 33 DAC16_MON 16-Bit DAC Monitor Mux Output. 34 VSS Supply −5.75 V. 35 VDD Supply +10.0 V. 36 DGND Digital Ground. 37 SDOUT Serial Programmable Interface (SPI) Data Output. 38 SCLK Serial Programmable Interface (SPI) Clock. 39 SDIN Serial Programmable Interface (SPI) Data Input. 40 VDD Supply +10.0 V. 41 VCC Supply +3.3 V. 42 VSS Supply −5.75 V. 43 RST Serial Peripheral Interface (SPI) Reset. 44 AGND Analog Ground. 45 AGND Analog Ground. 46 AGND Analog Ground. 47 VREF +5 V DAC Reference Voltage. 48 VREF_GND DAC Ground Reference. 49 NC No Connect. No physical connection to die. 50 NC No Connect. No physical connection to die. 51 NC No Connect. No physical connection to die. 52 NC No Connect. No physical connection to die. 53 AGND Analog Ground. 54 AGND Analog Ground. 55 AGND Analog Ground. 56 Comp_QH0N High-Side Comparator Output (Negative) Channel 0. 57 Comp_QH0P High-Side Comparator Output (Positive) Channel 0. 58 Comp_VTT0 Comparator Supply Channel 0. 59 Comp_QL0N Low-Side Comparator Output (Negative) Channel 0. 60 Comp_QL0P Low-Side Comparator Output (Positive) Channel 0.

Rev. A | Page 26 of 58 Pin No. Mnemonic Description 61 AGND Analog Ground. 62 RCV0P Receive Data Input (Positive) Channel 0. 63 RCV0N Receive Data Input (Negative) Channel 0. 64 VSS Supply −5.75 V. 65 FFCAP_0A PMU Feedforward Capacitor Connection A Channel 0 (220 pF). 66 DATA0P Driver Data Input (Positive) Channel 0. 67 DATA0N Driver Data Input (Negative) Channel 0. 68 OVD_CH0 Overvoltage Detection Flag Output Channel 0. 69 VDD Supply +10.0 V. 70 FFCAP_0B PMU Feedforward Capacitor Connection B Channel 0 (220 pF). 71 SCAP0 PMU Stability Capacitor Connection Channel 0 (330 pF). 72 VPLUS Supply +16.75 V. 73 HVOUT High Voltage Driver Output. 74 NC No Connect. No physical connection to die. 75 NC No Connect. No physical connection to die. 76 NC No Connect. No physical connection to die. 77 NC No Connect. No physical connection to die. 78 PMUS_CH0 PMU External Sense Path Channel 0. 79 VSS Supply −5.75 V. 80 VDD Supply +10.0 V. 81 VSSO_0 (DRIVE) Driver Output Supply −5.75 V Channel 0. 82 DUT0 Device Under Test Channel 0. 83 VDDO_0 (DRIVE) Driver Output Supply +10.0 V Channel 0. 84 AGND Analog Ground. 85 AGND Analog Ground. 86 VSS Supply −5.75 V. 87 VDD Supply +10.0 V. 88 AGND Analog Ground. 89 VDD Supply +10.0 V. 90 VSS Supply −5.75 V. 91 AGND Analog Ground. 92 AGND Analog Ground. 93 VDDO_1 (DRIVE) Driver Output Supply +10.0 V Channel 1. 94 DUT1 Device Under Test Channel 1. 95 VSSO_1 (DRIVE) Driver Output Supply −5.75 V Channel 1. 96 VDD Supply +10.0 V. 97 VSS Supply −5.75 V. 98 PMUS_CH1 PMU External Sense Path Channel 1. 99 NC No Connect. No physical connection to die. 100 NC No Connect. No physical connection to die. EP Exposed Pad. The exposed pad is connected to VSS.

Figure 34. Comparator Shmoo;

1.0 V Swing; 200 ps (10%/90%)

Figure 35. Comparator Shmoo; Figure 36. Comparator Minimum Pulse Width Input; Figure 38. Comparator Output Waveform; COMP_QH0P, COMP_QH0N Figure 39. Comparator Threshold Linearity

Figure 76. SPI Timing Diagram Table 18. Serial Peripheral Interface Timing Requirements

2 SCLK cycles

16 SCLK cycles

1 Extra cycle is needed after read request to prime read data into SPI shift register.

selects, one R/W selector, and a 5-bit address. Depending on the operation, the data can be smaller (or nonexistent in the case of a read operation). are applied to the 14-bit DAC. Write 14 bits of data to the DAC. Write two bits of data to the 2-bit register. Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored, while Bit 1 through Bit 0 are applied to the register. Read request and follow with a 2nd instruction (could be NOP) to clock out the data. Table 19. Channel Selection Table 20. R/W Definition

0 Current register specified by address is shifted out

1 Current data is written to register specified by

for a minimum of two SCLK cycles. MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION. Figure 87. Reset Operation

The ADDR[4:0] bits determine the destination register of the data being written to the ADATE302-02. Table 21. Register Selection

Table 22. PE/PMU Enable (ADDR[4:0] = 0x0C) When set to 0, the PMU State bits are ignored, except for PMU Sense Path (Data[7]). See Table 30 for complete functionality of this bit. See Table 30 for complete functionality of this bit. Table 23. Channel State (ADDR[4:0] = 0x0D) This bit affects Channel 0 only. Ensure that Channel 0 bit in SPI write is active. Channel 1 bit in SPI write is don’t care. See Table 30 for complete functionality of this bit. See Table 30 for complete functionality of this bit. Table 24. PMU State (ADDR[4:0] = 0x0E)1, 2 mode. Data[9:8] and Data[6:0] of the PMU state register are ignored, and only Data[7], the PMU sense path bit, is valid.

Table 25. PMU Measure Enable (ADDR[4:0] = 0x0F)1 1 This register is written to or read from if either of the CH[1:0] bits is 1. Table 26. Differential Comparator Enable (ADDR[4:0] = 0x10) 1 1 This register is written to or read from if either of the CH[1:0] bits is 1. Table 27. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11) 1 1 This register is written to or read from if either of the CH[1:0] bits is 1. Table 28. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12) Table 29. OVD_CHx Alarm State (ADDR[4:0] = 0x13)1 1 This register is a read-only register.

Table 30. Driver and Load Truth Table1

1 X X X X X High-Z without

Table 31. HVOUT Truth Table1

0 X X Disabled (HVOUT pin set to 0 V low impedance)

Table 32. Comparator Truth Table

0 Normal window mode

1 Differential comparator mode

−2.5 V to +7.5 V; tracks DUTGND. Controls VH, VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.
−3.0 V to +7.0 V; tracks DUTGND. Controls OVD levels.
−2.5 V to +7.5 V; does not track DUTGND. Controls IOH and IOL levels. There is one 16-bit DAC per channel. This DAC provides the levels for the PMU. The output level is:
−2.5 V to +7.5 V; tracks DUTGND. Controls PMU levels.

Table 33. Level Transfer Functions 1 Programmable range includes margin outside of specified part performance, allowing for offset/gain calibration. Table 34. Load Transfer Functions 1 V(IOH), V(IOL) DAC levels are not referenced to DUTGND. Table 35. PMU Transfer Functions 1 R = 20 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.

Table 36. PMU User Required Capacitors Table 37. Temperature Sensor

0 K 0 V

300 K 3 V

Table 38. Default Test Conditions

Rev. A | Page 50 of 58 RECOMMENDED PMU MODE SWITCHING SEQUENCES To minimize any possible aberrations and voltage spikes on the DUT output, specific mode switching sequences are recommended for the following transitions:

PMU disable to PMU enable
PMU force voltage mode to PMU force current mode
PMU force current mode to PMU force voltage mode. PMU Disable to PMU Enable Step 1: See Table 39 for state of registers in PMU disabled mode. Table 39. Register Bit Setting PE/PMU Enable Register, ADDR[4:0] = 0x0C Data[2] 0 PMU State Register, ADDR[4:0] = 0x0E Data[9:8] XX Data[7] X Data[6] X Data[5] X Data[4] X Data[3] X Data[2:0] XXX Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 40). Table 40. Register Bit Setting Comments PMU State Register, ADDR[4:0] = 0x0E Data[9:8] 1X or 00 Set desired input selection Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 0 This bit must be set to force voltage mode to reduce aberrations Data[2:0] XXX Set desired range Step 3: Write to Register ADDR[4:0] = 0x0C (see Table 41). Table 41. Register Bit Setting Comments PE/PMU Enable Register, ADDR[4:0] = 0x0C Data[2] 1 PMU is now enabled in force voltage mode

Rev. A | Page 51 of 58 PMU Force Voltage Mode to PMU Force Current Mode Step 1: See Table 42 for state of registers in force voltage mode. Table 42. Register Bit Setting PE/PMU Enable Register, ADDR[4:0] = 0x0C Data[2] 1 PMU State Register, ADDR[4:0] = 0x0E Data[9:8] XX Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 0 Data[2:0] XXX Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 43). Table 43. Register Bit Setting Comments PMU State Register, ADDR[4:0] = 0x0E Data[9:8] 01 Set 2.5 V + VDUTGND input selection Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 1 Set to force current mode Data[2:0] 0XX 2 μA range has the minimum offset current Step 3: Write to Register ADDR[4:0] = 0x0B (see Table 44). Table 44. Register Bit Setting Comments PMUDAC Level, ADDR[4:0] = 0x0B Data[15:0] X Update the PMUDAC level register to the desired value Step 4: Write to Register ADDR[4:0] = 0x0E (see Table 45). Table 45. Register Bit Setting Comments PMU State Register, ADDR[4:0] = 0x0E Data[9:8] 1X PMUDAC input selection Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 1 Set to force current mode Data[2:0] XXX Set to the desired current range

Rev. A | Page 52 of 58 Transition from PMU Force Current Mode to PMU Force Voltage Mode Step 1: See Table 46 for state of registers in force current mode. Table 46. Register Bits Setting PE/PMU Enable Register, ADDR[4:0] = 0x0C Data[2] 1 PMU State Register, ADDR[4:0] = 0x0E Data[9:8] XX Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 1 Data[2:0] XXX Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 47). Table 47. Register Bits Setting Comments PMU State Register, ADDR[4:0] = 0x0E Data[9:8] 00 Set DUTGND input selection Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 0 Set to force voltage mode Data[2:0] XXX Set to the desired current range Step 3: Write to Register ADDR[4:0] = 0x0B (see Table 48). Table 48. Register Bits Setting Comments PMUDAC Level, ADDR[4:0] = 0x0B Data[15:0] X Update the PMUDAC level register to the desired value Step 4: Write to Register ADDR[4:0] = 0x0E (see Table 49). Table 49. Register Bits Setting Comments PMU State Register, ADDR[4:0] = 0x0E Data[9:8] 1X PMUDAC input selection Data[7] X Data[6] X Data[5] X Data[4] X Data[3] 0 Force voltage mode Data[2:0] XXX

SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE D ATA[2] = 0 (ADDR[4:0] = 0x0C), ALL

SWITCHES OPEN AND PMU POWERS DOWN.

THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.
25mA RANGE HAS ITS OWN OUTPUT BUFFER.
25mA BUFFER WILL BE TRISTATED WHEN NOT IN USE.

Figure 92. PMU Block Diagram

2 DATA[2] DATA[1] DATA[0]

2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG. Figure 93. OVD Block Diagram

EXCEPTION TO PACKAGE HEIGHT.

0.90 REF

0.305 REF

Figure 94. 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

14.00 BSC SQ

16.00 BSC SQ

0.08 MAX

0.05 VIEW A

0.50 BSC

Figure 95. 100-Lead Thin Quad Flatpack, Exposed Pad [TQFP_EP]

Rev. A | Page 58 of 58 ORDERING GUIDE Model Temperature Range Package Description Package Option ADATE302-02BBCZ1 −40°C to +85°C 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-84-2 ADATE302-02BSVZ1 −40°C to +85°C 100-Lead Thin Quad Flatpack, Exposed Pad [TQFP_EP] SV-100-7 1 Z = RoHS Compliant Part. ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07278-0-4/09(A)

Summary

500 MHz Dual Integrated DCL 23-Feb-2017

Description