ADAS1000

ADAS1000/ADAS1000-1/ADAS1000-2 (Rev.D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 79

Technical content

ADAS1000/ADAS1000-1/ADAS1000-2 Low Power, Five Electrode Electrocardiogram (ECG) Analog Front End Rev. D DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Biopotential signals in; digitized signals out ►5 acquisition (ECG) channels and one driven lead ►Parallel ICs for up to 10+ electrode measurements ►Primary ADAS1000 or ADAS1000-1 used with secondary ADAS1000-2 ►AC and dc lead-off detection ►Internal pace detection algorithm on 3 leads ►Support for user’s own pace ►Thoracic impedance measurement (internal/external path) ►Selectable reference lead ►Scalable noise vs. power control, power-down modes ►Low power operation from ►11 mW (1 lead), 15 mW (3 leads), 21 mW (all electrodes) ►Lead or electrode data available ►Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38 R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005, IEC60601-2-25 ed. 2.0:2011, IEC60601-2-27 ed. 2.0 b:2005, IEC60601-2-51 ed. 1.0 b:2005 ►Fast overload recovery ►Low or high speed data output rates ►Serial interface SPI-/QSPI™-/DSP-compatible ►56-lead LFCSP package (9 mm × 9 mm) ►64-lead LQFP package (10 mm × 10 mm body size)

APPLICATIONS

►ECG: monitor and diagnostic ►Bedside patient monitoring, portable telemetry, Holter, AED, cardiac defibrillators, ambulatory monitors, pace maker pro- grammer, patient transport, stress testing GENERAL DESCRIPTION The ADAS1000/ADAS1000-1/ADAS1000-2 measure electro car- diac (ECG) signals, thoracic impedance, pacing artifacts, and lead- on/lead-off status and output this information in the form of a data frame supplying either lead/vector or electrode data at programma- ble data rates. Its low power and small size make it suitable for portable, battery-powered applications. The high performance also makes it suitable for higher end diagnostic machines. The ADAS1000 is a full-featured, 5-channel ECG including res- piration and pace detection, while the ADAS1000-1 offers only ECG channels with no respiration or pace features. Similarly, the ADAS1000-2 is a subset of the main device and is configured for gang purposes with only the ECG channels enabled (no respiration, pace, or right leg drive). The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to simplify the task of acquiring and ensuring quality ECG signals. They provide a low power, small data acquisition system for biopotential applications. Auxiliary features that aid in better quality ECG signal acquisition include multichannel averaged driven lead, selectable reference drive, fast overload recovery, flexible respiration circuitry returning magnitude and phase information, internal pace detection algorithm operating on three leads, and the option of ac or dc lead-off detection. Several digital output options ensure flexibility when monitoring and analyzing signals. Value-added cardiac post processing is executed externally on a DSP, microprocessor, or FPGA. Because ECG systems span different applications, the ADAS1000/ ADAS1000-1/ADAS1000-2 feature a power/noise scaling architec- ture where the noise can be reduced at the expense of increasing power consumption. Signal acquisition channels can be shut down to save power. Data rates can be reduced to save power. To ease manufacturing tests and development as well as offer ho- listic power-up testing, the ADAS1000/ADAS1000-1/ADAS1000-2 offer a suite of features, such as dc and ac test excitation via the calibration DAC and cyclic redundancy check (CRC) redundancy testing, in addition to readback of all relevant register address space. The input structure is a differential amplifier input, thereby allowing users a variety of configuration options to best suit their application. The ADAS1000/ADAS1000-1/ADAS1000-2 are available in two package options, a 56-lead LFCSP package and a 64-lead LQFP package. Both packages are specified over a −40°C to +85°C temperature range.

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 TABLE OF CONTENTS analog.com Rev. D | 2 of 79 Electrode/Lead Formation and Input Stage Pacing Artifact Detection Function Pace Detection Via Secondary Serial Interface (ADAS1000 and ADAS1000-1 SPI Output Frame Structure (ECG and Status Power Supply, Grounding, and Decoupling

REVISION HISTORY

5/2024—Rev. C to Rev. D

Figure 1. ADAS1000 Full Featured Model Table 1. Overview of Features Available from ADAS1000 Generics conjunction with any primary device. 2 Primary interface is provided for users wishing to utilize their own digital pace algorithm; see the Secondary Serial Interface section.

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SPECIFICATIONS analog.com Rev. D | 4 of 79 Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. For specified performance, internal ADCVDD and DVDD linear regulators have been used. They may be supplied from external regulators. ADCVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ECG CHANNEL These specifications apply to the following pins: ECG1_LA, ECG2_LL, ECG3_RA, ECG4_V1, ECG5_V2, CM_IN (CE mode), EXT_RESP_xx pins when used in extend switch mode Electrode Input Range Independent of supply 0.3 1.3 2.3 V GAIN 0 (gain setting ×1.4) 0.63 1.3 1.97 V GAIN 1 (gain setting ×2.1) 0.8 1.3 1.8 V GAIN 2 (gain setting ×2.8) 0.97 1.3 1.63 V GAIN 3 (gain setting ×4.2) Input Bias Current −10 ±1 +10 nA Relates to each electrode input; over specified electrode input range; dc and ac lead-off are disabled, applies at ambient temperature, TA = 25°C −20 ±1 +20 nA Relates to each electrode input; over specified electrode input range; dc and ac lead-off are disabled, applies across full temperature range, TA = −40°C to +85°C −200 +200 nA Over full AGND to AVDD input range Input Offset −7 mV Electrode/vector mode with VCM = VCM_REF GAIN 3 −7 mV GAIN 2 −15 mV GAIN 1 −22 mV GAIN 0 Input Offset Tempco1 ±2 μV/°C Input Amplifier Input Impedance2 1||10 GΩ||pF At 10 Hz CMRR2 105 110 dB 51 kΩ imbalance, 60 Hz with ±300 mV differential dc offset; per AAMI/IEC standards; with driven leg loop closed Crosstalk1 80 dB Between channels Resolution2 19 Bits Electrode/vector mode, 2 kHz data rate, 24-bit data-word

18 Bits Electrode/vector mode, 16 kHz data rate, 24-bit data-word

16 Bits Electrode/analog lead mode, 128 kHz data rate, 16-bit data-

Integral Nonlinearity Error 30 ppm GAIN 0; all data rates Differential Nonlinearity Error 5 ppm GAIN 0 Gain2 Referred to input. (2 × VREF)/Gain/(2N − 1); applies after factory calibration; user calibration adjusts this number GAIN 0 (×1.4) 4.9 µV/LSB At 19-bit level in 2 kHz data rate 9.81 μV/LSB At 18-bit level in 16 kHz data rate 39.24 μV/LSB At 16-bit level in 128 kHz data rate GAIN 1 (×2.1) 3.27 μV/LSB At 19-bit level in 2 kHz data rate 6.54 μV/LSB At 18-bit level in 16 kHz data rate 26.15 μV/LSB At 16-bit level in 128 kHz data rate GAIN 2 (×2.8) 2.45 μV/LSB At 19-bit level in 2 kHz data rate 4.9 μV/LSB At 18-bit level in 16 kHz data rate 19.62 μV/LSB At 16-bit level in 128 kHz data rate GAIN 3 (×4.2) 1.63 μV/LSB No factory calibration for this gain setting At 19-bit level in 2 kHz data rate

Table 2. (Continued)

1 Guaranteed by characterization, not production tested. 2 Guaranteed by design, not production tested. 3 ADCVDD and DVDD can be powered from an internal LDO or, alternatively, can be powered from external 1.8 V rail, which may result in a lower power solution. 4 Pace is a digital function and incurs no power penalty. Table 3. Typical Input Referred Noise over 0.5 Second Window (µV p-p)1 1 Typical values measured at 25°C, not subject to production test. Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands. 3 Analog lead mode as shown in Figure 58. Table 4. Typical Input Referred Noise (μV p-p)1

Table 4. Typical Input Referred Noise (μV p-p)1 (Continued) 1 Typical values measured at 25°C, not subject to production test. Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands. 3 Analog lead mode as shown in Figure 58. configurations. See the Electrode/Lead Formation and Input Stage Configuration section. 5 Digital lead mode as shown in Figure 59. 6 Digital lead mode is available in 2 kHz and 16 kHz data rates.

= −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. permanently low. See a full description in the Serial Interfaces section. 1 Guaranteed by characterization, not production tested. 2 Guaranteed by design, not production tested. Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)

ing conditions for extended periods may affect product reliability. soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance1

1 Based on JEDEC standard 4-layer (2S2P) high effective thermal conductivity

test board (JESD51-7) and natural convection. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Table 9. Pin Function Descriptions (Continued) capacitors in the Power Supply, Grounding, and Decoupling Strategy section. the VREG_EN pin tied to ground to disable the ADCVDD and DVDD regulators. Decoupling Strategy section. 59 19 19 59 19 VREG_EN Enables or disables the internal voltage regulators used for ADCVDD and DVDD. 10 6 6 ECG1_LA Analog Input, Left Arm (LA). 11 5 5 ECG2_LL Analog Input, Left Leg (LL). 12 4 4 ECG3_RA Analog Input, Right Arm (RA). 13 3 3 ECG4_V1 Analog Input, Chest Electrode 1 or Auxiliary Biopotential Input (V1). 14 2 2 ECG5_V2 Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2). 4 12 EXT_RESP_RA Optional External Respiration Input. 5 11 EXT_RESP_LL Optional External Respiration Input. 6 10 EXT_RESP_LA Optional External Respiration Input. 19 55 55 19 55 CM_IN Common-Mode Input. 21 53 53 21 53 RLD_SJ Summing Junction for Right Leg Drive Amplifier. 20 54 54 RLD_OUT Output and Feedback Junction for Right Leg Drive Amplifier.

61 17 17 CAL_DAC_IO Calibration DAC Input/Output. Output for a primary device, input for a secondary. Not intended to drive current. 9 7 7 9 7 REFIN Reference Input. For standalone mode, use REFOUT connected to REFIN. reference can be connected to REFIN. 8 8 8 8 8 REFOUT Reference Output. 7 9 9 7 9 REFGND Reference Ground. Connect to a clean ground. also be driven by an external clock as configured through the ECGCTL register. The CLK_IO pin powers up in high impedance. frame the entire suite of data in framing mode. 43 33 33 43 33 SDI Serial Data Input. 53 25 25 53 25 PD Power-Down, Active Low. read to allow DRDY to return high. their power-on reset values. 36 40 40 GPIO0/MCS General-Purpose I/O or Primary 128 kHz SPI CS. 37 39 39 GPIO1/MSCLK General-Purpose I/O or Primary 128 kHz SPI SCLK. 38 38 38 GPIO2/MSDO General-Purpose I/O or Primary 128 kHz SPI SDO. 39 37 37 GPIO3 General-Purpose I/O. 36 40 GPIO0 General-Purpose I/O. 37 39 GPIO1 General-Purpose I/O. 38 38 GPIO2 General-Purpose I/O. 39 37 GPIO3 General-Purpose I/O. 18 SHIELD Output of Shield Driver.

29 45 CLK_IN Buffered Clock Input. Drive this pin from the primary CLK_IO pin. the most negative potential, AGND.

to ensure suitability to these varying requirements. readback of all relevant register address space. Figure 53. ADAS1000 Simplified Block Diagram

other purposes, such as calibration or temperature measurement). 1.3 V; see details in Table 50.

1. Digital lead mode is not available for this data rate.

individual electrode measurements. Table 10. Lead Composition1 secondary device. For correct operation of the secondary device, the device must be configured in electrode mode (see the FRMCTL register in Table 37). 2 These augmented leads are not calculated within the ADAS1000, but can be derived in the host DSP/microcontroller/FPGA.

reference level is removed from the final lead data. contained in the header word (see Table 54). Figure 56. Simplified Schematic of a Single ECG Channel

Figure 62. Electrode and Lead Configurations, Common Electrode B

a usable signal to be obtained from just two electrodes. ►If SW1 is closed, SW7 must be open. nal buffer is required if there is any loading on the CM_OUT pin. Figure 66. Common-Mode Generation Block Table 11. Truth Table for Common-Mode Selection

0 X X X X X X X Powered down, paths disconnected

1 X 1 X X X X X SW1 External VCM selected

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 APPLICATIONS INFORMATION analog.com Rev. D | 36 of 79 CALIBRATION DAC Within the ADAS1000/ADAS1000-1, there are a number of calibra- tion features. The 10-bit calibration DAC can be used to correct channel gain errors (to ensure channel matching) or to provide several test tones. The options are as follows: ►DC voltage output (range: 0.3 V to 2.7 V). The DAC transfer function for dc voltage output is 0 . 3 V + 2 . 4 V × c o de 2 10 − 1 (1) ►1 mV p-p sine wave of 10 Hz or 150 Hz ►1 mV 1 Hz square wave Internal switching allows the calibration DAC signals to be routed to the input of each ECG channel (see Figure 65). Alternatively, it can be driven out from the CAL_DAC_IO pin, enabling measurement and correction for external error sources in the entire ECG signal chain and/or for use as an input to the ADAS1000-2 companion chip calibration input. To ensure a successful update of the calibration DAC (see Table 36), the host controller must issue four additional SCLK cycles after writing the new calibration DAC register word. GAIN CALIBRATION The gain for each ECG channel can be adjusted to correct for gain mismatches between channels. Factory trimmed gain correction coefficients are stored in nonvolatile memory on‑ chip for GAIN 0, GAIN 1, and GAIN 2; there is no factory calibration for GAIN 3. The default gain values can be overwritten by user gain correction coefficients, which are stored in volatile memory and available by addressing the appropriate gain control registers (see Table 51). The gain calibration applies to the ECG data available on the standard interface and applies to all data rates. LEAD-OFF DETECTION An ECG system must be able to detect if an electrode is no longer connected to the patient. The ADAS1000/ADAS1000-1/ ADAS1000-2 support two methods of lead-off detection, ac lead-off detection and dc lead-off detection. The two systems are independ- ent and can be used singly or together under the control of the serial interface (see Table 29). A lead-off event sets a flag in the frame header word (see Table 54). Identification of which electrode is off is available as part of the data frame or as a register read from the lead‑ off status register (Register LOFF, see Table 47). In the case of ac lead-off, information about the amplitude of the lead-off signal or signals can be read back through the serial interface (see Table 52). In a typical ECG configuration, the electrodes RA, LA, and LL are used to generate a common mode of Wilson Central Terminal (WCT). If one of these electrodes is off, this affects the WCT signal and any lead measurements that it contributes to. As a result, the ECG measurements on these signals are expected to degrade. The user has full control over the common mode amplifier and can adjust the common-mode configuration to remove that electrode from the common-mode generation. In this way, the user can continue to make measurements on the remaining connected leads. DC Lead-Off Detection This method injects a small programmable dc current into each in- put electrode. When an electrode is properly connected, the current flows into the right leg (RLD_OUT) and produces a minimal voltage shift. If an electrode is off, the current charges the capacitance of that pin, causing the voltage at the pin to float positive and create a large voltage change that is detected by the comparators in each channel. These comparators use fixed, gain-independent upper and lower threshold voltages of 2.4 V and 0.2 V, respectively. If the input exceeds either of these levels, the lead-off flag is raised. The lower threshold is included in the event that something pulls the electrode down to ground. The dc lead-off detection current can be programmed via the serial interface. Typical currents range from 10 nA to 70 nA in 10 nA steps. All input pins (RA, LA, LL, V1, V2, and CM_IN) use identical dc lead-off detection circuitry. Detecting if the right-leg electrode has fallen off is necessarily different as RLD_OUT is a low impedance amplifier output. A pair of fixed threshold comparators monitor the output voltage to detect amplifier saturation that would indicate a lead-off condition. This information is available in the DCLEAD-OFF register (Register 0x1E) along with the lead-off status of all the input pins. The propagation delay for detecting a dc lead-off event depends on the cable capacitance and the programmed current. It is approxi- mately Delay = Voltage × Cable Capacitance/Programmed Current(2) For example: Delay = 1.2 V × (200 pF/70 nA) = 3.43 ms DC Lead-Off and High Gains Using dc lead-off at high gains can result in failure of the circuit to flag a lead-off condition. The chopping nature of the input amplifier stage contributes to this situation. When the electrode is off, the electrode is pulled up; however, in this gain setting, the first stage amplifier goes into saturation before the input signal crosses the dc lead-off (DCLO) upper threshold, resulting in no lead-off flag. This affects the gain setting GAIN 3 (4.2) and partially GAIN 2 (2.8). Increasing the AVDD voltage raises the voltage at which the input amplifiers saturate, allowing the off electrode voltage to rise high enough to trip the DCLO comparator (fixed upper threshold of 2.4

mation (see the ADC Out of Range section). the debounce timer counts down to (and saturates at) all zeros. Figure 68. Simplified AC Lead-Off Configuration CM_IN) and is not supported for the RLD_OUT pin. low pass filtered and sent to the digital threshold detectors. divider (source and cable capacitance). many of the circuit variables. connected. The lower threshold checks for a minimum signal level. resulting voltage measurement available on a per channel basis. mode, the amplitude result for the measured electrode is returned. higher codes in the ac lead-off results. range or the ac lead-off flag is set.

The propagation delay for detecting an ac lead-off event is <10 ms. from the RLD contribution and the common mode contribution. determine which electrode degraded or fell off. external amplifier connected to the CM_OUT pin can be used. the peak detection needed to establish breathing (or lack thereof). Switch On Respiration Paths section. Table 12. Maximum Allowable Cable and Thoracic Loading

Figure 69. Simplified Respiration Block Diagram

influence on the carrier frequency as shown in Table 13. Table 13. Control of Respiration Carrier Frequencies.

0 X3 1 00 56

1 X 0 00 32

1 X 0 01 28

1 X 0 11 23

1 Control bits from RESPCTL (Register 0x03). 2 Control bit from ECGCTL (Register 0x01). control register (see Table 30). Table 14. Control of Respiration Carrier Frequency Available on GPIO3 1 Control bits from RESPCTL (Register 0x03). 2 Control bit from ECGCTL (Register 0x01). filter the latency as described in Table 16. Figure 72. Alternative Use of the Respiration Paths artifacts and measures the width and amplitude of valid pulses.

detection algorithm is shown in Figure 74. respiration impedance measurement circuitry enabled. 0x3A to Address 0x3C) as shown in Table 53. (Lead I, Lead II, Lead III, and aVF) for pacing artifact detection. filter cutoff, and mode (electrode, analog lead, common electrode). urations as detailed in Table 15. be used for each of the three pace detection state machines. can be disabled if not in use. 44). The pace algorithm looks for a negative or positive pulse. Table 15. Pace Lead Calculation 1 Register ECGCTL, Bit CHCONFIG, see Table 28. 2 Register CMREFCTL, Bit CEREFEN, see Table 32. 3 Register PACECTL, Bit PACExSEL [1:0], see Table 31.

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 APPLICATIONS INFORMATION analog.com Rev. D | 44 of 79 Pace Level Threshold This programmable level (Address 0x0F, see Table 42) is used to detect when the leading edge of a candidate pulse ends. In general, a pace pulse is not perfectly square, and the top, meaning the portion after the leading edge, may continue to increase slightly or droop back towards the baseline. PACELVLTH defines an allowable slope for this portion of the candidate pulse, where the slope is defined as the change in value over an internally-fixed interval after the pace edge is qualified. PACELVLTH is an 8-bit, twos complement number. Positive values represent movement away from the baseline (pulse amplitude is still increasing) while negative values represent droop back towards the baseline. P A CE L VL TH s ett i n g = N × V REF G A I N × 2 16 (4) where: N is the 8-bit programmed PACELVLTH value (−128 ≤ N ≤ 127). VREF is the ADAS1000 reference voltage of 1.8 V. GAIN is the programmed gain of the ECG channel. The minimum value for ×1.4 gain is 9.8 µV, while the maximum for the same gain setting is 2.50 mV. An additional qualification step, performed after PACELVLTH is satisfied, rejects pulses with a leading edge transition time great- er than about 156 µs. This filter improves immunity to motion and other artifacts and cannot be disabled. Overly aggressive ESIS filtering causes this filter to disqualify valid pace pulses. In such cases, increasing the value of PACEEDGETH provides more robust pace pulse detection. Although counterintuitive, this change forces a larger initial deviation from the recent baseline before the pace detection algorithm starts, reducing the time until PACELVLTH comes into play and shortening the apparent leading edge transition. Increasing the value of PACEEDGETH may require a reduction in PACEAMPTH. Pace Amplitude Threshold This register (Address 0x07, see Table 34) sets the minimum valid pace pulse amplitude. PACEAMPTH is an unsigned 8-bit number. The programmed height is given by: P A CE A MPTH s ett i ng = 2 × N × VRE F G AI N × 2 16 (5) where: N is the 8-bit programmed PACEAMPTH value (1 ≤ N ≤ 255). VREF is the ADAS1000 reference voltage of 1.8 V. GAIN is the programmed gain of the ECG channel. The minimum threshold for ×1.4 gain is 19.6 µV, while the maxi- mum for the same gain setting is 5.00 mV. PACEAMPTH is typically set to the minimum expected pace amplitude and must be larger than the value of PACEEDGETH. The default register setting of N = 0x24 results in 1.4 mV for a gain = 1 setting. An initial PACEAMPTH setting between 1.4 mV and 2 mV provides a good starting point for both unipolar and biventricular pacing detection. Values below 250 µV are not recommended because they greatly increase sensitivity to ambient noise from the patient. The amplitude may need to be adjusted much higher than 1 mV when other medical devices are connected to the patient. Pace Validation Filters A candidate pulse that successfully passes the combined tests of PACEEDGETH, PACELVLTH, and PACEAMPTH is next passed through two optional validation filters. These filters are used to re- ject sub-threshold pulses such as minute ventilation (MV) pulse and signals from inductively coupled implantable telemetry systems. These filters perform different tests of pulse shape using a number of samples. Both filters are enabled by default; Filter 1 is controlled by Bit 9 in the PACECTL register (see Table 31) and Filter 2 is controlled by Bit 10 in the same register. These filters are not available on a lead by lead basis; if enabled, they are applied to all leads being used for pace detection. Pace Width Filter A candidate pulse that successfully passes the edge, amplitude, and noise filters is finally checked for width. When this final filter is enabled, it checks that the candidate pulse is between 100 μs and 2 ms wide. When a valid pace width is detected, the width is stored. Disabling this filter affects only the minimum width (100 µs) determination; the maximum width detection portion of the filter is always active. This filter is controlled by the PACECTL register, Bit 11 (see Table 31). BIVENTRICULAR PACERS As described previously, the pace algorithm expects the pace pulse to be less than 2 ms wide. In a pacer where both ventricles are paced, they can be paced simultaneously. Where they fall within the width and height limits programmed into the algorithm, a valid pace is flagged, but only one pace pulse may be visible. With the pace width filter enabled, the pace algorithm seeks pace pulse widths within a 100 μs to 2 ms window. Assuming that this filter is enabled and in a scenario where two ventricle pacer pulses fire at slightly different times, resulting in the pulse showing in the lead as one large, wider pulse, a valid pace is flagged so long as the total width does not exceed 2 ms. PACE DETECTION MEASUREMENTS Design verification of the ADAS1000 digital pace algorithm includes detection of a range of simulated pace signals in addition to using the ADAS1000 and evaluation board with one pacemaker device connected to various simulated loads (approximately 200 Ω to over 2 kΩ) and covering the following 4 waveform corners. ►Minimum pulse width (100 μs), minimum height (to <300 μV)

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 APPLICATIONS INFORMATION analog.com Rev. D | 45 of 79 ►Minimum pulse width (100 μs), maximum height (up to 1.0 V) ►Maximum pulse width (2 ms), minimum height (to <300 μV) ►Maximum pulse width (2 ms), maximum height (up to 1.0 V) These scenarios passed with acceptable results. The use of the ac lead-off function had no obvious impact on the recorded pace height, width, or the ability of the pace detection algorithm to identi- fy a pace pulse. The pace algorithm was also evaluated with the respiration carrier enabled; again, no differences in the threshold or pacer detect were noted from the carrier. While these experiments validate the pace algorithm over a con- fined set of circumstances and conditions, they do not replace end system verification of the pacer algorithm. This can be performed in only the end system, using the system manufacturer’s specified cables and validation data set. EVALUATING PACE DETECTION PERFORMANCE ECG simulators offer a convenient means of studying the perform- ance and ability of the ADAS1000 to capture pace signals over the range of widths and heights defined by the various regulatory standards. While the pace detection algorithm of the ADAS1000 is designed to conform to medical instrument standards (pace widths of 100 μs to 2.00 ms and with amplitudes of <400 μV to >1000 mV), some simulators put out signals wider or narrower than called for in the standards. The pace detection algorithm has been designed to measure a maximum pace widths of 2 ms with a margin of 0.25 ms to allow for simulator variations. PACE WIDTH The ADAS1000 is capable of measuring pace widths of 100 μs to 2.00 ms. The measured pace width is available through the PACExDATA registers. These registers have limited resolution. The minimum pace width is 101.56 μs and the maximum is 2.00 ms. The pace detection algorithm always returns a width greater than what is measured at the 50% point, ensuring that the algorithm is capable of measuring a narrow 100 μs pulse. A valid pulse width of 100 μs is reported as 101.56 μs. Any valid pace pulses ≥ 2.00 ms and ≤ 2.25 ms are reported as 2.00 ms. PACE LATENCY The pace algorithm always examines 128 kHz, 16-bit ECG data, regardless of the selected frame rate and ECG filter setting. A pace pulse is qualified when a valid trailing edge is detected and is flagged in the next available frame header. Pace and ECG data is always correctly time-aligned at the 128 kHz frame rate, but the additional filtering inherent in the slower frame rates delays the ECG data of the frame relative to the pace pulse flag. These delays are summarized in Table 16 and must be taken into account to enable correct positioning of the pace event relative to the ECG data. There is an inherent one-frame-period uncertainty in the exact location of the pace trailing edge. PACE DETECTION VIA SECONDARY SERIAL INTERFACE (ADAS1000 AND ADAS1000-1 ONLY) The ADAS1000/ADAS1000-1 provide a second serial interface for users who want to implement their own pace detection schemes. This interface is configured as a primary interface. It provides ECG data at the 128 kHz data rate only. The purpose of this interface is to allow the user to access the ECG data at a rate sufficient to allow them to run their own pace algorithm, while maintaining all the filtering and decimation of the ECG data that the ADAS1000/ ADAS1000-1 offer on the standard serial interface (2 kHz and 16 kHz data rates). This dedicated pace interface uses three of the four GPIO pins, leaving one GPIO pin available even when the secondary serial interface is enabled. Note that the on-chip digital calibration to ensure channel gain matching does not apply to data that is available on this interface. This interface is discussed in more detail in the Secondary Serial Interface section. FILTERING Figure 75 shows the ECG digital signal processing. The ADC sample rate is programmable. In high performance mode, it is 2.048 MHz; in low power mode, the sampling rate is reduced to 1.024 MHz. The user can tap off framing data at one of three data rates, 128 kHz, 16 kHz, or 2 kHz. Note that although the data-word width is 24 bits for the 2 kHz and 16 kHz data rate, the usable bits are 19 and 18, respectively. The amount of decimation depends on the selected data rate, with more decimation for the lower data rates. Four selectable low-pass filter corners are available at the 2 kHz data rate. Filters are cleared by a reset. Table 16 shows the filter latencies at the different data rates.

Figure 75. ECG Channel Filter Signal Flow Table 16. Relationship of ECG Waveform to Pace Indication1, 2, 3 1 ECG waveform delay is the time required to reach 50% of final value following a step input. 2 Guaranteed by design, not subject to production test. 3 There is an unavoidable residual uncertainty of 8 μs in determining the pace pulse trailing edge. 4 Add 38 μs to obtain the absolute delay for any setting.

pins as possible and on the same side of the PCB as the device. easily extend to larger systems by paralleling up multiple devices. ondary devices have been made available. SYNC_GANG pin is automatically set as an output. the SYNC_GANG and CLK_IO pins are set as inputs. impedance until configured in gang mode. Figure 76. Primary/Secondary Device Connections in Gang Mode, Using the same signal which results in better matching across channels.

to a primary and secondary device. device or separate SDO paths. ensure that the number of lines requiring isolation is minimized. Table 17. Some Possible Arrangements for Gang Operation Figure 78. One Method of Interfacing to Multiple Devices

operate at SCLK frequencies up to 40 MHz. data-words and other status functions within the device. low for the first bit of the following word. on the rising edges of SCLK. Figure 79. Serial Interface face works with both a continuous and a burst (gated) serial clock. taken low again. Register writes are used to configure the device. write new configuration data to the device while in framing mode. Address, data, and the read/write bits are all in the same word. Table 18. Similarly, when using data rates of 2 kHz and 16 kHz, each word is 32 bits (address bits and data bits). Table 18. Serial Bit Assignment (Applies to All Register Writes, 2 kHz and 16 Table 19. Write/Read Data Stream

example, pace and respiration). are provided in 16-bit data format (see Table 23). held constantly low during the entire frame. Table 20. Example of Reading Registers and Frames Regular register reads are always 32 bits long and MSB first. Table 21. SCLK Clock Frequency vs. Packet Data/Frame Rates be configured to provide only the words of interest. See Table 37. Table 22. Default 2 kHz and 16 kHz Data Rate: 32-Bit Frame Word Format Table 23. Default 128 kHz Data Rate: 16-Bit Frame Word Format1 1 Respiration phase words (2 × 16-bit words) are not shown in this frame, but can be included.

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SERIAL INTERFACES analog.com Rev. D | 52 of 79 Internal operations are synchronized to the internal main clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1 and HP = 0, respectively, see Table 28). Because there is no guaranteed relationship between the internal clock and the SCLK signal of the SPI, an internal handshaking scheme is used to ensure safe data transfer between the two clock domains. A full handshake requires three internal clock cycles and imposes an upper speed limit on the SCLK frequency when reading frames with small word counts. This is true for all data frame rates. SCLK (max) = (1.024 MHz × (1 + HP) × words_per_frame × bits_per_word)/3; or 40 MHz, whichever is lower. (7) Exceeding the maximum SCLK frequency for a particular operating mode causes erratic behavior in the DRDY signal and results in the loss of data. Data Rate and Skip Mode Although the standard frame rates available are 2 kHz, 16 kHz, and 128 kHz, there is also a provision to skip frames to further reduce the data rate. This can be configured in the frame control register (see Table 37). Data Ready (DRDY) The DRDY pin is used to indicate that a frame composed of decimated data at the selected data rate is available to read. It is high when busy and low when ready. Send commands only when the status of DRDY is low or ready. During power-on, the status of DRDY is high (busy) while the device initializes itself. When initialization is complete, DRDY goes low and the user can start configuring the device for operation. When the device is configured and enabled for conversions by writing to the conversion bit (CNVEN) in the ECGCTL register, the ADCs start to convert and the digital interface starts to make data available, loading them into the buffer when ready. If conversions are enabled and the buffer is empty, the device is not ready and DRDY goes high. Once the buffer is full, DRDY goes low to indicate that data is ready to be read out of the device. If the device is not enabled for conversions, the DRDY ignores the state of the buffer full status. When reading packets of data, the entire data packet must be read; otherwise, DRDY stays low. There are three methods of detecting DRDY status. ►DRDY pin. This is an output pin from the ADAS1000/ ADAS1000-1/ADAS1000-2 that indicates the device read or busy status. No data is valid while this pin is high. The DRDY signals that data is ready to be read by driving low and remaining low until the entire frame has been read. It is cleared when the last bit of the last word in the frame is clocked onto SDO. The use of this pin is optional. ►SDO pin. The user can monitor the voltage level of the SDO pin by bringing CS low. If SDO is low, data is ready; if high, busy. This does not require clocking the SCLK input. (CPHA = CPOL = 1 only). ►One of the first bits of valid data in the header word available on SDO is a data ready status bit (see Table 43). Within the configuration of the ADAS1000/ADAS1000-1/ADAS1000-2, the user can set the header to repeat until the data is ready. See Bit 6 (RDYRPT) in the frame control register in Table 37. The host controller must read the entire frame to ensure DRDY returns low and ready. If the host controller treats the DRDY as an edge triggered signal and then misses a frame or underruns, the DRDY remains high because there is still data available to read. The host controller must treat the DRDY signal as level triggered, ensuring that whenever it goes low, it generates an interrupt which can initiate a SPI frame transfer. On completion of the transfer the DRDY returns high. Detecting Missed Conversion Data To ensure that the current data is valid, the entire frame must be read at the selected data rate. If a read of the entire frame takes longer than the selected data rate allows, the internal buffer is not loaded with the latest conversion data. The frame header register (see Table 54) provides four settings to indicate an overflow of frame data. The settings of Bits[29:28] report how many frames have been missed since the last valid frame read. A missed frame may occur as a result of the last read taking too long. The data in the current frame is valid data, but it is not the current data. It is the calculation made directly after the last valid read. To clear such an overflow, the user must read the entire frame. SPI INTERFACE RESYNC The ADAS1000 interface supports frame mode and accepts com- mands to reconfigure the device during frame reads. In the event of communication issues when interrupting frame reads, it is possible to resync the interface by keeping SDI high for 64 SCLK cycles, followed by a read of any register so that SDI is brought low for the first bit of the following word. CRC Word Framed data integrity is provided by CRCs. For the 128 kHz frame rates, the 16-bit CRC-CCITT polynomial is used. For the 2 kHz and 16 kHz frame rates, the 24-bit CRC polynomial used. In both cases, the CRC residue is preset to all 1s and inverted before being transmitted. The CRC parameters are summarized in Table 24. To verify that data is correctly received, software computes a CRC on both the data and the received checksum. If data and checksum are received correctly, the resulting CRC residue equals the check constant shown in Table 24. Note that data is shifted through the generator polynomial MSB first, the same order that it is shifted out serially. The bit and byte order of the CRC that is appended to the frame is such that the MSB of the CRC is shifted through the generator polynomial first in the same

crystal or clock input frequency of 8.192 MHz. respiration frequency, and pace algorithm corners accordingly. Figure 80. Input Clock capacitance may cause issues with startup. frequency error is <500 ppm. Table 24. CRC Polynomials

plied. If this interface is inactive, it draws no power. Data is available in 16-bit words, MSB first. This interface can be enabled via the GPIO register (see Table 33). Figure 81. Primary SPI Interface for External Pace Detection Purposes same CRC word as documented in Table 24 for the 128 kHz rate. individual channels are not enabled. the contents of all internal registers to their power-on reset state. the status of the RESET pin is ignored until it goes low again. Table 25. Primary SPI Frame Format; All Words are 16 Bits 1 As set by the FRMCTL register data DATAFMT, Bit [4], see Table 37.

data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data). Table 26. SPI Register Memory Map 1 R/W = register both readable and writable; R = read only.

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SPI REGISTER DEFINITIONS AND MEMORY MAP analog.com Rev. D | 57 of 79 2 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. 3 Reserved bits in any register are undefined. In some cases a physical (but unused) memory bit may be present—in other cases not. Do not issue commands to reserved registers/space. Read operations of unassigned bits are undefined.

format applies throughout the register map. Table 27. Serial Bit Assignment Table 28. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000 R/W 0 23 LAEN ECG channel enable; shuts down power to the channel; the input becomes high-Z. R/W 0 22 LLEN 0 (default) = disables ECG channel. When disabled, the entire ECG channel is shut down and dissipating minimal power. R/W 0 20 V1EN 1 = enables ECG channel. R 0 [18:11] Reserved Reserved, set to 0. R/W 0 10 CHCONFIGSetting this bit selects the differential analog front end (AFE) input. See Figure 58. 0 (default) = single-ended input (digital lead mode or electrode mode). 1 = differential input (analog lead mode). R/W 00 [9:8] GAIN [1:0] Preamplifier and anti-aliasing filter overall gain. 11 = GAIN 3 = ×4.2 (user gain calibration is required for this gain setting). R/W 0 7 VREFBUF VREF buffer enable. 1 = enabled (when using the internal VREF, VREFBUF must be enabled). appropriate clock (XTAL or CLK_IO) when configured on the first write to the CLKEXT bit. 0 (default) = XTAL is clock source. mode (gang = 0), this bit is ignored. ADAS1000-2 cannot be configured as a primary device. 0 (default) = secondary device. R/W 0 4 Gang Enable gang mode. Setting this bit causes CLK_IO and SYNC_GANG to be activated. 0 (default) = single channel mode. 0 (default) = 1 MSPS, low power. 1 = 2 MSPS, high performance/low noise. R/W 0 2 CNVEN Conversion enable. Setting this bit enables the ADC conversion and filters. disabled. The register contents are retained during power down as long as DVDD is not removed.

Table 28. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000 (Continued) reset requires a NOP command to complete the reset. Table 29. Lead-Off Control Register (LOFFCTL) Address 0x02, Reset Value = 0x000000 R/W 0 23 LAPH AC lead-off phase. R/W 0 22 LLPH 0 (default) = in phase. R/W 0 15 RAACLOEN 0 (default) = ac lead-off disabled. R/W 0 14 V1ACLOEN 1 = ac lead-off enabled. R 0 [11:9] Reserved Reserved, set to 0. R/W 00 [8:7] ACCURRENT Set current level for ac lead-off. 00 [6:5] Reserved Reserved, set to 0. R/W 000 [4:2] DCCURRENT Set current level for dc lead-off (active only for ACSEL = 0). R/W 0 1 ACSEL DC or AC (out-of-band) lead-off detection. ACSEL). AC lead-off enables are the OR of ACSEL and the individual ac lead-off channel enables. If LOFFEN = 0, this bit is don’t care. 0 (default) = dc lead-off detection enabled (individual ac lead-off can be enabled through Bits[17:12]). 1 = dc lead-off detection disabled. AC lead-off detection enabled (all electrodes except CE electrode). When the calibration DAC is enabled, ac lead-off is disabled. R/W 0 0 LOFFEN Enable lead-off detection. 0 (default) = lead-off disabled.

Table 30. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x0000001 [23:17] Reserved Reserved, set to 0. RESFREQ to select drive frequency. 0 (default) = periodic every N cycles (default). synchronize an external generator to the respiration carrier. It is a constant period only when RESPALTFREQ = 1. 0 (default) = normal GPIO3 function. 1 = MSB of RESPDAC driven onto GPIO3 pin. input directly to the ADC. See Figure 71. 0 (default) = RESPDAC_LL and RESPDAC_RA. 1 = RESPDAC_LA and RESPDAC_RA. R/W 0 12 RESPCAP Selects source of respiration capacitors. 0 (default) = use internal capacitors. 1 = use external capacitors. R/W 0000 [11:8] RESPGAIN [3:0]Respiration in amp gain (saturates at 10). RESPSEL. EXT_RESP_RA is automatically enabled. R/W 00 [6:5] RESPSEL [1:0] Set leads for respiration measurement. 11 = external respiration path. R/W 00 [4:3] RESPAMP Set the test tone amplitude for respiration drive signal. R/W 00 [2:1] RESPFREQ Set frequency for respiration. R/W 0 0 RESPEN Enable respiration.

Table 30. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x0000001 (Continued) 0 (default) = respiration disabled. 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 31. Pace Detection Control Register (PACECTL) Address 0x04, Reset Value = 0x000F881 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 32. Common-Mode, Reference, and Shield Drive Control Register (CMREFCTL) Address 0x05, Reset Value = 0xE00000 R/W 1 23 LACM Common-mode electrode select. driven from the internal VCM_REF (1.3 V) when Bits [23:19] = 0. 0 = does not contribute to the common mode. 1 = contributes to the common mode. 0 [18:15] Reserved Reserved, set to 0. R/W 0 12 RARLD 0 (default) = does not contribute to RLD input. R/W 0 11 V1RLD 1 = contributes to RLD input. R/W 0 8 CEREFEN Common electrode (CE) reference, see Figure 58. 0 (default) = common electrode disabled. 1 = common electrode enabled. R/W 0000 [7:4] RLDSEL [3:0]1 Select electrode for reference drive.

Table 32. Common-Mode, Reference, and Shield Drive Control Register (CMREFCTL) Address 0x05, Reset Value = 0xE00000 (Continued) pin. This bit has no effect if an external common mode is selected. 0 (default) = common mode is not driven out. 1 = common mode is driven out of the external common-mode pin. R/W 0 2 EXTCM Select the source of common mode (use when operating multiple devices together). 0 (default) = internal common mode selected. 1 = external common mode selected (all the internal common-mode switches are off). R/W 0 1 RLDEN1 Enable right leg drive reference electrode. R/W 0 0 SHLDEN1 Enable shield drive. 0 (default) = shield drive disabled. 1 ADAS1000 and ADAS1000-1 models only, ADAS1000-2 models does not contain these features. Table 33. GPIO Control Register (GPIOCTL) Address 0x06, Reset Value = 0x000000

Table 33. GPIO Control Register (GPIOCTL) Address 0x06, Reset Value = 0x000000 (Continued) Table 34. Pace Amplitude Threshold Register (PACEAMPTH) Address 0x07, Reset Value = 0x2424241 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 35. Test Tone Register (TESTTONE) Address 0x08, Reset Value = 0x000000

Table 35. Test Tone Register (TESTTONE) Address 0x08, Reset Value = 0x000000 (Continued) Table 36. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x0020001 0 [23:14] Reserved Reserved, set to 0. noise. Chopping is performed at 256 kHz. R/W 0 12 CALMODEEN Calibration mode enable. 0 (default) = disable calibration mode. 1 = enable calibration mode; connect CAL DAC_IO, begin data acquisition on ECG channels. R/W 0 11 CALINT Calibration internal or external. signal internally to all ECG channels. R/W 0 10 CALDACEN Enable 10-bit calibration DAC for calibration mode or external use. 0 (default) = disable calibration DAC. is enabled, ac lead-off is disabled. R/W 0000000000 [9:0] CALDATA[9:0] Set the calibration DAC value. 1 To ensure successful update of the calibration DAC, the serial interface must issue four additional SCLK cycles after writing the new calibration DAC register word. Table 37. Frame Control Register (FRMCTL) Address 0x0A, Reset Value = 0x079000 R/W 0 21 LEADIII/RADIS 0 (default) = included in frame. R/W 0 20 V1DIS 1 = exclude from frame. R/W 1111 [18:15] Reserved Reserved, set to 1111. R/W 0 14 PACEDIS1 Pace detection.

Table 37. Frame Control Register (FRMCTL) Address 0x0A, Reset Value = 0x079000 (Continued) 0 (default) = included in frame. R/W 0 13 RESPMDIS1 Respiration magnitude. 0 (default) = included in frame. R/W 1 12 RESPPHDIS1 Respiration phase. 1 (default) = exclude from frame. R/W 0 11 LOFFDIS Lead-off status. 0 (default) = included in frame. R/W 0 10 GPIODIS GPIO word disable. 0 (default) = included in frame. R/W 0 9 CRCDIS CRC word disable. 0 (default) = included in frame. R/W 0 8 RESERVED Reserved, set to 0. 0 (default) = fixed frame format. 1 = autodisable words (words per frame changes). 0 (default) = always send entire frame. 1 = repeat frame header until ready. R/W 0 5 Reserved Reserved, set to 0 . R/W 0 4 DATAFMT Sets the output data format, see Figure 58. 0 (default) = digital lead/vector format (available only in 2 kHz and 16 kHz data rates). R/W 00 [3:2] SKIP[1:0] Skip interval. This field provides a way to decimate the data. 00 (default) = output every frame. 01 = output every other frame. 1× = output every 4th frame. R/W 00 [1:0] FRMRATE[1:0] Sets the output data rate. 00 (default) = 2 kHz output data rate. 01 = 16 kHz output data rate. 10 = 128 kHz output data rate (DATAFMT must be set to 1). 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 38. Filter Control Register (FILTCTL) Address 0x0B, Reset Value = 0x000000

Table 38. Filter Control Register (FILTCTL) Address 0x0B, Reset Value = 0x000000 (Continued) Table 39. AC Lead-Off Upper Threshold Register (LOFFUTH) Address 0x0C, Reset Value = 0x00FFFF Table 40. AC Lead-Off Lower Threshold Register (LOFFLTH) Address 0x0D, Reset Value = 0x000000 Table 41. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x0000001 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.

Table 42. Pace Level Threshold Register (PACELVLTH) Address 0x0F, Reset Value = 0x0000001 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 43. Read Electrode/Lead Data Registers (Electrode/Lead) Address 0x11 to 0x15, Reset Value = 0x0000001 R 0 [23:0] ECG data Channel data value. Data left justified (MSB) irrespective of data rate.

1. In electrode mode and analog lead mode, the digital result value is an unsigned integer.

to electrode format because it can swing from +VREF to –VREF. Therefore, the LSB size is doubled. where N = number of data bits: 16 for 128 kHz data rate or 24 for 2 kHz/16 kHz data rate. 1 If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. Table 44. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x0000001, 2, 3 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. R 000 [22:20] Pace Channel 3 width This bit is log2 (width) − 1 of the pace pulse. R 0000 [19:16] Pace Channel 3 height This bit is the log2 (height) of the pace pulse. Height = 2N × 2 VREF/GAIN/216. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. R 000 [14:12] Pace Channel 2 width This bit is log2 (width) − 1 of the pace pulse.

Table 44. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x0000001, 2, 3 (Continued) R 0000 [11:8] Pace Channel 2 height This bit is the log2 (height) of the pace pulse. Height = 2N × 2 VREF/GAIN/216. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. R 000 [6:4] Pace Channel 1 width This bit is log2 (width) − 1 of the pace pulse. R 0000 [3:0] Pace Channel 1 height This bit is the log2 (height) of the pace pulse. Height = 2N × 2 VREF/GAIN/216. 1 If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. more accurate reading, read Register 0x3A, Register 0x3B, and Register 0x3C (see Table 53). 3 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 45. Read Respiration Data—Magnitude Register (RESPMAG) Address 0x1B, Reset Value = 0x0000001, 2 R 0 [23:0] Respiration magnitude[23:0] Magnitude of respiration signal. This is an unsigned value. 1 If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. 2 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 46. Read Respiration Data—Phase Register (RESPPH) Address 0x1C, Reset Value = 0x0000001, 2 from 0 to 2π. If signed, the range is from – π to +π. 1 This register is not part of framing data, but may be read by issuing a register read command of this address. 2 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 47. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000 R 0 23 RLD lead-off status Electrode connection status.

21 LL lead-off status

20 RA lead-off status

19 V1 lead-off status The common electrodes have only dc lead-off detection. These bits accumulate in the frame buffer and are cleared when the frame buffer is loaded into the SPI buffer.

Table 47. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000 (Continued) 1 = electrode is disconnected. RLD lead-off is not detected in ac lead-off. R 0 [17:14] Reserved Reserved. R 0 12 LAADCOR ADC out of range error for each ADC channel. 11 LLADCOR These status bits indicate the resulting ADC code is out of range. 10 RAADCOR These bits accumulate in the frame buffer and are cleared when the frame buffer is loaded into the SPI buffer.

9 V1ADCOR

R 0 [7:0] Reserved Reserved. Table 48. DC Lead-Off Register (DCLEAD-OFF) Address 0x1E, Reset Value = 0x0000001 indicate if the dc lead-off comparator threshold level has been exceeded. 22 LA input overrange 0 = electrode < overrange threshold, 2.4 V. 21 LL input overrange 1 = electrode > overrange threshold, 2.4 V.

20 RA input overrange

19 V1 input overrange

18 V2 input overrange

13 CE input overrange

the dc lead-off comparator threshold level has been exceeded. 11 LA input underrange0 = electrode > underrange threshold, 0.2 V. 10 LL input underrange1 = electrode < underrange threshold, 0.2 V.

9 RA input underrange

8 V1 input underrange

7 V2 input underrange

2 CE input underrange

1 This register is not part of framing data, but can be read by issuing a register read command of this address. Table 49. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x0000001 R 0 [23:4] Reserved Reserved. R 0 3 Internal error Internal digital failure. This is set if an error is detected in the digital core.

Table 49. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x0000001 (Continued) once this register is read or the PWREN bit (Address 0x01[1]) is cleared. R 0 0 PLL locked status This bit indicates the current state of the PLL locked status. areas of malfunction within a failing device. Table 50. Extended Switch for Respiration Inputs Register (EXTENDSW) Address 0x20, Reset Value = 0x000000

22 EXT_RESP_RA to ECG2_LLSW1b

21 EXT_RESP_RA to ECG3_RASW1c 0 = switch open. 20 EXT_RESP_RA to ECG4_V1SW1d 1 = switch closed.

19 EXT_RESP_RA to ECG5_V2SW1e

18 EXT_RESP_LL to ECG1_LASW2a

17 EXT_RESP_LL to ECG2_LLSW2b

16 EXT_RESP_LL to ECG3_RASW2c

15 EXT_RESP_LL to ECG4_V1SW2d

14 EXT_RESP_LL to ECG5_V2SW2e

13 EXT_RESP_LA to ECG1_LASW3a

12 EXT_RESP_LA to ECG2_LLSW3b

11 EXT_RESP_LA to ECG3_RASW3c

10 EXT_RESP_LA to ECG4_V1SW3d

9 EXT_RESP_LA to ECG5_V2SW3e

R/W 0 8 AUX_V1 V1 and V2 electrodes can be used for measurement purposes other than ECG. and V2 relative to the VCM_REF level. loop, therefore there is increased noise on the measurement as a result. R/W 0 [6:0] Reserved Reserved, set to 0. 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these EXT_RESP_xx pins. Table 51. User Gain Calibration Registers (CALxx) Address 0x21 to Address 0x25, Reset Value = 0x000000 [31:24] Address [7:0] 0x21: calibration LA. R/W 0 23 USRCAL User can choose between default calibration values or user calibration values for GAIN 0, GAIN 1, GAIN 2. Note that for GAIN 3, there is no factory calibration.

Table 51. User Gain Calibration Registers (CALxx) Address 0x21 to Address 0x25, Reset Value = 0x000000 (Continued) 0 = default calibration values (factory calibration). 1 = user calibration values. R/W 0 [11:0] CALVALUE Gain calibration value. returns the default value for the current gain setting. Table 52. Read AC Lead-Off Amplitude Registers (LOAMxx) Address 0x31 to Address 0x35, Reset Value = 0x0000001 [31:24] Address [7:0] These registers report the measured ac lead-off amplitude for each ECG channel. 0x31: LA or Lead I ac lead-off amplitude. 0x32: LL or Lead II ac lead-off amplitude. 0x33: RA or Lead III ac lead-off amplitude. 0x34: V1 ac lead-off amplitude. 0x35: V2 ac lead-off amplitude. R/W 0 [23:16] Reserved Reserved. R 0 [15:0] LOFFAM Measured amplitude. (average of rectified sine wave). To convert to RMS, scale the output by π/(2√2). 1 This register is not part of framing data, but can be read by issuing a register read command of this address. Table 53. Pace Width and Amplitude Registers (PACExDATA) Address 0x3A to Address 0x3C, Reset Value = 0x0000001, 2

Table 53. Pace Width and Amplitude Registers (PACExDATA) Address 0x3A to Address 0x3C, Reset Value = 0x0000001, 2 (Continued) that is, pulses narrower than 101.56 μs. 1 These registers are not part of framing data but can be read by issuing a register read command of these addresses. 2 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 54. Frame Header (FRAMES) Address 0x40, Reset Value = 0x8000001 R 1 31 Marker Header marker, set to 1 for the header. R 0 30 Ready bit Ready bit indicates if ECG frame data is calculated and ready for reading. 0 = ready, data frame follows. nonzero value indicates an overflow. 11 = 3 or more frames missed. R 0 27 Fault Internal device error detected. R 0 26 Pace 3 detected Pace 3 indicates pacing artifact was qualified at most recent point. 1 = pacing artifact present. R 0 25 Pace 2 detected Pace 2 indicates pacing artifact was qualified at most recent point. 1 = pacing artifact present. R 0 24 Pace 1 detected Pace 1 indicates pacing artifact was qualified at most recent point. 1 = pacing artifact present. R 0 23 Respiration 0 = no new respiration data. 1 = respiration data updated. lead-off is enabled, this bit reflects the OR of all dc and ac lead-off flags. 1 = one or more lead-off detected. R 0 21 DC lead-off detected 0 = all leads connected. 1 = one or more lead-off detected. R 0 20 ADC out of range 0 = ADC within range. 1 If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.

Table 55. Frame CRC Register (CRC) Address 0x41, Reset Value = 0xFFFFFF1 1 The CRC register is a 32-bit word for 2 kHz and 16 kHz data rate and a 16-bit word for 128 kHz rate. See Table 24 for more details. and to start framing ECG data.

1. Write 1 configures the CMREFCTL register for CM = WCT

electrode. The shield amplifier is enabled.

1. Write 2 configures the FRMCTL register to output nine words
2. Write 3 addresses the ECGCTL register, enabling all channels

also put into conversion mode in this write.

1. Write 4 issues the read command to start putting the converted
2. Continue to issue SCLK cycles to read the converted data at
3. Write 1 configures the RESPCTL register with a 56 kHz respira-

capacitors and measuring on Lead I.

1. Write 2 issues the read command to start putting the converted
2. Continue to issue SCLK cycles to read the converted data at

the configured packet data rate.

1. Note that this example assumes that the FRMCTL register has

1. Write 1 configures the LOFFCTL register with a dc lead-off

enabled for a lead-off current of 50 nA.

1. Write 2 issues the read command to start putting the converted
2. Continue to issue SCLK cycles to read the converted data at

the configured packet data rate.

1. Note that this example assumes that the FRMCTL register

Table 56. Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data Table 57. Example 2: Enable Respiration and Stream Conversion Data Table 58. Example 3: Enable DC Lead-Off and Stream Conversion Data

1. Write 1 configures the CMREFCTL register to VCM_REF =

RLD_OUT, and the shield amplifier enabled.

1. Write 2 addresses the TESTTONE register to enable the 150

Hz sine wave onto all electrode channels.

1. Write 3 addresses the FILTCTL register to change the internal
2. Write 4 configures the FRMCTL register to output nine words

tone signal correctly on each electrode channel.

1. Write 5 addresses the ECGCTL register, enabling all channels

ADAS1000 is also put into conversion mode in this write.

1. Write 6 issues the read command to start putting the converted
2. Continue to issue SCLK cycles to read the converted data at

the configured packet data rate.

1. Write 1 configures the PACECTL register with all three pace
2. Write 2 issues the read command to start putting the converted
3. Continue to issue SCLK cycles to read the converted data at

height of the measured pulse from each measured lead.

1. Note that the PACEAMPTH register default setting is 0x242424,
2. Note that this example assumes that the FRMCTL register

Table 59. Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Table 60. Example 5: Enable Pace Detection and Stream Conversion Data

1. Write 1 configures the FRMCTL register to output seven words
2. Write 2 configures the CMREFCTL register to receive an exter-

nal common mode from the primary device.

1. Write 3 addresses the ECGCTL register, which powers up the
2. Write 4 is a read of the contents of the OPSTAT register to

miss the sync pulse from the primary device.

1. Write 5 configures the FRMCTL register to output nine words

frame is configured to always send irrespective of ready status. controller would then be required to make the lead calculations.

1. Write 6 configures the CMREFCTL register for CM = WCT =

(LA + LL + RA)/3; RLD is enabled onto RLD_OUT electrode.

1. Write 7 addresses the ECGCTL register, powering up the de-

vice, enabling all channels into a gain of 1.4, low noise mode.

1. Write 8 is a read of the contents of the OPSTAT register to

miss the sync pulse from the primary device.

1. If the OPSTAT register confirms the PLL is locked, then Write 9
2. Write 10 issues the read command to start putting the convert-

ed and decimated data out on the SDO pin.

1. Continue to issue SCLK cycles to read the converted data at

the configured packet data rate. Table 61. Example 6: Writing to Primary and Secondary Devices and Streaming Conversion Data

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CONTROL REGISTERS DETAILS analog.com Rev. D | 78 of 79 POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADAS1000/ADAS1000-1/ADAS1000-2 must have ample sup- ply decoupling of 0.1 μF on each supply pin located as close to the device pin as possible, ideally right up against the device. In addition, there must be one 4.7 μF capacitor for each of the power domains, AVDD and IOVDD, again located as close to the device as possible. IOVDD is best split from AVDD due to its noisy nature. Similarly, the ADCVDD and DVDD power domains each require one 2.2 μF capacitor with ESR in the range of 0.5 Ω to 2 Ω. The ideal location for each 2.2 μF capacitor is dependent on package type. For the LQFP package and DVDD decoupling, the 2.2 μF capacitor is best placed between Pin 30 and Pin 31, while for ADCVDD, place the 2.2 μF capacitor between Pin 55 and Pin 56. Similarly, for the LFCSP package, the DVDD 2.2 μF capacitor is ideal between Pin 43 and Pin 44, and between Pin 22 and Pin 23 for ADCVDD. A 0.1 μF capacitor is recommended for high frequency decoupling at each pin. The 0.1 μF capacitors must have low effective series resistance (ESR) and effective series inductance (ESL), such as the common ceramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Avoid digital lines running under the device because these couple noise onto the device. Allow the analog ground plane to run under the device to avoid noise coupling. The power supply lines must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching digital signals with digital ground to avoid radiating noise to other parts of the board and never run them near the reference inputs. It is essential to minimize noise on VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each other. This reduces the effects of feedthrough throughout the board. As is the case for all thin packages, take care to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. During layout of board, ensure that bypass capacitors are placed as close to the relevant pin as possible, with short, wide traces ideally on the topside. AVDD While the ADAS1000/ADAS1000-1/ADAS1000-2 are designed to operate from a wide supply rail, 3.15 V to 5.5 V, the performance is similar over the full range, but overall power increases with increasing voltage. ADCVDD AND DVDD SUPPLIES The AVDD supply rail powers the analog blocks in addition to the internal 1.8 V regulators for the ADC and the digital core. If using the internal regulators, connect the VREG_EN pin to AVDD and then use the ADCVDD and DVDD pins for decoupling purposes. The DVDD regulator can be used to drive other external digital circuitry as required; however, the ADCVDD pin is purely provided for bypassing purposes and does not have available current for other components. Where overall power consumption must be minimized, using exter- nal 1.8 V supply rails for both ADCVDD and DVDD would provide a more efficient solution. The ADCVDD and DVDD inputs have been designed to be driven externally and the internal regulators can be disabled by tying VREG_EN pin directly to ground. UNUSED PINS/PATHS In applications where not all ECG paths or functions might be used, the preferred method of biasing the different functions is as follows: ►Unused ECG paths power up disabled. For low power operation, keep them disabled throughout operation. Ideally, connect these pins to RLD_OUT if not being used. ►Unused external respiration inputs can be tied to ground if not in use. ►If unused, the shield driver can be disabled and output left to float. ►CM_OUT, CAL_DAC_IO, DRDY, GPIOx, CLK_IO, SYNC_GANG can be left open. LAYOUT RECOMMENDATIONS To maximize CMRR performance, pay careful attention to the ECG path layout for each channel. All channels must be identical to minimize difference in capacitance across the paths. Place all decoupling as close to the ADAS1000/ADAS1000-1/ ADAS1000-2 devices as possible, with an emphasis on ensuring that the VREF decoupling be prioritized, with VREF decoupling on the same side as the ADAS1000/ADAS1000-1/ADAS1000-2 devices, where possible.

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 OUTLINE DIMENSIONS ©2012-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. D | 79 of 79 Package Drawing (Option) Package Type Package Description CP-56-7 LFCSP 56-Lead Lead Frame Chip Scale Package ST-64-2 LQFP 64-Lead Low Profile Quad Flat Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: January 29, 2024 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADAS1000-1BCPZ -40°C to +85°C 56-Lead LFCSP (9mm x 9mm x 0.85mm w/ EP) CP-56-7 ADAS1000-1BCPZ-RL -40°C to +85°C 56-Lead LFCSP (9mm x 9mm x 0.85mm w/ EP)Reel, 2500 CP-56-7 ADAS1000-2BCPZ -40°C to +85°C 56-Lead LFCSP (9mm x 9mm x 0.85mm w/ EP) CP-56-7 ADAS1000-2BCPZ-RL -40°C to +85°C 56-Lead LFCSP (9mm x 9mm x 0.85mm w/ EP)Reel, 2500 CP-56-7 ADAS1000-2BSTZ -40°C to +85°C 64-Lead LQFP (10mm x 10mm) ST-64-2 ADAS1000-2BSTZ-RL -40°C to +85°C 64-Lead LQFP (10mm x 10mm) Reel, 1500 ST-64-2 ADAS1000BCPZ -40°C to +85°C 56-Lead LFCSP (9mm x 9mm x 0.85mm w/ EP) CP-56-7 ADAS1000BCPZ-RL -40°C to +85°C 56-Lead LFCSP (9mm x 9mm x 0.85mm w/ EP)Reel, 2500 CP-56-7 ADAS1000BSTZ -40°C to +85°C 64-Lead LQFP (10mm x 10mm) ST-64-2 ADAS1000BSTZ-RL -40°C to +85°C 64-Lead LQFP (10mm x 10mm) Reel, 1500 ST-64-2 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description Package Description EVAL‑ ADAS1000SDZ ADAS1000 Evaluation Board Evaluation Kit2 EVAL-SDP-CB1Z System Demonstration Board (SDP), used as a controller board for data transfer via USB interface to PC Controller Board3 1 Z = RoHS Compliant Part. 2 This evaluation kit consists of ADAS1000BSTZ × 2 for up to 12-lead configuration. Because the ADAS1000 contains all features, it is the evaluation vehicle for all ADAS1000 variants. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.