ADAS1000-4BCPZ-RL

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Low Power, Three Electrode Electrocardiogram (ECG) Analog Front End Data Sheet ADAS1000-3/ADAS1000-4

FEATURES

Biopotential signals in; digitized signals out 3 acquisition (ECG) channels and one driven lead Can be ganged for 8 electrode + RLD using master ADAS1000 or ADAS1000-1 AC and DC lead-off detection Internal pace detection algorithm on 3 leads Support for user’s own pace Thoracic impedance measurement (internal/external path) Selectable reference lead Scalable noise vs. power control, power-down modes Low power operation from 11 mW (1 lead), 15 mW (3 leads) Lead or electrode data available Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38 R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005, IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0 b:2005, IEC60601-2-51 ed. 1.0 b: 2005 Fast overload recovery Low or high speed data output rates Serial interface SPI-/QSPI™-/DSP-compatible 56-lead LFCSP package (9 mm × 9 mm) 64-lead LQFP package (10 mm × 10 mm body size)

APPLICATIONS

ECG: monitor and diagnostic Bedside patient monitoring, portable telemetry, Holter, AED, cardiac defibrillators, ambulatory monitors, pace maker programmer, patient transport, stress testing GENERAL DESCRIPTION The ADAS1000-3/ADAS1000-4 measure electro cardiac (ECG) signals, thoracic impedance, pacing artifacts, and lead-on/off status and output this information in the form of a data frame supplying either lead/vector or electrode data at programmable data rates. Its low power and small size make it suitable for portable, battery-powered applications. The high performance also makes it suitable for higher end diagnostic machines. The ADAS1000-4 is a full-featured, 3-channel ECG including respiration and pace detection, while the ADAS1000-3 offers only ECG channels with no respiration or pace features. The ADAS1000-3/ADAS1000-4 are designed to simplify the task of acquiring and ensuring quality ECG signals. They provide a low power, small data acquisition system for biopotential applications. Auxiliary features that aid in better quality ECG signal acquisition include: multichannel averaged driven lead, selectable reference drive, fast overload recovery, flexible respiration circuitry returning magnitude and phase information, internal pace detection algorithm operating on three leads, and the option of ac or dc lead-off detection. Several digital output options ensure flexibility when monitor- ing and analyzing signals. Value-added cardiac post processing is executed externally on a DSP , microprocessor, or FPGA. Because ECG systems span different applications, the ADAS1000-3/ADAS1000-4 feature a power/noise scaling architecture where the noise can be reduced at the expense of increasing power consumption. Signal acquisition channels may be shut down to save power. Data rates can be reduced to save power. To ease manufacturing tests and development as well as offer holistic power-up testing, the ADAS1000-3 /ADAS1000-4 offer a suite of features, such as dc and ac test excitation via the calibration DAC and CRC redundancy testing in addition to readback of all relevant register address space. The input structure is a differential amplifier input thereby allowing users a variety of configuration options to best suit their application. The ADAS1000-3/ADAS1000-4 are available in two package options: either a 56-lead LFCSP or a 64-lead LQFP package; they are specified over −40°C to +85°C temperature range. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

ADAS1000-3/ADAS1000-4 Data Sheet TABLE OF CONTENTS Electrode/Lead Formation and Input Stage Configuration .. 29 Pacing Artifact Detection Function (ADAS1000-4 Only).... 41 Rev. B | Page 2 of 80

Data Sheet ADAS1000-3/ADAS1000-4

REVISION HISTORY

1/15—Rev. A to Rev. B Changed Frequency Range from 2.031 kHz (Typ) to 2.039 kHz Changes to Digital Lead Mode and Calculation Section and Electrode Mode: Common Electrode A and Common Electrode B Configuration Section; Added Figure 55; Added Figure 66 and Changes to Respiration (ADAS1000-4 Changes to Respiration Carrier Frequency Section; Added Changes to Pacing Artifact Detection Function (ADAS1000-4 Changes to Pace Edge Threshold, Pace Level Threshold, Pace Amplitude Threshold, Pace Validation Filters, and Pace Width Changes to Evaluating Pace Detection Performance Section and Changes to Data Ready ( E E Changes to Secondary Serial Interface Section and Table 25 .... 55 Changes to Example 1: Initialize the Device for ECG Capture 1/13—Rev. 0 to Rev. A Changes to Respiration (ADAS1000-4 Model Only) Section 11/12—Revision 0: Initial Version Rev. B | Page 3 of 80

Figure 1. ADAS1000-4 3-Channel Full Featured Model Table 1. Overview of Features Available from ADAS1000 Generics 1 Master interface is provided for users wishing to utilize their own digital pace algorithm; see the Secondary Serial Interface section.

Data Sheet ADAS1000-3/ADAS1000-4 SPECIFICATIONS AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. For specified performance, internal ADCVDD and DVDD linear regulators have been used. They may be supplied from external regulators. ADCVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ECG CHANNEL These specifications apply to the following pins: ECG1_LA, ECG2_LL, ECG3_RA, CM_IN (CE mode), EXT_RESP_xx pins when used in extend switch mode Electrode Input Range Independent of supply 0.3 1.3 2.3 V GAIN 0 (gain setting ×1.4) 0.63 1.3 1.97 V GAIN 1 (gain setting ×2.1) 0.8 1.3 1.8 V GAIN 2 (gain setting ×2.8) 0.97 1.3 1.63 V GAIN 3 (gain setting ×4.2) Input Bias Current −40 ±1 +40 nA Relates to each electrode input; over operating range; dc and ac lead-off are disabled −200 +200 nA AGND to AVDD Input Offset −7 mV Electrode/vector mode with VCM = VCM_REF GAIN 3 −7 mV GAIN 2 −15 mV GAIN 1 −22 mV GAIN 0 Input Offset Tempco1 ±2 μV/°C Input Amplifier Input Impedance2 1||10 GΩ||pF At 10 Hz CMRR2 105 110 dB 51 kΩ imbalance, 60 Hz with ±300 mV differential dc offset; per AAMI/IEC standards; with driven leg loop closed Crosstalk1 80 dB Between channels Resolution2 19 Bits Electrode/vector mode, 2 kHz data rate, 24-bit data-word

18 Bits Electrode/vector mode, 16 kHz data rate, 24-bit data-

16 Bits Electrode/analog lead mode, 128 kHz data rate, 16-bit

Integral Nonlinearity Error 30 ppm GAIN 0; all data rates Differential Nonlinearity Error 5 ppm GAIN 0 Gain2 Referred to input; (2 × VREF)/gain/(2N − 1); Applies after factory calibration. User calibration adjusts this number. GAIN 0 (×1.4) 4.9 µV/LSB At 19-bit level in 2 kHz data rate 9.81 μV/LSB At 18-bit level in 16 kHz data rate 39.24 μV/LSB At 16-bit level in 128 kHz data rate GAIN 1 (×2.1) 3.27 μV/LSB At 19-bit level in 2 kHz data rate 6.54 μV/LSB At 18-bit level in 16 kHz data rate 26.15 μV/LSB At 16-bit level in 128 kHz data rate GAIN 2 (×2.8) 2.45 μV/LSB At 19-bit level in 2 kHz data rate 4.9 μV/LSB At 18-bit level in 16 kHz data rate 19.62 μV/LSB At 16-bit level in 128 kHz data rate GAIN 3 (×4.2) 1.63 μV/LSB No factory calibration for this gain setting At 19-bit level in 2 kHz data rate 3.27 μV/LSB At 18-bit level in 16 kHz data rate 13.08 μV/LSB At 16-bit level in 128 kHz data rate Rev. B | Page 5 of 80

ADAS1000-3/ADAS1000-4 Data Sheet Rev. B | Page 6 of 80 Parameter Min Typ Max Unit Test Conditions/Comments Gain Error −1 +0.01 +1 % GAIN 0 to GAIN 2, factory calibrated; programmable user or factory calibration option enables; factory gain calibration applies only to standard ECG interface −2 +0.1 +2 % GAIN 3 setting, no factory calibration for this gain Gain Matching −0.1 +0.02 +0.1 % GAIN 0 to GAIN 2 Gain Tempco1 25 ppm/°C Input Referred Noise1 GAIN 2, 2 kHz data rate, see Table 4 Analog Lead Mode 6 μV p-p 0.5 Hz to 40 Hz; high performance mode 10 μV p-p 0.05 Hz to 150 Hz; high performance mode 12 μV p-p 0.05 Hz to 150 Hz; low power mode Electrode Mode 11 μV p-p 0.05 Hz to 150 Hz; high performance mode 12 μV p-p 0.05 Hz to 150 Hz; low power mode Digital Lead Mode 14 μV p-p 0.05 Hz to 150 Hz; high performance mode 16 μV p-p 0.05 Hz to 150 Hz; low power mode Power Supply Sensitivity2 100 dB At 120 Hz Analog Channel Bandwidth1 65 kHz Dynamic Range1 104 dB GAIN 0, 2 kHz data rate, −0.5 dBFS input signal, 10 Hz Signal-to-Noise Ratio1 100 dB −0.5 dB FS input signal COMMON-MODE INPUT CM_IN pin Input Voltage Range 0.3 2.3 V Input Impedance2 1||10 GΩ||pF Input Bias Current −40 ±1 +40 nA Over oper ating range; dc and ac lead-off disabled −200 +200 nA AGND to AVDD COMMON-MODE OUTPUT CM_OUT pin VCM_REF 1.28 1.3 1.32 V Internal voltage; independent of supply Output Voltage, VCM 0.3 1.3 2.3 V No dc load Output Impedance1 0.75 kΩ Not intended to drive current Short-Circuit Current1 4 mA Electrode Summation Weighting Error2 1 % Resistor matching error RESPIRATION FUNCTION (ADAS1000-4 ONLY) These specifications apply to the following pins: EXT_RESP_LA, EXT_RESP_LL, EXT_RESP_RA and selected internal respiration paths (Lead I, Lead II, Lead III) Input Voltage Range 0.3 2.3 V AC-coupled, independent of supply Input Voltage Range (Linear Operation) 1.8/gain V p-p Programmable gain (10 states) Input Bias Current −10 ±1 +10 nA Applies to EXT_RESP_xx pins over AGND to AVDD Input Referred Noise1 0.85 μV rms Frequency2 46.5 to 64 kHz Programmab le frequency, see Table 30 Excitation Current Respiration drive current corresponding to differential voltage programmed by the RESPAMP bits in the RESPCTL register; internal respiration mode, cable 5 kΩ/200 pF, 1.2 kΩ chest impedance 64 μA p-p Drive Range A 32 μA p-p Drive Range B2 16 μA p-p Drive Range C2 8 μA p-p Drive Range D2 Resolution2 24 Bits Update rate 125 Hz Measurement Resolution1 0.2 Ω Cable <5 kΩ/200 pF per electrode, body resistance modeled as 1.2 kΩ 0.02 Ω No cable impedance, body resistance modeled as 1.2 kΩ In-Amp Gain1 1 to 10 Digitally programmable in steps of 1 Gain Error 1 % LSB weight for GAIN 0 setting Gain Tempco1 25 ppm/C

Data Sheet ADAS1000-3/ADAS1000-4 Parameter Min Typ Max Unit Test Conditions/Comments RIGHT LEG DRIVE/DRIVEN LEAD Output Voltage Range 0.2 AVDD − 0.2 V RLD_OUT Short-Circuit Current −5 ±2 +5 mA External protection resistor required to meet regulatory patient current limits; output shorted to AVDD/AGND Closed-Loop Gain Range2 25 V/V Slew Rate2 200 mV/ms Input Referred Noise1 8 μV p-p 0.05 Hz to 150 Hz Amplifier GBP2 1.5 MHz DC LEAD-OFF Internal current source, pulls up open ECG pins; programmable in 10 nA steps: 10 nA to 70 nA Lead-Off Current Accuracy ±10 % Of programmed value High Threshold Level1 2.4 V Inputs are compared to threshold levels; if inputs exceed levels, lead-off flag is raised Low Threshold Level1 0.2 V Threshold Accuracy 25 mV AC LEAD-OFF Programmable in 4 steps: 12.5 nA rms, 25 nA rms, 50 nA rms, 100 nA rms Frequency Range 2.039 kHz Fixed frequency Lead-Off Current Accuracy ±10 % Of programmed value, measured into low impedance REFIN Input Range2 1.76 1.8 1.84 V Channel gain scales directly with REFIN Input Current 113 μA Per active ADC 450 675 950 μA Three ECG channels and respiration enabled REFOUT On-chip reference voltage for ADC; not intended to drive other components reference inputs directly, must be buffered externally Output Voltage, VREF 1.785 1.8 1.815 V Reference Tempco1 ±10 ppm/°C Output Impedance2 0.1 Ω Short-Circuit Current1 4.5 mA Short circuit to ground Voltage Noise1 33 μV p-p 0.05 Hz to 150 Hz (ECG band) 17 μV p-p 0.05 Hz to 5 Hz (respiration) CALIBRATION DAC Available on CAL_DAC_IO (output for master, input for slave) DAC Resolution 10 Bits Full-Scale Output Voltage 2.64 2.7 2.76 V No load, nominal FS output is 1.5 × REFOUT Zero-Scale Output Voltage 0.24 0.3 0.36 V No load DNL −1 +1 LSB Output Series Resistance2 10 kΩ Not intended to drive low impedance load, used for slave CAL_DAC_IO configured as an input Input Current ±5 nA When used as an input CALIBRATION DAC TEST TONE Output Voltage 0.9 1 1.1 mV p-p Rides on common-mode voltage, VCM_REF = 1.3 V Square Wave 1 Hz Low Frequency Sine Wave 10 Hz High Frequency Sine Wave 150 Hz SHIELD DRIVER Output Voltage Range 0.3 2.3 V Rides on common-mode voltage (VCM) Gain 1 V/V Offset Voltage −20 +20 mV Short-Circuit Current 15 25 μA Output current limited by internal series resistance Stable Capacitive Load2 10 nF CRYSTAL OSCILLATOR Applied to XTAL1 and XTAL2 Frequency2 8.192 MHz Start-Up Time2 15 ms Internal startup Rev. B | Page 7 of 80

ADAS1000-3/ADAS1000-4 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments CLOCK_IO External clock source supplied to CLK_IO; this pin is configured as an input when the device is programmed as a slave Operating Frequency2 8.192 MHz Input Duty Cycle2 20 80 % Output Duty Cycle2 50 % DIGITAL INPUTS Applies to all digital inputs Input Low Voltage, VIL 0.3 × IOVDD V Input High Voltage, VIH 0.7 × IOVDD V Input Current, IIH, IIL −1 +1 μA −20 +20 μA E E A A has an internal pull-up resistor RESET Pin Capacitance2 3 pF DIGITAL OUTPUTS Output Low Voltage, VOL 0.4 V ISINK = 1 mA Output High Voltage, VOH IOVDD − 0.4 V ISOURCE = −1 mA Output Rise/Fall Time 4 ns Capacitive load = 15 pF, 20% to 80% DVDD REGULATOR Internal 1.8 V regulator for DVDD Output Voltage 1.75 1.8 1.85 V Available Current1 1 mA Droop < 10 mV; for external device loading purposes Short-Circuit Current Limit 40 mA ADCVDD REGULATOR Internal 1.8 V regulator for ADCVDD; not recommended as a supply for other circuitry Output Voltage 1.75 1.8 1.85 V Short-Circuit Current Limit 40 mA POWER SUPPLY RANGES2 AVDD 3.15 3.3 5.5 V IOVDD 1.65 3.6 V ADCVDD 1.71 1.8 1.89 V If applied by external 1.8 V regulator DVDD 1.71 1.8 1.89 V If applied by external 1.8 V regulator POWER SUPPLY CURRENTS AVDD Standby Current 785 975 μA IOVDD Standby Current 1 60 μA EXTERNALLY SUPPLIED ADCVDD AND DVDD All three channels enabled, RLD enabled, pace enabled AVDD Current 2.4 4.1 mA High performance mode 2.2 4.1 mA Low performance mode 3.2 mA High performance mode, respiration enabled ADCVDD Current 4.5 6.5 mA High performance mode 3.3 5.5 mA Low performance mode 5.4 mA High performance mode, respiration enabled DVDD Current 2.0 4 mA High performance mode 1.1 3 mA Low performance mode 2.0 mA High performance mode, respiration enabled INTERNALLY SUPPLIED ADCVDD AND DVDD All three channels enabled, RLD enabled, pace enabled AVDD Current 9 12.6 mA High performance mode 6.6 9.6 mA Low performance mode 11 14.6 mA High performance mode, respiration enabled POWER DISSIPATION All 3 channels enabled, RLD enabled, pace enabled Externally Supplied ADCVDD and DVDD3 Three Input Channels and RLD 19.6 mW High performance (low noise) 15.2 mW Low power mode Internally Supplied ADCVDD and DVDD All three channels enabled, RLD enabled, pace enabled Three Input Channels and RLD 29.7 mW High performance (low noise) 21.8 mW Low power mode Rev. B | Page 8 of 80

Data Sheet ADAS1000-3/ADAS1000-4 Parameter Min Typ Max Unit Test Conditions/Comments OTHER FUNCTIONS4 Power Dissipation Respiration 7.6 mW Shield Driver 150 μW EXTERNALLY SUPPLIED ADCVDD AND DVDD Two electrodes enabled for one lead measurement, RLD enabled, pace enabled AVDD Current 1.9 3.7 mA High performance mode 1.7 3.7 mA Low performance mode ADCVDD Current 3.6 5.5 mA High performance mode 2.5 4.5 mA Low performance mode DVDD Current 1.7 4 mA High performance mode 0.9 3 mA Low performance mode INTERNALLY SUPPLIED ADCVDD AND DVDD Two electrodes enabled for one lead measurement, RLD enabled, pace enabled AVDD Current 7.3 10.7 mA High performance mode 5.3 8.2 mA Low performance mode POWER DISSIPATION Two electrodes enabled for one lead measurement, RLD enabled, pace enabled Externally Supplied ADCVDD and DVDD3 Two Input Channels and RLD 15.8 mW High performance (low noise) 11.7 mW Low power mode Internally Supplied ADCVDD and DVDD Two Input Channels and RLD 24 mW High performance (low noise) 17.5 mW Low power mode 1 Guaranteed by characterization, not production tested. 2 Guaranteed by design, not production tested. 3 ADCVDD and DVDD can be powered from an internal LDO or, alternatively, can be powered from an external 1.8 V rail, which may result in a lower power solution. 4 Pace is a digital function and incurs no power penalty. Rev. B | Page 9 of 80

Table 3. Typical Input Referred Noise over a 0.5 sec Window (μV p-p)1 1 Typical values measured at 25°C, not subject to production test. either 40 Hz or 150 Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands. 3 Analog lead mode as shown in Figure 56. Table 4. Typical Input Referred Noise (μV p-p)1 1 Typical values measured at 25°C, not subject to production test. either 40 Hz or 150 Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands. 3 Analog lead mode as shown in Figure 56. 5 Digital lead mode as shown in Figure 57. 6 Digital lead mode is available in 2 kHz and 16 kHz data rates.

8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. 16 kHz, 128 kHz; use skip mode for slower rates. SCLK Cycle Time 25 40 50 ns min See Table 21 for detai ls on SCLK frequency vs. packet data/frame rates. A valid setup time to rising SCLK. A valid hold time to rising SCLK. tCH 8 8 8 ns min SCLK high time. tCL 8 8 8 ns min SCLK low time. tDO 8.5 11.5 20 ns typ SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF. tDS 2 2 2 ns min SDI valid setup time from SCLK rising edge. tDH 2 2 2 ns min SDI valid hold time from SCLK rising edge. A valid setup time from SCLK rising edge. A valid hold time from SCLK rising edge. 1 Guaranteed by characterization, not production tested. 2 Guaranteed by design, not production tested. Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)

soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance1

1 Based on JEDEC standard 4-layer (2S2P) high effective thermal conductivity

test board (JESD51-7) and natural convection.

Figure 7. ADAS1000-3, 64-Lead LQFP Pin Configuration Figure 8. ADAS1000-3, 56-Lead LFCSP Pin Configuration Figure 9. ADAS1000-4, 64-Lead LQFP Pin Configuration Figure 10. ADAS1000-4, 56-Lead LFCSP Pin Configuration

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT

PINS BECAUSE NOISE COUPLING MAY RESULT.

42 DGND

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER
2. THE EXPOSED PAD IS ON THE TOP OF THE PACKAGE;

IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.

29 DGND

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO
2. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO
3. THE EXPOSED PAD IS ON THE TOP OF THE PACKAGE;

IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.

Table 9. Pin Function Descriptions ADAS1000-3 Pin No. ADAS1000-4 Pin No. Grounding, and Decoupling Strategy section. bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section. bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section. Decoupling Strategy section. 10 6 10 6 ECG1_LA Analog Input, Left Arm (LA). 11 5 11 5 ECG2_L L Analog Input, Left Leg (LL). 12 4 12 4 ECG3_RA Analog Input, Right Arm (RA). 4 12 EXT_RESP_RA Optional External Respiration Input. 5 11 EXT_RESP_LL Optional External Respiration Input. 6 10 EXT_RESP_LA Optional External Respiration Input. Shared Pin (User-Configured). Output of Shield Driver (SHIELD). Negative Side 1 (RESPDAC_LA). 60 18 SHIELD Output of Shield Driver. 19 55 19 55 CM_IN Common-Mode Input. 21 53 21 53 RLD_SJ Summing Junction for Right Leg Drive Amplifier. 20 54 20 54 RLD_OUT Output and Feedback Junction for Right Leg Drive Amplifier. 8 8 8 8 REFOUT Reference Output. 7 9 7 9 REFGND Reference Ground. Connect to a clean ground. applied to CLK_IO. Each XTAL pin requires a 15 pF capacitor to ground. the entire suite of data in framing mode.

Data Sheet ADAS1000-3/ADAS1000-4 Rev. B | Page 17 of 80 ADAS1000-3 Pin No. ADAS1000-4 Pin No. Mnemonic Description LQFP LFCSP LQFP LFCSP 44 32 44 32 SCLK Clock Input. Data is clocked into the shift register on a rising edge and clocked out on a falling edge. 43 33 43 33 SDI Serial Data Input. 53 25 53 25 A PD E Power-Down, Active Low. 45 31 45 31 SDO Serial Data Output. This pin is used for reading back register configuration data and for the data frames. 42 34 42 34 A DRDY E Digital Output. This pin indicates that conversion data is ready to be read back when low, busy when high. When reading packet data, the entire packet must be read to allow A DRDY E A to return high. 54 24 54 24 A RESET E Digital Input. This pin has an internal pull-up resistor. This pin resets all internal nodes to their power-on reset values. 52 26 52 26 SYNC_GANG Digital Input/Output (Output on Master, Input on Slave). Used for synchronization control where multiple devices are connected together. Powers up in high impedance. 36 40 36 40 GPIO0/A MCS E General-Purpose I/O or Master 128 kHz SPI A CS E A . 37 39 37 39 GPIO1/MSCL K General-Purpose I/O or Master 128 kHz SPI SCLK. 38 38 38 38 GPIO2/MSDO General-Pu rpose I/O or Master 128 kHz SPI SDO. 39 37 39 37 GPIO3 General-Purpose I/O. 1, 3, 4, 5, 6, 13, 14, 16, 17, 32, 33, 48, 49, 62, 64 2, 3, 10, 11, 12, 13, 16 1, 13, 14, 16, 17, 32, 33, 48, 49, 2, 3 NC No connect. Do not connect to these pi ns (see Figure 7, Figure 8, Figure 9, and Figure 10). 57 57 EPAD Exposed Pad. The exposed pad is on th e top of the package; it is connected to the most negative potential, AGND.

Figure 11. Input Referred Noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Figure 12. Input Referred Noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Figure 13. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data Figure 14. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data Figure 15. ECG Channel Noise Performance over a 0.5 Hz to 40 Hz or 0.5 Hz to Figure 16. Typical Gain Error Across Channels

10 SECONDS OF DATA

Figure 29. VCM_REF vs. Temperature Figure 30. Typical AVDD Supply Current vs. Temperature, Using Internal Figure 31. Typical AVDD Supply Current vs. Temperature, Using Externally Figure 32. Typical AVDD Supply Current vs. Temperature in Standby Mode Figure 33. Typical AVDD Supply Current vs. AVDD Supply Voltage Figure 34. Respiration with 200 mΩ Impedance Variation, Using Internal

3 ECG CHANNELS ENABLED

scaling to ensure suitability to these varying requirements. addition to readback of all relevant register address space. Figure 52. ADAS1000-3 Simplified Block Diagram

Figure 53. ADAS1000-4 Simplified Block Diagram

available for this data rate. deriving leads from other lead measurements. Table 10. Lead Composition 1 These augmented leads are not calculated within the ADAS1000-3/ADAS1000-4, but can be derived in the host DSP/microcontroller/FPGA.

removed from the final lead data. each channel’s available signal range. ~250 kHz is well above the bandwidth of any signals of interest.

2 MHz SAR converter; 1024 × oversampling helps achieve the

and LOFFLTH registers (see Table 39 and Table 40, respectively). Figure 54. Simplified Schematic of a Single ECG Channel

Table 37. This allows maximum flexibility of the input stage for a variety of applications. tion, with WCT created using the common-mode amplifier. digital core will calculate each lead from the electrode signals. 2 kHz and 16 kHz data rates (see Figure 57). as described in Table 32 (see Figure 59). ADAS1000-1/ADAS1000-2 (see Figure 58 and Figure 60). Figure 55. Electrode and Lead Configurations 1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE. 2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL INPUT (ANALOG LEAD MODE). 3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

Figure 58. Electrode and Lead Configurations, Common Electrode A Figure 59. Electrode and Lead Configurations, Single-Ended Input Electrode 1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE. 2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL INPUT (ANALOG LEAD MODE). 3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

2 IN THIS CASE

1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE. 2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL INPUT (ANALOG LEAD MODE). 3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

Figure 60. Electrode and Lead Configurations, Common Electrode B 1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE. 2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE). 3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

electrode is buffered, these buffers are omitted for clarity.  If SW1 is closed, SW7 must be open. buffer is required if there is any loading on the CM_OUT pin. Figure 64. Common-Mode Generation Block Table 11. Truth Table for Common-Mode Selection

0 X X X X X Powered down, paths disconnected

1 X 1 X X X SW1 External VCM selected

ADAS1000-3/ADAS1000-4 Data Sheet CALIBRATION DAC Within the ADAS1000-3/ADAS1000-4, there are a number of calibration features. The 10-bit calibration DAC can be used to correct channel gain errors (to ensure channel matching) or to provide several test tones. The options are as follows:

• DC voltage output (range: 0.3 V to 2.7 V). The DAC transfer function for dc voltage output is ( ) −×+ 12V4.2V3.0 10 code
• 1 mV p-p sine wave of 10 Hz or 150 Hz
• 1 mV 1 Hz square wave Internal switching allows the calibration DAC signals to be routed to the input of each ECG channel (see Figure 63). Alternatively, it can be driven out from the CAL_DAC_IO pin, enabling measurement and correction for external error sources in the entire ECG signal chain. To ensure a successful update of the calibration DAC (see Table 36), the host controller must issue four additional SCLK cycles after writing the new calibration DAC register word. GAIN CALIBRATION The gain for each ECG channel can be adjusted to correct for gain mismatches between channels. Factory trimmed gain correction coefficients are stored in nonvolatile memory on-chip for GAIN 0, GAIN 1, and GAIN 2; there is no factory calibration for GAIN 3. The default gain values can be over- written by user gain correction coefficients, which are stored in volatile memory and available by addressing the appropriate gain control registers (see Table 50). The gain calibration applies to the ECG data available on the standard interface and applies to all data rates. LEAD-OFF DETECTION An ECG system must be able to detect if an electrode is no longer connected to the patient. The ADAS1000-3/ADAS1000-4 support two methods of lead-off detection, ac lead-off detection and dc lead-off detection. The two systems are independent and can be used singly or together under the control of the serial interface (see Table 29). A lead-off event sets a flag in the frame header word (see Table 53). Identification of which electrode is off is available as part of the data frame or as a register read from the lead-off status register (Register LOFF , see Table 47). In the case of ac lead-off, infor- mation about the amplitude of the lead-off signal or signals can be read back through the serial interface (see Table 51). In a typical ECG configuration, the electrodes RA, LA, and LL are used to generate a common mode of Wilson Central Terminal (WCT). If one of these electrodes is off, this affects the WCT signal and any lead measurements that it contributes to. As a result, the ECG measurements on these signals are expected to degrade. The user has full control over the common-mode amplifier and can adjust the common-mode configuration to remove that electrode from the common-mode generation. In this way, the user can continue to make measurements on the remaining connected leads. DC Lead-Off Detection This method injects a small programmable dc current into each input electrode. When an electrode is properly connected, the current flows into the right leg (RLD_OUT) and produces a minimal voltage shift. If an electrode is off, the current charges that pin’s capacitance, causing the voltage at the pin to float positive and create a large voltage change that is detected by the comparators in each channel. These comparators use fixed, gain-independent upper and lower threshold voltages of 2.4 V and 0.2 V , respectively. If the input exceeds either of these levels, the lead-off flag is raised. The lower threshold is included in the event that something pulls the electrode down to ground. The dc lead-off detection current can be programmed via the serial interface. Typical currents range from 10 nA to 70 nA in 10 nA steps. All input pins (RA, LA, LL, V1, V2, and CM_IN) use identical dc lead-off detection circuitry. Detecting if the right-leg electrode has fallen off is necessarily different as RLD_OUT is a low impedance amplifier output. A pair of fixed threshold comparators monitor the output voltage to detect amplifier saturation that would indicate a lead-off condition. This information is available in the DCLEAD-OFF register (Register 0x1E) along with the lead-off status of all the input pins. The propagation delay for detecting a dc lead-off event depends on the cable capacitance and the programmed current. It is approximately Delay = Voltage × Cable Capacitance/Programmed Current For example: Delay = 1.2 V × (200 pF/70 nA) = 3.43 ms DC Lead-Off and High Gains Using dc lead-off at high gains can result in failure of the circuit to flag a lead-off condition. The chopping nature of the input amplifier stage contributes to this situation. When the electrode is off, the electrode is pulled up; however, in this gain setting, the first stage amplifier goes into saturation before the input signal crosses the DCLO upper threshold, resulting in no lead- off flag. This affects the gain setting GAIN 3 (4.2) and partially GAIN 2 (2.8). Increasing the AVDD voltage raises the voltage at which the input amplifiers saturate, allowing the off electrode voltage to rise high enough to trip the DCLO comparator (fixed upper threshold of 2.4 V). The ADAS1000 operates over a voltage range of 3.15 V to 5.5 V . If using GAIN 2/GAIN 3 and dc lead-off, an increased AVDD supply voltage (minimum 3.6 V) allows dc lead-off to flag correctly at higher gains. Rev. B | Page 36 of 80

or amplitude artifacts into the ECG signal. Figure 66. Simplified AC Lead-Off Configuration and CM_IN) and is not supported for the RLD_OUT pin. is low pass filtered and sent to the digital threshold detectors. upper and lower threshold voltages (see Table 39 and Table 40). the same detection thresholds. voltage divider (source and cable capacitance). detected, then increasing the threshold by some safety margin. compensates for many of the circuit variables. connected. The lower threshold checks for a minimum signal level. resulting voltage measurement available on a per channel basis. of range flag is contained in the header word (see Table 53). muxed to be one of the pins for external capacitor connection. and a shallow modulation envelope at the respiration frequency. to sub ohm resolution in the presence of large series resistance.

breathing (or lack thereof). designed for the respiration signal measurement. (±1 V) through the RESPCTRL register (see Table 30). Table 12. Maximum Allowable Cable and Thoracic Loading Figure 67. Simplified Respiration Block Diagram

Figure 68. Respiration Measurement Using External Capacitor

Figure 69. Respiration Using External Capacitor and External Amplifiers has an influence on the carrier frequency as shown in Table 13. Table 13. Control of Respiration Carrier Frequencies

1 X3 1 00 64

1 X3 0 00 32

1 X3 0 01 28

1 X3 0 11 23

1 Control bits from RESPCTL (Register 0x03). 2 Control bit from ECGCTL (Register 0x01). the respiration control register (see Table 30). Table 14. Control of Respiration Carrier Frequency 1 Control bits from RESPCTL (Register 0x03). 2 Control bit from ECGCTL (Register 0x01).

Data Sheet ADAS1000-3/ADAS1000-4 EVALUATING RESPIRATION PERFORMANCE ECG simulators offer a convenient means of studying the ADAS1000-3/ADAS1000-4’s performance. While many simulators offer a variable-resistance respiration capability, care must be taken when using this feature. Some simulators use electrically-programmable resistors, often referred to as digiPOTs, to create the time-varying resistance to be measured by the respiration function. The capacitances at the digitPOT's terminals are often unequal and code- dependent, and these unbalanced capacitances can give rise to unexpectedly large or small results on different leads for the same programmed resistance variation. Best results are obtained with a purpose-built fixture that carefully balances the capacitance presented to each ECG electrode. PACING ARTIFACT DETECTION FUNCTION (ADAS1000-4 ONLY) The pacing artifact validation function qualifies potential pacing artifacts and measures the width and amplitude of valid pulses. These parameters are stored in and available from any of the pace data registers (Address 0x1A, Address 0x3A to Address 0x3C). This function runs in parallel with the ECG channels. Digital detection is performed using a state machine operating on the 128 kHz 16-bit data from the ECG decimation chain. The main ECG signals are further decimated before appearing in the 2 kHz output stream so that detected pace signals are not perfectly time-aligned with fully-filtered ECG data. This time difference is deterministic and may be compensated for. The pacing artifact validation function can detect and measure pacing artifacts with widths from 100 μs to 2 ms and with amplitudes of <400 μV to >1000 m V. Its filters are designed to reject heartbeat, noise, and minute ventilation pulses. The flowchart for the pace detection algorithm is shown in Figure 71. The ADAS1000-4 pace algorithm can operate with the ac lead- off and respiration impedance measurement circuitry enabled. Once a valid pace has been detected in the assigned leads, the pace-detected flags appear in the header word (see Table 53) at the start of the packet of ECG words. These bits indicate that a pace was qualified. Further information on height and width of pace is available by reading the contents of Address 0x1A (Register PACE DATA, see Table 44). This word can be included in the ECG data packet/frame as dictated by the frame control register (see Table 37). The data available in the PACEDATA register is limited to seven bits total for width and height information; therefore, if more resolution is required on the pace height and width, this is available by issuing read commands of the PACExDATA registers (Address 0x3A to Address 0x3C) as shown in Table 52. The on-chip filtering contributes some delay to the pace signal (see the Pace Latency section). Choice of Leads Three identical and independent state machines are available and can be configured to run on up to three of four possible leads (Lead I, Lead II, Lead III, and aVF) for pacing artifact detection. Any necessary lead calculations are performed internally and are independent of EGG channel settings for output data rate, low-pass filter cutoff, and mode (electrode, analog lead, common electrode). These calculations take into account the available front-end configurations as detailed in Table 15. The pace detection algorithm searches for pulses by analyzing samples in the 128 kHz ECG data stream. The algorithm searches for a leading edge, a peak, and a trailing edge as defined by values in the PACEEDGETH, PACEAMPTH, and PACELVLTH registers, along with fixed width qualifiers. The post-reset default register values can be overwritten via the SPI bus, and different values can be used for each of the three pace detection state machines. Some users may not want to use three pace leads for detection. In this case, Lead II is the vector of choice, because this lead is likely to display the best pacing artifact. The other two pace instances can be disabled if not in use. The first step in pace detection is to search the data stream for a valid leading edge. Once a candidate edge has been detected, the algorithm begins searching for a second, opposite-polarity edge that meets with pulse width criteria and passes the (optional) noise filters. Only those pulses meeting all the criteria are flagged as valid pace pulses. Detection of a valid pace pulse sets the flag(s) in the frame header register and stores amplitude and width information in the PACEDATA register (Address 0x1A; see Table 44). The pace algorithm looks for a negative or positive pulse Rev. B | Page 41 of 80

Table 15. Pace Lead Calculation

1 X Analog leads Lead I

1 Register ECGCTL, Bit CHCONFIG, see Table 28. 2 Register CMREFCTL, Bit CEREFEN, see Table 32. 3 Register PACECTL, Bit PACExSEL [1:0], see Table 31.

ADAS1000-3/ADAS1000-4 Data Sheet Pace Edge Threshold This programmable level (Address 0x0E, see Table 41) is used to find a leading edge, signifying the start of a potential pace pulse. A candidate edge is one in which the leading edge crosses a threshold PACEEDGETH from the recent baseline. PACEEDGETH can be assigned any value between 0 and 255. Setting P ACEEDGETH to 0 forces it to the value PACEAMPTH/2 (see the following equation). Non-zero values give the following: PACEEDGETH setting = 162× GAIN VREFN where: N is the 8-bit programmed PACEEDGETH value (1 ≤ N ≤ 255). VREF is the ADAS1000-4 reference voltage of 1.8 V . GAIN is the programmed gain of the ECG channel. The minimum threshold for ×1.4 gain is 19.6 µV , while the maximum for the same gain setting is 5.00 mV . Pace Level Threshold This programmable level (Address 0x0F , see Table 42) is used to detect when the leading edge of a candidate pulse ends. In general, a pace pulse is not perfectly square, and the top, meaning the portion after the leading edge, may continue to increase slightly or droop back towards the baseline. PACELVLTH defines an allowable slope for this portion of the candidate pulse, where the slope is defined as the change in value over an internally- fixed interval after the pace edge is qualified. PACELVLTH is an 8-bit, twos complement number. Positive values represent movement away from the baseline (pulse amplitude is still increasing) while negative values represent droop back towards the baseline. PACELVLTH setting = 162× GAIN VREFN where: N is the 8-bit programmed PACELVLTH value (−128 ≤ N ≤ 127). VREF is the ADAS1000-4 reference voltage of 1.8 V . GAIN is the programmed gain of the ECG channel. The minimum value for ×1.4 gain is 9.8 µV , while the maximum for the same gain setting is 2.50 mV . An additional qualification step, performed after PACELVLTH is satisfied, rejects pulses with a leading edge transition time greater than about 156 µs. This filter improves immunity to motion and other artifacts and cannot be disabled. Overly aggressive ESIS filtering causes this filter to disqualify valid pace pulses. In such cases, increasing the value of PACEEDGETH provides more robust pace pulse detection. Although counterintuitive, this change forces a larger initial deviation from the recent baseline before the pace detection algorithm starts, reducing the time until PACELVLTH comes into play and shortening the apparent leading edge transition. Increasing the value of PACEEDGETH may require a reduction in PACEAMPTH. Pace Amplitude Threshold This register (Address 0x07, see Table 34) sets the minimum valid pace pulse amplitude. PACEAMPTH is an unsigned 8-bit number. The programmed height is given by: PACEAMPTH setting = 162 GAIN VREFN , where: N is the 8-bit programmed PACEAMPTH value (1 ≤ N ≤ 255). VREF is the ADAS1000-4 reference voltage of 1.8 V . GAIN is the programmed gain of the ECG channel. The minimum threshold for ×1.4 gain is 19.6 µV , while the maximum for the same gain setting is 5.00 mV . PACEAMPTH is typically set to the minimum expected pace amplitude and must be larger than the value of PACEEDGETH. The default register setting of N = 0x24 results in 706 μV for a gain = 1 setting. An initial PACEAMPTH setting between 700 µV and 1 mV provides a good starting point for both unipolar and biventricular pacing detection. Values below 250 µV are not recommended because they greatly increase sensitivity to ambient noise from the patient. The amplitude may need to be adjusted much higher than 1 mV when other medical devices are connected to the patient. Pace Validation Filters A candidate pulse that successfully passes the combined tests of PACEEDGETH, PACELVLTH, and PACEAMPTH is next passed through two optional validation filters. These filters are used to reject sub-threshold pulses such as minute ventilation (MV) pulse and signals from inductively coupled implantable telemetry systems. These filters perform different tests of pulse shape using a number of samples. Both filters are enabled by default; Filter 1 is controlled by Bit 9 in the PACECTL register (see Table 31) and Filter 2 is controlled by Bit 10 in the same register. These filters are not available on a lead by lead basis; if enabled, they are applied to all leads being used for pace detection. Pace Width Filter A candidate pulse that successfully passes the edge, amplitude, and noise filters is finally checked for width. When this final filter is enabled, it checks that the candidate pulse is between 100 μs and 2 ms wide. When a valid pace width is detected, the width is stored. Disabling this filter affects only the minimum width (100 µs) determination; the maximum width detection portion of the filter is always active. This filter is controlled by the PACECTL register, Bit 11 (see Table 31). Rev. B | Page 44 of 80

Data Sheet ADAS1000-3/ADAS1000-4 BIVENTRICULAR PACERS As described previously, the pace algorithm expects the pace pulse to be less than 2 ms wide. In a pacer where both ventricles are paced, they can be paced simultaneously. Where they fall within the width and height limits programmed into the algo- rithm, a valid pace will be flagged, but only one pace pulse may be visible. With the pace width filter enabled, the pace algorithm seeks pace pulse widths within a 100 μs to 2 ms window. Assuming that this filter is enabled and in a scenario where two ventricle pacer pulses fire at slightly different times, resulting in the pulse showing in the lead as one large, wider pulse, a valid pace is flagged so long as the total width does not exceed 2 ms. PACE DETECTION MEASUREMENTS Design verification of the ADAS1000-4 digital pace algorithm includes detection of a range of simulated pace signals in addition to using the ADAS1000-4 and evaluation board with one pacemaker device connected to various simulated loads (approximately 200 Ω to over 2 kΩ) and covering the following four waveform corners.

• Minimum pulse width (100 μs), minimum height (to <300 μV)
• Minimum pulse width (100 μs), maximum height (up to 1.0 V)
• Maximum pulse width (2 ms), minimum height (to <300 μV)
• Maximum pulse width (2 ms), maximum height (up to 1.0 V) These scenarios passed with acceptable results. The use of the ac lead-off function had no obvious impact on the recorded pace height, width, or the ability of the pace detection algorithm to identify a pace pulse. The pace algorithm was also evaluated with the respiration carrier enabled; again, no differences in the threshold or pacer detect were noted from the carrier. While these experiments validate the pace algorithm over a confined set of circumstances and conditions, they do not replace end system verification of the pacer algorithm. This can be performed in only the end system, using the system manufacturer’s specified cables and validation data set. EVALUATING PACE DETECTION PERFORMANCE ECG simulators offer a convenient means of studying the perfor- mance and ability of the ADAS1000-4 to capture pace signals over the range of widths and heights defined by the various regulatory standards. While the pace detection algorithm of the ADAS1000 is designed to conform to medical instrument standards (pace widths of 100 μs to 2.00 ms and with amplitudes of <400 μV to >1000 mV), some simulators put out signals wider or narrower than called for in the standards. The pace detection algorithm has been designed to measure a maximum pace widths of 2 ms with a margin of 0.25 ms to allow for simulator variations. PACE WIDTH The ADAS1000-4 is capable of measuring pace widths of 100 μs to 2.00 ms. The measured pace width is available through the PACExDATA registers. These registers have limited resolution. The minimum pace width is 101.56 μs and the maximum is 2.00 ms. The pace detection algorithm always returns a width greater than what is measured at the 50% point, ensuring that the algorithm is capable of measuring a narrow 100 μs pulse. A valid pulse width of 100 μs is reported as 101.56 μs. Any valid pace pulses ≥2.00 ms and ≤ 2.25 ms are reported as 2.00 ms. PACE LATENCY The pace algorithm always examines 128 kHz, 16-bit ECG data, regardless of the selected frame rate and ECG filter setting. A pace pulse is qualified when a valid trailing edge is detected and is flagged in the next available frame header. Pace and ECG data is always correctly time-aligned at the 128 kHz frame rate, but the additional filtering inherent in the slower frame rates delays the frame's ECG data relative to the pace pulse flag. These delays are summarized in Table 16 and must be taken into account to enable correct positioning of the pace event relative to the ECG data. There is an inherent one-frame-period uncertainty in the exact location of the pace trailing edge. PACE DETECTION VIA SECONDARY SERIAL INTERFACE The ADAS1000-3/ADAS1000-4 provide a second serial interface for users to implement their own pace detection schemes. This interface is configured as a master interface. It provides ECG data at the 128 kHz data rate only. The purpose of this interface is to allow the user to access the ECG data at a rate sufficient to allow them to run their own pace algorithm, while maintaining all the filtering and decimation of the ECG data that the ADAS1000-3/ADAS1000-4 offer on the standard serial interface (2 kHz and 16 kHz data rates). This dedicated pace interface uses three of the four GPIO pins, leaving one GPIO pin available even when the secondary serial interface is enabled. Note that the on-chip digital calibration to ensure channel gain matching does not apply to data that is available on this interface. This interface is discussed in more detail in the Secondary Serial Interface section. Rev. B | Page 45 of 80

the usable bits are 19 and 18, respectively. with more decimation for the lower data rates. at the different data rates. Figure 72. ECG Channel Filter Signal Flow Table 16. Relationship of ECG Waveform to Pace Indication1, 2, 3 1 ECG waveform delay is the time required to reach 50% of final value following a step input. 2 Guaranteed by design, not subject to production test. 3 There is an unavoidable residual uncertainty of 8 μs in determining the pace pulse trailing edge. 4 Add 38 μs to obtain the absolute delay for any setting.

18 USABLE BITS

19 USABLE BITS

devices, each device should use its own internal reference. as possible and on the same side of the PCB as the device. ADAS1000-4 device delivers the required eight electrodes. SYNC_GANG and CLK_IO pins are set as inputs. impedance until configured in gang mode. impedance until enabled via gang mode. Figure 73. Master/Slave Connections in Gang Mode, Using Multiple but, rather, must be configured via Table 36.

ADAS1000-3/ADAS1000-4 Data Sheet Common Mode The ADAS1000-3/ADAS1000-4 have a dedicated CM_OUT pin serving as an output and a CM_IN pin as an input. In gang mode, the master device determines the common-mode voltage based on the selected input electrodes. This common- mode signal (on CM_OUT) can then be used by subsequent slave devices (applied to CM_IN) as the common-mode reference. All electrodes within the slave device are then measured with respect to the CM_IN signal from the master device. See the CMREFCTL register in Table 32 for more details on the control via the serial interface. Figure 74 shows the connections between a master and slave device using multiple devices. Right Leg Drive The right leg drive comes from the master device. If the internal RLD resistors of the slave device are to contribute to the RLD loop, tie the RLD_SJ pins of master and slave together. Sequencing Devices into Gang Mode When entering gang mode with multiple devices, both devices can be configured for operation, but the conver- sion enable bit (ECGCTL register, Bit 2, Table 28) of the master device should be set after the conversion enable bit of the slave device. When the master device conversion signal is set, the master device generates one edge on its SYNC_GANG pin. This applies to any slave SYNC_GANG inputs, allowing the devices to synchronize ADC conversions. Rev. B | Page 48 of 80

Figure 74. Configuring Multiple Devices to Extend Number of Electrodes/Leads Table 17. Some Possible Arrangements for Gang Operation

user must collect the ECG data directly from each device. of how to approach interfacing to a master and slave device. requiring isolation is minimized. Figure 75. One Method of Interfacing to Multiple Devices

operate at SCLK frequencies up to 40 MHz. that operates with an SCLK of 20.48 MHz. ECG data-words and other status functions within the device. SDI is brought low for the first bit of the following word. device on the rising edges of SCLK. the frame buffer is empty, this pin is driven busy/high. If the frame buffer is full, this pin is driven low/ready. Figure 76. Serial Interface operation for the device is to send out frames of ECG data. new configuration data to the device while in framing mode. seeing usable framing data again. Address, data, and the read/write bits are all in the same word. ADAS1000-4, the data-word is 32 bits, as shown in Table 18. word is 32 bits (address bits and data bits). Table 18. Serial Bit Assignment (Applies to All Register Table 19. Read/Write Data Stream

16 bits of register). There are no address bits, only data bits. 16-bit words (for example, pace and respiration). rate, words are provided in 16-bit data format (see Table 23). when another read or write command is issued. be held constantly low during the entire frame. a frame contains 13 × 16-bit words when reading at 128 kHz. Table 53) to start framing again. read register command during the last word of frame data. Data shifted out during the next word is the register read data. register contents from the previous read command. Table 20. Example of Reading Registers and Frames Regular register reads are always 32 bits long and MSB first. clocked out before the next frame becomes available. Table 21. SCLK Clock Frequency vs. Packet Data/Frame Rates be configured to provide only the words of interest. See Table 37. Table 22. Default 2 kHz and 16 kHz Data Rate: 32-Bit Frame Word Format Table 23. Default 128 kHz Data Rate: 16-Bit Frame Word Format

Data Sheet ADAS1000-3/ADAS1000-4 Internal operations are synchronized to the internal master clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1 and HP = 0, respectively, see Table 28). Because there is no guaranteed relationship between the internal clock and the SPI's SCLK signal, an internal handshaking scheme is used to ensure safe data transfer between the two clock domains. A full handshake requires three internal clock cycles and imposes an upper speed limit on the SCLK frequency when reading frames with small word counts. This is true for all data frame rates. SCLK (max) = (1.024 MHz × (1 + HP) × words_per_frame × bits_per_word)/3; or 40 MHz, whichever is lower. Exceeding the maximum SCLK frequency for a particular operating mode causes erratic behavior in the E E A A signal and results in the loss of data. DRDY 90B Data Rate and Skip Mode Although the standard frame rates available are 2 kHz, 16 kHz, and 128 kHz, there is also a provision to skip frames to further reduce the data rate. This can be configured in the frame control register (see Table 37). 91B Data Ready (A A DRDY E E A A ) The A A DRDY E E A A pin is used to indicate that a frame composed of decimated data at the selected data rate is available to read. It is high when busy and low when ready. Send commands only when the status of A A DRDY E E A A is low or ready. During power-on, the status of A A DRDY E E A A is high (busy) while the device initializes itself. When initialization is complete, A A DRDY E E A A goes low and the user can start configuring the device for operation. When the device is configured and enabled for conversions by writing to the conversion bit (CNVEN) in the ECGCTL register, the ADCs start to convert and the digital interface starts to make data available, loading them into the buffer when ready. If conver- sions are enabled and the buffer is empty, the device is not ready and A A DRDY E E A A goes high. Once the buffer is full, A A DRDY E E A A goes low to indicate that data is ready to be read out of the device. If the device is not enabled for conversions, the A A DRDY E E A A ignores the state of the buffer full status. When reading packets of data, the entire data packet must be read; otherwise, A A DRDY E E A A stays low. There are three methods of detecting A A DRDY E E A A status.

• A A DRDY E E A A pin. This is an output pin from the ADAS1000-3/ ADAS1000-4 that indicates the device read or busy status. No data is valid while this pin is high. The A A DRDY E E A A signals that data is ready to be read by driving low and remaining low until the entire frame has been read. It is cleared when the last bit of the last word in the frame is clocked onto SDO. The use of this pin is optional.
• SDO pin. The user can monitor the voltage level of the SDO pin by bringing A A CS E E A A low. If SDO is low, data is ready; if high, busy. This does not require clocking the SCLK input. (CPHA = CPOL = 1 only).
• One of the first bits of valid data in the header word availa- ble on SDO is a data ready status bit (see Table 43). Within the configuration of the ADAS1000-3/ADAS1000-4, the user can set the header to repeat until the data is ready. See Bit 6 (RDYRPT) in the frame control register in Table 37. The host controller must read the entire frame to ensure A A DRDY E E A A returns low and ready. If the host controller treats the A A DRDY E E A A as an edge triggered signal and then misses a frame or underruns, the A A DRDY E E A A remains high because there is still data available to read. The host controller must treat the A A DRDY E E A A signal as level triggered, ensuring that whenever it goes low, it generates an interrupt which can initiate a SPI frame transfer. On completion of the transfer the A A DRDY E E A A returns high. 92B Detecting Missed Conversion Data To ensure that the current data is valid, the entire frame must be read at the selected data rate. If a read of the entire frame takes longer than the selected data rate allows, the internal buffer is not loaded with the latest conversion data. The frame header register (see Table 53) provides four settings to indicate an overflow of frame data. The settings of Bits[29:28] report how many frames have been missed since the last valid frame read. A missed frame may occur as a result of the last read taking too long. The data in the current frame is valid data, but it is not the current data. It is the calculation made directly after the last valid read. To clear such an overflow, the user must read the entire frame. Rev. B | Page 53 of 80

2 kHz and 16 kHz frame rates, the 24-bit CRC polynomial used. Figure 77. Input Clock power, the CLK_IO is disabled when not in gang mode. respiration frequency, and pace algorithm corners accordingly. Table 24. CRC Polynomials

can be used for the user’s own pace detection purposes. This interface contains ECG data at 128 kHz data rate only. Data is available in 16-bit words, MSB first.

• GPIO1/MSCLK
• GPIO0/A A MCS E E
• GPIO2/MSDO This interface can be enabled via the GPIO register (see Table 33).

Figure 78. Master SPI Interface for External Pace Detection Purposes the individual channels are not enabled. frames have been missed and how many. contents of all internal registers to their power-on reset state. be issued to complete the reset cycle. A A pin powers down all functions in low power mode. Table 25. Master SPI Frame Format; All Words are 16 Bits 1 As set by the FRMCTL register data DATAFMT, Bit [4], see Table 37.

128 kHz for electrode/lead data (16-bit words). Figure 79. Output Frame Structure for 2 kHz and 16 kHz Data Rates with SDO Data Configured for Electrode or Lead Data Figure 80. Output Frame Structure for 128 kHz Data Rate with SDO Data Configured for Electrode Data

1 CS MAY BE USED IN ONE OF THE FOLLOWING WAYS:

B) USED TO FRAME THE ENTIRE PACKET OF DATA. C) USED TO FRAME EACH INDIVIDUAL 32-BIT WORD. 2 FULL WORD COUNT = 10 (RESPIRATION PHASE EXCLUDED HERE). WORDS MAY BE EXCLUDED, SEE THE FRMCTL REGISTER. B) USED TO FRAME THE ENTIRE PACKET OF DATA. C) USED TO FRAME EACH INDIVIDUAL 16-BIT WORD. 2 FULL WORD COUNT = 13 (RESPIRATION PHASE EXCLUDED HERE). WORDS MAY BE EXCLUDED, SEE THE FRMCTL REGISTER.

24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data). Table 26. SPI Register Memory Map 1 R/W = register both readable and writable; R = read only. 2 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. reserved registers/space. Read operations of unassigned bits are undefined.

this format applies throughout the register map. Table 27. Serial Bit Assignment Table 28. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000 R/W 0 23 LAEN ECG channel enable; shuts down power to the channel; the input becomes high-Z. R/W 0 [20:11] Reserved Reserved, set to 0. R/W 0 10 CHCONFIG Setting this bit selects the differential analog front-end (AFE) input. See Figure 56. 0 (default) = single-ended input (digital lead mode or electrode mode). 1 = differential input (analog lead mode). R/W 00 [9:8] GAIN [1:0] Preamplifier and anti-aliasing filter overall gain. 11 = GAIN 3 = ×4.2 (user gain calibration is required for this gain setting). R/W 0 7 VREFBUF VREF buffer enable. 1 = enabled (when using the internal VREF, VREFBUF must be enabled). 0 (default) = XTAL is clock source. channel mode (gang = 0), this bit is ignored. R/W 0 4 Gang Enable gang mode. Setting this bit causes CLK_IO and SYNC_GANG to be activated. 0 (default) = single channel mode. discussed in the Respiration Carrier Frequency section. 0 (default) = 1 MSPS, low power. 1 = 2 MSPS, high performance/low noise. R/W 0 2 CNVEN Conversion enable. Setting this bit enables the ADC conversion and filters. R/W 0 0 SWRST Software reset. Setting this bit clears all registers to their reset value. This bit automatically clears itself. The software reset requires a NOP command to complete the reset.

Table 29. Lead-Off Control Register (LOFFCTL) Address 0x02, Reset Value = 0x000000 R/W 0 23 LAPH AC lead-off phase. R/W 0 [20:19] Reserved Reserved, set to 0. R/W 0 18 CEPH AC lead-off phase. individual ac lead-off channel enables. 0 (default) = ac lead-off disabled. R/W 0 [14:13] Reserved Reserved, set to 0. individual ac lead-off channel enables. 0 (default) = ac lead-off disabled. R/W 0 [11:9] Reserved Reserved, set to 0. R/W 00 [8:7] ACCURRENT Set current level for ac lead-off. R/W 00 [6:5] Reserved Reserved, set to 0. R/W 000 [4:2] DCCURRENT Set current level for dc lead-off (active only for ACSEL = 0). R/W 0 1 ACSEL DC or AC (out-of-band) lead-off detection. If LOFFEN = 0, this bit is don’t care. When the calibration DAC is enabled, ac lead-off is disabled. R/W 0 0 LOFFEN Enable lead-off detection. 0 (default) = lead-off disabled.

Table 30. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x0000001 [23:17] Reserved Reserved, set to 0. conjunction with RESFREQ to select drive frequency. 0 (default) = periodic every N cycles (default). 0 (default) = normal GPIO3 function. 1 = MSB of RESPDAC driven onto the GPIO3 pin. amplifier stage and input directly to the ADC. See Figure 69. 0 (default) = RESPDAC_LL and RESPDAC_RA. 1 = RESPDAC_LA and RESPDAC_RA. R/W 0 12 RESPCAP Selects source of respiration capacitors. 0 (default) = use internal capacitors. 1 = use external capacitors. R/W 0000 [11:8] RESPGAIN [3:0] Respiration in amp gain (saturates at 10). selected in RESPSEL. EXT_RESP_RA is automatically enabled. R/W 00 [6:5] RESPSEL [1:0] Set leads for respiration measurement. 11 = external respiration path. R/W 00 [4:3] RESPAMP Set the test tone amplitude for respiration drive signal. R/W 00 [2:1] RESPFREQ Set frequency for respiration. R/W 0 0 RESPEN Enable respiration. 0 (default) = respiration disabled. 1 ADAS1000-4 model only, ADAS1000-3 model does not contain this feature.

Table 31. Pace Detection Control Register (PACECTL) Address 0x04, Reset Value = 0x000F881 1 ADAS1000-4 model only, ADAS1000-3 model does not contain this feature.

Table 32. Common-Mode, Reference, and Shield Drive Control Register (CMREFCTL) Address 0x05, Reset Value = 0xE00000 R/W 1 23 LACM Common-mode electrode select. 0 = does not contribute to the common mode. 1 = contributes to the common mode. R/W 0 [20:15] Reserved Reserved, set to 0. R/W 0 14 LARLD RLD summing junction. 0 (default) = does not contribute to RLD input. 1 = contributes to RLD input. R/W 0 [11:10] Reserved Reserved, set to 0. R/W 0 9 CERLD RLD summing junction. 0 (default) = does not contribute to RLD input. 1 = contributes to RLD input. R/W 0 8 CEREFEN Common electrode (CE) reference, see Figure 56. 0 (default) = common electrode disabled. 1 = common electrode enabled. R/W 0000 [7:4] RLDSEL [3:0] Select electrode for reference drive. 0 (default) = common mode is not driven out. 1 = common mode is driven out of the external common-mode pin. R/W 0 2 EXTCM Select the source of common mode (use when operating multiple devices together). 0 (default) = internal common mode selected. 1 = external common mode selected (all the internal common-mode switches are off ). R/W 0 1 RLDSEL Enable right leg drive reference electrode. R/W 0 0 SHLDEN Enable shield drive. 0 (default) = shield drive disabled.

Table 33. GPIO Control Register (GPIOCTL) Address 0x06, Reset Value = 0x000000

Table 34. Pace Amplitude Threshold Register (PACEAMPTH) Address 0x07, Reset Value = 0x2424241 1 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 35. Test Tone Register (TESTTONE) Address 0x08, Reset Value = 0x000000

Table 36. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x0020001 0 [23:14] Reserved Reserved, set to 0. chopped to lower 1/f noise. Chopping is performed at 256 kHz. R/W 0 12 CALMODEEN Calibration mode enable. 0 (default) = disable calibration mode. R/W 0 11 CALINT Calibration internal or external. connects calibration DAC signal internally to all ECG channels. R/W 0 10 CALDACEN Enable 10-bit calibration DAC for calibration mode or external use. 0 (default) = disable calibration DAC. CAL_DAC_IO pin. When the calibration DAC is enabled, ac lead-off is disabled. R/W 0000000000 [9:0] CALDATA[9:0] Set the calibration DAC value. 1 To ensure successful update of the calibration DAC, the serial interface must issue four additional SCLK cycles after writing the new calibration DAC register word.

Table 37. Frame Control Register (FRMCTL) Address 0x0A, Reset Value = 0x079000 word and the electrode falls off, the data-word is undefined. 0 (default) = included in frame. R/W 1111 [20:15] Reserved Reserved, set to 111111. R/W 0 14 PACEDIS1 Pace detection. 0 (default) = included in frame. R/W 0 13 RESPMDIS1 Respiration magnitude. 0 (default) = included in frame. R/W 1 12 RESPPHDIS1 Respiration phase. 1 (default) = exclude from frame. R/W 0 11 LOFFDIS Lead-off status. 0 (default) = included in frame. R/W 0 10 GPIODIS GPIO word disable. 0 (default) = included in frame. R/W 0 9 CRCDIS CRC word disable. 0 (default) = included in frame. R/W 0 8 Reserved Reserved, set to 0. 0 (default) = fixed frame format. 1 = autodisable words (words per frame changes). header is continuously sent until data is ready. 0 (default) = always send entire frame. 1 = repeat frame header until ready. R/W 0 5 Reserved Reserved, set to 0. R/W 0 4 DATAFMT Sets the output data format, see Figure 56. 0 (default) = digital lead/vector format (available only in 2 kHz and 16 kHz data rates). R/W 00 [3:2] SKIP[1:0] Skip interval. This field provides a way to decimate the data. 00 (default) = output every frame. 01 = output every other frame. 1× = output every 4th frame. R/W 00 [1:0] FRMRATE[1:0] Sets the output data rate. 00 (default) = 2 kHz output data rate. 01 = 16 kHz output data rate. 10 = 128 kHz output data rate (DATAFMT must be set to 1). 1 ADAS1000-4 model only, ADAS1000-3 model does not contain these features.

Table 38. Filter Control Register (FILTCTL) Address 0x0B, Reset Value = 0x000000 Table 39. AC Lead-Off Upper Threshold Register (LOFFUTH) Address 0x0C, Reset Value = 0x00FFFF Table 40. AC Lead-Off Lower Threshold Register (LOFFLTH) Address 0x0D, Reset Value = 0x000000

Table 41. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x0000001 1 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 42. Pace Level Threshold Register (PACELVLTH) Address 0x0F, Reset Value = 0x0000001 1 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 43. Read Electrode/Lead Data Registers (Electrode/Lead) Address 0x11 to 0x13, Reset Value = 0x0000001 R 0 [23:0] ECG data Channel data value. Data left justified (MSB) irrespective of data rate. therefore, the LSB size is doubled. where N = number of data bits: 16 for 128 kHz data rate or 24 for 2 kHz/16 kHz data rate. 1 If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent.

Table 44. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x0000001, 2, 3 trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. R 000 [22:20] Pace Channel 3 width This bit is log2 (width) − 1 of the pace pulse. R 0000 [19:16] Pace Channel 3 height This bit is the log2 (height) of the pace pulse. Height = 2N × VREF/gain/216. trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. R 000 [14:12] Pace Channel 2 width This bit is log2 (width) − 1 of the pace pulse. R 0000 [11:8] Pace Channel 2 height This bit is the log2 (height) of the pace pulse. Height = 2N × VREF/gain/216. trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. R 000 [6:4] Pace Channel 1 width This bit is log2 (width) − 1 of the pace pulse. R 0000 [3:0] Pace Channel 1 height This bit is the log2 (height) of the pace pulse. Height = 2N × VREF/gain/216. 1 If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. 2 Log data for width and height is provided here to ensure that it fits in one full 32-bit data-word. As a result, there may be some amount of error in the resulting value. For more accurate reading, read the 0x3A, 0x3B, 0x3C registers (see Table 52). 3 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 45. Read Respiration Data—Magnitude Register (RESPMAG) Address 0x1B, Reset Value = 0x0000001, 2 R 0 [23:0] Respiration Magnitude[23:0] Magnitude of respiration signal. This is an unsigned value. 1 If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. 2 ADAS1000-4 model only, ADAS1000-3 model does not contain these features. Table 46. Read Respiration Data—Phase Register (RESPPH) Address 0x1C, Reset Value = 0x0000001, 2 unsigned, the range is from 0 to 2π. If signed, the range is from – π to +π. 1 This register is not part of framing data, but may be read by issuing a register read command of this address. 2 ADAS1000-4 model only, ADAS1000-3 model does not contain these features.

Table 47. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000 Electrode connection status. lead-off is available in the DCLEAD-OFF register (see Table 48). The common electrodes have only dc lead-off detection. amplitude of the other electrodes. 1 = electrode is disconnected.

22 LA lead-off status

21 LL lead-off status

20 RA lead-off status

13 CELO

R 0 [19:14] Reserved Reserved. R 0 12 LAADCOR ADC out of range error. These status bits indicate the resulting ADC code is out of range.

11 LLADCOR

10 RAADCOR

R 0 [9:0] Reserved Reserved. Table 48. DC Lead-Off Register (DCLEAD-OFF) Address 0x1E, Reset Value = 0x0000001 0 = electrode < overrange threshold, 2.4 V. 1 = electrode > overrange threshold, 2.4 V.

22 LA input

21 LL input

20 RA input

13 CE input

electrode bits indicate if the dc lead-off comparator threshold level has been exceeded. 0 = electrode > underrange threshold, 0.2 V. 1 = electrode < underrange threshold, 0.2 V.

11 LA input

10 LL input

9 RA input

2 CE input

1 This register is not part of framing data, but can be read by issuing a register read command of this address.

Table 49. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x0000001 R 0 [23:4] Reserved Reserved. R 0 3 Internal error Internal digital failure. This is set if an error is detected in the digital core. R 0 2 Configuration status This bit is set after a reset indicating that the configuration has not been read yet. Once the configuration is set, this bit is ready. R 0 0 PLL locked status This bit indicates the current state of the PLL locked status. potential areas of malfunction within a failing device. Table 50. User Gain Calibration Registers (CALxx) Address 0x21 to Address 0x23, Reset Value = 0x000000 [31:24] Address [7:0] 0x21: calibration LA. Note that for GAIN 3, there is no factory calibration. 0 = default calibration values (factory calibration). 1 = user calibration values. R/W 0 [22:12] Reserved Reserved, set to 0. R/W 0 [11:0] CALVALUE Gain calibration value. to 0, this register returns the default value for the current gain setting.

Table 51. Read AC Lead-Off Amplitude Registers (LOAMxx) Address 0x31 to Address 0x33, Reset Value = 0x0000001 [31:24] Address [7:0] 0x31: LA ac lead-off amplitude. 0x32: LL ac lead-off amplitude. 0x33: RA ac lead-off amplitude. R/W 0 [23:16] Reserved Reserved. R 0 [15:0] LOFFAM Measured amplitude. rms, scale the output by π/(2√2). 1 This register is not part of framing data, but can be read by issuing a register read command of this address. Table 52. Pace Width and Amplitude Registers (PACExDATA) Address 0x3A to Address 0x3C, Reset Value = 0x0000001, 2 return values of N < 12, that is, pulses narrower than 101.56 μs. 1 These registers are not part of framing data but can be read by issuing a register read command of these addresses. 2 ADAS1000-4 model only, ADAS1000-3 model does not contain these features.

Table 53. Frame Header (FRAMES) Address 0x40, Reset Value = 0x8000001 R 1 31 Marker Header marker, set to 1 for the header. R 0 30 Ready bit Ready bit indicates if ECG frame data is calculated and ready for reading. 0 = ready, data frame follows. including this header word is valid but old if the overflow bits are >0. flag, where a nonzero value indicates an overflow. 11 = 3 or more frames missed. R 0 27 Fault Internal device error detected. R 0 26 Pace 3 detected Pace 3 indicates pacing artifact was qualified at most recent point. 1 = pacing artifact present. R 0 25 Pace 2 detected Pace 2 indicates pacing artifact was qualified at most recent point. 1 = pacing artifact present. R 0 24 Pace 1 detected Pace 1 indicates pacing artifact was qualified at most recent point. 1 = pacing artifact present. R 0 23 Respiration 0 = no new respiration data. 1 = respiration data updated. 1 = one or more lead-off detected. R 0 21 DC lead-off detected 0 = all leads connected. 1 = one or more lead-off detected. R 0 20 ADC out of range 0 = ADC within range. 1 If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. Table 54. Frame CRC Register (CRC) Address 0x41, Reset Value = 0xFFFFFF1 1 The CRC register is a 32-bit word for 2 kHz and 16 kHz data rate and a 16-bit word for 128 kHz rate. See Table 24 for more details.

particular modes of operation and to start framing ECG data.

1. Write 1 configures the CMREFCTL register for CM =

RLD_OUT electrode. The shield amplifier is enabled.

1. Write 2 configures the FRMCTL register to output seven

is in analog lead mode with a data rate of 2 kHz.

1. Write 3 addresses the ECGCTL register, enabling all
2. Write 4 issues the read command to start putting the

converted data out on the SDO pin.

1. Continue to issue SCLK cycles to read the converted data

to allow the interface to process the new command.

1. Write 1 configures the RESPCTL register with a 56 kHz

the respiration capacitors and measuring on Lead I.

1. Write 2 issues the read command to start putting the

converted data out on the SDO pin.

1. Continue to issue SCLK cycles to read the converted data

at the configured packet data rate.

1. Note that this example assumes that the FRMCTL register
2. Write 1 configures the LOFFCTL register with a dc lead-off

enabled for a lead-off current of 50 nA.

1. Write 2 issues the read command to start putting the

converted data out on the SDO pin.

1. Continue to issue SCLK cycles to read the converted

data at the configured packet data rate.

1. Note that this example assumes that the FRMCTL register

Table 55. Example 1: Initialize the Device for ECG Capture and Start Streaming Data Table 56. Example 2: Enable Respiration and Stream Conversion Data (Applies to ADAS1000-4 Only) Table 57. Example 3: Enable DC Lead-Off and Stream Conversion Data

1. Write 1 configures the CMREFCTL register to VCM_REF

to RLD_OUT, and the shield amplifier enabled.

1. Write 2 addresses the TESTTONE register to enable the

150 Hz sine wave onto all electrode channels.

1. Write 3 addresses the FILTCTL register to change the
2. Write 4 configures the FRMCTL register to output nine

configured to always send, irrespective of ready status. signal correctly on each electrode channel.

1. Write 5 addresses the ECGCTL register, enabling all
2. Write 6 issues the read command to start putting the

converted data out on the SDO pin.

1. Continue to issue SCLK cycles to read the converted data

at the configured packet data rate.

1. Write 1 configures the PACECTL register with all three
2. Write 2 issues the read command to start putting the

converted data out on the SDO pin.

1. Continue to issue SCLK cycles to read the converted data
2. Note that the PACEAMPTH register default setting is
3. Note that this example assumes that the FRMCTL register

Table 58. Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Table 59. Example 5: Enable Pace Detection and Stream Conversion Data (Applies to ADAS1000-4 Only)

eight input electrodes and one right leg drive.

1. Write 1 configures the FRMCTL register to output five
2. Write 2 configures the CMREFCTL register to receive an

external common mode from the master.

1. Write 3 addresses the ECGCTL register, enabling all

CLK_IN input source (derived from master ADAS1000). the master device before it starts converting.

• Write 4 configures the FRMCTL register to output seven words per frame/packet (note that this differs from the number of words in a frame available from the slave device). The frame/packet of words consists of the header, five ECG words, pace, respiration magnitude, and lead-off. In this example, the frame is configured to always send irrespective of ready status. The master, ADAS1000, is in vector mode format with a data rate of 2 kHz. Similar to the slave device, the master could be configured for electrode mode; the host controller would then be required to make the lead calculations. 1. Write 5 configures the CMREFCTL register for CM = WCT = (LA + LL + RA)/3; RLD is enabled onto RLD_OUT electrode. The shield amplifier is enabled. The CM = WCT signal is driven out of the master device (CM_OUT) into the slave device (CM_IN). 2. Write 6 addresses the ECGCTL register, enabling all channels into a gain of 1.4, low noise mode. It configures the device as a master in gang mode and driven from the XTAL input source. The ADAS1000 master is set to differential input, which places it in analog lead mode. This ECGCTL register write puts the master into conversion mode, where the device sends an edge on the SYNC_GANG pin to the slave device to trigger the simultaneous conversions of both devices. 3. Write 7 issues the read command to both devices to start putting the converted and decimated data out on the respective SDO pins. 4. Continue to issue SCLK cycles to read the converted data at the configured packet data rate.

Table 60. Example 6: Writing to Master and Slave Devices and Streaming Conversion Data

ADAS1000-3/ADAS1000-4 Data Sheet POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADAS1000-3/ADAS1000-4 should have ample supply decoupling of 0.01 μF on each supply pin located as close to the device pin as possible, ideally right up against the device. In addition, there should be one 4.7 μF capacitor for each of the power domains, AVDD and IOVDD, again located as close to the device as possible. IOVDD is best split from AVDD due to its noisy nature. Similarly, the ADCVDD and DVDD power domains each require one 2.2 μF capacitor with ESR in the range of 0.5 Ω to 2 Ω. The ideal location for each 2.2 μF capacitor is dependent on package type. For the LQFP package and DVDD decoupling, the 2.2 μF capacitor is best placed between Pin 30 and Pin 31, while for ADCVDD, the 2.2 μF capacitor should be placed between Pin 55 and Pin 56. Similarly for the LFCSP package, the DVDD 2.2 μF capacitor is ideal between Pin 43 and Pin 44, and between Pin 22 and Pin 23 for ADCVDD. A 0.01 μF capacitor is recommended for high frequency decoupling at each pin. The 0.01 μF capacitors should have low effective series resistance (ESR) and effective series inductance (ESL), such as the common ceramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Digital lines running under the device should be avoided because these couple noise onto the device. The analog ground plane should be allowed to run under the device to avoid noise coupling. The power supply lines should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. It is essential to minimize noise on VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. As is the case for all thin packages, take care to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. During layout of board, ensure that bypass capacitors are placed as close to the relevant pin as possible, with short, wide traces ideally on the topside. AVDD While the ADAS1000-3/ADAS1000-4 are designed to operate from a wide supply rail, 3.15 V to 5.5 V , the performance is similar over the full range, but overall power increases with increasing voltage. ADCVDD AND DVDD SUPPLIES The AVDD supply rail powers the analog blocks in addition to the internal 1.8 V regulators for the ADC and the digital core. If using the internal regulators, connect the VREG_EN pin to AVDD and then use the ADCVDD and DVDD pins for decoupling purposes. The DVDD regulator can be used to drive other external digital circuitry as required; however, the ADCVDD pin is purely provided for bypassing purposes and does not have available current for other components. Where overall power consumption must be minimized, using external 1.8 V supply rails for both ADCVDD and DVDD would provide a more efficient solution. The ADCVDD and DVDD inputs have been designed to be driven externally and the internal regulators may be disabled by tying VREG_EN pin directly to ground. UNUSED PINS/PATHS In applications where not all ECG paths or functions might be used, the preferred method of biasing the different functions is as follows:

• Unused ECG paths power up disabled. For low power operation, they should be kept disabled throughout operation. Ideally, these pins should be connected to RLD_OUT if not being used.
• Unused external respiration inputs can be tied to ground if not in use.
• If unused, the shield driver can be disabled and output left to float.
• CM_OUT, CAL_DAC_IO, E E A A , GPIOx, CLK_IO, SYNC_GANG can be left open. DRDY 56B LAYOUT RECOMMENDATIONS To maximize CMRR performance, pay careful attention to the ECG path layout for each channel. All channels should be identical to minimize difference in capacitance across the paths. Place all decoupling as close to the ADAS1000-3/ADAS1000-4 devices as possible, with an emphasis on ensuring that the VREF decoupling be prioritized, with VREF decoupling on the same side as the ADAS1000-3/ADAS1000-4devices, where possible. Rev. B | Page 78 of 80

Figure 82. 56-Lead, Lead Frame Chip Scale Package [LFCSP_VQ] Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP]

6.50 REF

0.20 REF

0.05 MAX

0.01 NOM

0.70 MAX

0.65 NOM

ADAS1000-3/ADAS1000-4 Data Sheet Rev. B | Page 80 of 80 ORDERING GUIDE Model1 Option Description Temperature Range Package

Description

ADAS1000-3BSTZ Tray 3 ECG Channels −40°C to +85°C 64-Lead LQFP ST-64-2 ADAS1000-3BSTZ-RL Reel, 1000 −40°C to +85°C 64-Lead LQFP ST-64-2 ADAS1000-3BCPZ Tray −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7 ADAS1000-3BCPZ-RL Reel, 2500 −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7 ADAS1000-4BSTZ Tray 3 ECG Channels, Pace Algorithm, Re spiration Circuit −40°C to +85°C 64-Lead LQFP ST-64-2 ADAS1000-4BSTZ-RL Reel, 1000 −40°C to +85°C 64-Lead LQFP ST-64-2 ADAS1000-4BCPZ Tray −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7 ADAS1000-4BCPZ-RL Reel, 2500 −40°C to +85°C 56-Lead LFCSP_VQ CP-56-7 EVAL-ADAS1000SDZ ADAS1000 Evaluation Board Evaluation Kit2 EVAL-SDP-CB1Z System Demonstration Board (SDP), used as a controller board for data transfer via USB interface to PC Controller Board3 1 Z = RoHS Compliant Part. 2 This evaluation kit consists of ADAS1000BSTZ × 2 for up to 12-lead configuration. Because the ADAS1000 contains all features, it is the evaluation vehicle for all ADAS1000 variants. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator. ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D10997-0-1/15(B)