ADAR1000

ADAR1000 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer (Rev.B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 79

Technical content

8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer

Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►8 GHz to 16 GHz frequency range ►Half-duplex for transmit and receive modes ►Single-pin transmit and receive control ►360° phase adjustment range ►2.8° phase resolution ►≥31 dB gain adjustment range ►≤0.5 dB gain resolution ►Bias and control for external transmit and receive modules ►Memory for 121 prestored beam positions ►Four −20 dBm to +10 dBm power detectors ►Integrated temperature sensor ►Integrated 8-bit ADC for power detectors and temperature sen- sor ►Programmable bias modes ►4-wire SPI interface

APPLICATIONS

►Phased array radar ►Satellite communications systems GENERAL DESCRIPTION The ADAR1000 is a 4-channel, X and Ku frequency band, beam- forming core chip for phased arrays. This device operates in half- duplex between receive and transmit modes. In receive mode, input signals pass through four receive channels and are combined and output at the common RF_IO pin. In transmit mode, the RF_IO input signal is split and passes through the four transmit channels. In both modes, the ADAR1000 provides a ≥31 dB gain adjustment range and a full 360° phase adjustment range in each radio fre- quency (RF) channel, with 6-bit resolution (less than ≤0.5 dB and 2.8°, respectively). A simple 4-wire serial port interface (SPI) controls all of the on-chip registers. In addition, two address pins allow SPI control of up to four devices on the same serial lines. Dedicated transmit and receive load pins also provide synchronization of all ADAR1000 chips in the same array, and a single pin controls fast switching between the transmit and receive modes. The ADAR1000 is fabricated in a silicon-germanium, bipolar CMOS (BiCMOS) process. The device is available in a compact, 88-termi- nal, 7 mm × 7 mm, LGA package and is specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM Figure 1.

analog.com Rev. B | 2 of 79 Transmit and Receive Switch Driver Control....38 PA Bias, LNA Bias, and Switch Bias Setup

REVISION HISTORY

7/2022—Rev. A to Rev. B

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analog.com Rev. B | 5 of 79 AVDD1 = −5 V, AVDD3 = +3.3 V, TA = 25°C, and the device is programmed to the maximum channel gain and the nominal bias conditions on all channels, unless otherwise noted. Nominal bias register settings: Register 0x034 = 0x08, Register 0x035 = 0x55, Register 0x036 = 0x2D, and Register 0x37 = 0x06. Low power bias register settings: Register 0x034 = 0x05, Register 0x035 = 0x1A, Register 0x036 = 0x2A, and Register 0x37 = 0x03. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OPERATING CONDITIONS RF Range 8 16 GHz Operating Temperature −40 +85 °C TRANSMIT SECTION RF_IO, TX1, TX2, TX3, and TX4 pins Maximum Single Channel Gain1

9.5 GHz 21 dB

11.5 GHz 19 dB

14 GHz 16 dB

Gain Flatness vs. Frequency Across any 1 GHz bandwidth dB From 9 GHz to 14 GHz ±1.0 dB From 8 GHz to 15 GHz ±1.7 dB Gain Variation vs. Temperature 11.5 GHz ±2.5 dB Output 1 dB Compression (P1dB) Maximum gain setting Nominal Bias Setting

9.5 GHz 10 dBm

11.5 GHz 10 dBm

14 GHz 10 dBm

9.5 GHz 6 dBm

11.5 GHz 8 dBm

14 GHz 7 dBm

Saturated Power (PSAT) Maximum gain setting Nominal Bias Setting

9.5 GHz 14 dBm

11.5 GHz 14 dBm

14 GHz 13 dBm

Gain Resolution ≤0.5 dB Root Mean Square (RMS) Gain Error Over phase settings and frequencies 0.2 dB Phase Adjustment Range 360 Degrees Phase Resolution 2.8 Degrees RMS Phase Error Over phase settings and frequencies 2 Degrees Noise Figure Maximum gain setting Nominal Bias Setting

9.5 GHz 22 dB

11.5 GHz 23 dB

14 GHz 25 dB

analog.com Rev. B | 6 of 79 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit Channel to Channel Isolation2 −40 dB Transmit Output to RF_IO Maximum gain setting, 9.5 GHz −60 dB Output Return Loss TX1, TX2, TX3, or TX4 pin −10 dB Input Return Loss RF_IO pin −12 dB Output Third-Order Intercept (IP3) Maximum gain setting, 1 MHz carrier spacing Nominal Bias Setting

9.5 GHz 20 dBm

11.5 GHz 21 dBm

14 GHz 22 dBm

9.5 GHz 15 dBm

11.5 GHz 16 dBm

14 GHz 16 dBm

Maximum Single Channel Gain3 Nominal bias setting

9.5 GHz 10 dB

11.5 GHz 9 dB

14 GHz 7 dB

Maximum Electronic Gain4 Nominal bias setting

9.5 GHz 16 dB

11.5 GHz 15 dB

14 GHz 13 dB

Maximum Coherent Gain5 Nominal bias setting

11.5 GHz 21 dB

14 GHz 19 dB

Gain Flatness Across any 1 GHz bandwidth From 9 GHz to 14 GHz ±1.0 dB From 8 GHz to 15 GHz ±1.7 dB Gain Variation vs. Temperature 11.5 GHz ±3 dB Input P1dB Unmeasured paths enabled and terminated with 50 Ω Nominal Bias Setting

9.5 GHz −16 dBm

11.5 GHz −16 dBm

14 GHz −15 dBm

9.5 GHz −13 dBm

11.5 GHz −12 dBm

14 GHz −10 dBm

Input IP3 Maximum gain setting, carrier spacing 1 MHz; unmeasured paths enabled and terminated with 50 Ω Nominal Bias Setting

9.5 GHz −7 dBm

11.5 GHz −7 dBm

14 GHz −6 dBm

analog.com Rev. B | 7 of 79 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit

11.5 GHz −6 dBm

14 GHz −5 dBm

Gain Adjustment Range Variable gain amplifier (VGA) and step attenuator≥31 dB Gain Resolution ≤0.5 dB RMS Gain Error 0.2 dB Phase Adjustment Range 360 Degrees Phase Resolution 2.8 Degrees RMS Phase Error 2 Degrees Noise Figure Maximum gain setting; unmeasured paths disabled and terminated with 50 Ω Nominal Bias Setting

9.5 GHz 8 dB

11.5 GHz 8 dB

14 GHz 9 dB

9.5 GHz 9 dB

11.5 GHz 10 dB

14 GHz 11 dB

Channel to Channel Isolation6 40 dB RF_IO to Receive Isolation 60 dB Input Return Loss −10 dB Output Return Loss RF_IO pin −12 dB TEMPERATURE SENSOR Range −40 +85 °C Slope 0.8 LSB/°C Nominal Analog-to-Digital Converter (ADC) Output Power-on reset (POR) mode (transmit and receive not enabled), TA = 25°C

145 Decimal

TRANSMIT AND RECEIVE SWITCHING TX_LOAD, RX_LOAD, and TR pins Transmit and Receive Switching Time From rising/falling edge of TR at 50% to RF at 90% 180 ns Phase and Gain Switching Time From rising edge of TX_LOAD or RX_LOAD at 50% to RF at 90% 20 ns POWER DETECTOR DET1, DET2, DET3, and DET4 pins RF Input Power Range 11.5 GHz −20 +10 dBm Input Return Loss −10 dB Nominal ADC Output Code Input power (PIN) = 0 dBm, 11.5 GHz 60 Decimal Resolution 8 Bits POWER AMPLIFIER (PA) DIGITAL-TO-ANALOG CONVERTER (DAC) PA_BIAS1, PA_BIAS2, PA_BIAS3, and PA_BIAS4 pins Resolution 8 Bits Voltage Range −4.8 to 0 V Source and Sink Current −10 to +10 mA Off to On Switching Time From TR or CSB at 50% to VOUT at 90%, VOUT from −1 V to −2 V, 1 nF CLOAD 60 ns On to Off Switching Time From TR or CSB at 50% to VOUT at 10%, VOUT from −1 V to −2 V, 1 nF CLOAD 60 ns LOW NOISE AMPLIFIER (LNA) DAC LNA_BIAS pin Resolution 8 Bits

analog.com Rev. B | 8 of 79 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit Voltage Range −4.8 to 0 V Source and Sink Current −10 to+10 mA Off to On Switching Time From TR or CSB at 50% to VOUT at 90%, VOUT from −2 V to −1 V, 1 nF CLOAD 60 ns On to Off Switching Time From TR or CSB at 50% to VOUT at 10%, VOUT from −1 V to −2 V, 1 nF CLOAD 60 ns TRANSMIT AND RECEIVE MODULE CONTROLTR_SW_POS, TR_SW_NEG, TR_POL pins Voltage Range TR_SW_NEG, TR_POL −4.8 to 0 V TR_SW_POS 0 to 3.2 V Off to On Switching Time From TR or CSB at 50% to VOUT at 90% 15 ns On to Off Switching Time From TR or CSB at 50% to VOUT at 10% 15 ns LOGIC INPUTS7 TR, RX_LOAD, TX_LOAD, CSB, SCLK, and SDIO pins Input High Voltage (VIH) 1.0 V Input Low Voltage (VIL) 0.4 V High and Low Input Current (IINH, IINL) ±1 µA Input Capacitance (CIN) 1 pF LOGIC OUTPUTS SDO and SDIO pins Output High Voltage (VOH) Output high current (IOH) = 0 mA (open circuit) 1.8 V Output Low Voltage (VOL) Output low current (IOL) = 0 mA (open circuit) 0 V Output High Voltage (VOH) Output high current (IOH) = −10 mA 1.4 V Output Low Voltage (VOL) Output low current (IOL) = 10 mA 0.4 V POWER SUPPLIES AVDD1 −5.25 −5 −4.75 V AVDD3 3.1 3.3 3.5 V IAVDD1 Quiescent (reset state) −4 mA IAVDD1 PA bias outputs fully loaded −50 mA IAVDD3 Reset Mode (Standby) 23 mA Transmit Mode Four channels enabled, nominal bias 350 mA Four channels enabled, low bias setting 240 mA Receive Mode Four channels enabled, nominal bias 260 mA Four channels enabled, low bias setting 160 mA 1 Single channel transmit gain defined as the ratio of output power at any Tx output port to the input power applied to the RF_IO port. 2 From one transmit channel port to another, both channels must be set to the maximum gain. 3 Single channel receive gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports terminated in 50 Ω. 4 Electronic gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports driven and phased for coherent combining with 6 dB subtracted. The electronic gain is approximately 6 dB higher than the single path gain, and 6 dB lower than coherent gain. 5 Coherent gain is the ratio of output power at RF_IO to the input power applied to any single receive port, with the other three receive ports driven and phased for coherent combining. 6 From one receive channel port to another, both channels must be set to the maximum gain. 7 Inputs have 100 mV (typical) of hysteresis. TIMING SPECIFICATIONS AVDD1 = −5 V, AVDD3 = +3.3 V, TA = 25°C, unless otherwise noted.

1 Applicable to any receive or transmit input. ing conditions for extended periods may affect product reliability. Table 4. Thermal Resistance 1 Simulated based on PCB specified in JESD-51.

2 Simulated with cold plate attached on top of the package using 100 μm of

thermal interface material (3.6 W/mK). damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Table 5. Pin Function Descriptions default value upon power up or soft reset. on-chip capacitor. The dc bias is 0 V due to the on-chip shunt inductor. the PA_ON pin, Register 0x02A (CH2_PA_BIAS_ON value), and Register 0x047 (CH2_PA_BIAS_OFF value). default value upon power up or soft reset. the PA_ON pin, Register 0x029 (CH1_PA_BIAS_ON value), and Register 0x046 (CH1_PA_BIAS_OFF value). default value upon power up or soft reset. regulator bias voltage with a 100 kΩ resistor. B4 TR_POL Gate Control Output for External Polarization Switch (0 V or −5 V). B11 AVDD1 −5 V Power Supply. AVDD1 provides the negative currents for sinking the PA_BIASx and LNA_BIAS outputs. or at the same time as the AVDD1 pin (−5 V). C1 TX3 Channel 3 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and series capacitor. C13 RX2 Channel 2 Input in Receive Mode. This pin is ac-coupled via an on-chip balun. E1 RX3 Channel 3 Input in Receive Mode. This pin is ac-coupled via an on-chip balun. E13 TX2 Channel 2 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and a series capacitor. the detector disabled and either provide a 50 Ω termination or ground the input. the detector disabled and either provide a 50 Ω termination or ground the input. J1 TX4 Channel 4 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and a series capacitor. J13 RX1 Channel 1 Input in Receive Mode. This pin is ac-coupled via an on-chip balun. L1 RX4 Channel 4 Input in Receive Mode. This pin is ac-coupled via an on-chip balun. L13 TX1 Channel 1 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and a series capacitor. M4 SDO SPI Serial Data Output (1.8 V CMOS Logic). Enabled when SDO ACTIVE Bit = 1. Used in 4-wire SPI protocol. Pin has a readback error when sharing a bus with other chips. See SDO Readback Problem and Solution. protocol when SDO ACTIVE Bit = 0. read cycle, output data changes at the falling edge of SCLK.

to ground if not using pin. Logically OR'ed internally with LDRX_OVERRIDE signal. to ground if not using pin. Logically OR'ed internally with LDTX_OVERRIDE signal. N5 ADDR1 Address Pin for 2-Bit Chip Address Code (1.8 V CMOS Logic). Corresponds to Bit 14 in the SPI address header. ADDR1 and ADDR0 together select one of four core chips to accept the serial instructions and data. the detector disabled and either provide a 50 Ω termination or ground the input.

pin (high) is used for transmit and receive control. performance for lower dc power. both the transmit and receive subcircuits power down. input, allowing fast switching between transmit and receive modes. receive subcircuits on while in receive mode. Table 6. SPI Settings for Nominal and Low Power Modes Figure 93. Receive Subcircuit Enabling Logic

MUX_SEL (Bits[3:1]). See Table 7. clock). This bit is active high and is self clearing. ►The CLK_EN (Bit 5) turns on ADC clock oscillator; active high. a 250 kHz clock frequency (low and high, respectively).

1. The ST_CONV bit is asserted high via SPI write to Register
2. The ADC input is sampled during four ADC clock cycles.
3. The ADC input is held and the conversion happens over the
4. The ADC_EOC bit asserts high and data in Register 0x33

becomes valid after 16 total ADC clock cycles. Table 7. Mux Selection Decoding An example write to Chip 2 has the following address bit settings. ADDR0 is set to low with the address header Bits[14:13] = 10. the amplitude and phase settings are sourced from. ►If BEAM_RAM_BYPASS = 0, data sourced from memory. ►If BEAM_RAM_BYPASS = 1, data sourced from registers. 0x1790 and transmit bias settings start at 0x1F90. greater flexibility. This is described in Single Memory Fetch section. is provided in Table 31 in the SPI Programming Example section.

1. Set BEAM_RAM_BYPASS low in Register 0x038.
2. Perform Step a or Step b, but not both:

analog.com Rev. B | 33 of 79 0x03A (for transmit) and assert the fetch bit high (Bit 7) in each register. b. For loading different beam positions indices to individual channels, assert TX_CHX_RAM_BYPASS in Register 0x38 for transmit channels and/or RX_ CHX_RAM_BYPASS for receive channels. Then, write the desired 7-bit beam posi- tion to Register 0x3D through Register 0x40 for the receive channels and Register 0x41 through Register 0x44 for the transmit channels, and assert the fetch bit high in each register. 3. Provide at least six additional clock cycles on SCLK to load the new data from the RAM. For data load, SCLK is independent of CSB state. Data is loaded when CSB is high and SCLK is applied or when CSB is low during a SPI write/read. 4. Pulse the TX_LOAD/RX_LOAD pin or the LDTX_OVER- RIDE/LDRX_OVERRIDE bit for the new data to take effect. Keep the transmit and receive load commands separate be- cause loading problems can occur when the TX_LOAD and RX_LOAD pins are pulsed high together or the LDTX_OVER- RIDE/LDRX_OVERRIDE bits are asserted high in the same SPI write. Keep the pin pulsing separated by at least eight SCLK cycles for the former, and asserting the bits in separate SPI writes for the latter. Bias Setting Memory Fetch Seven memory locations are provided for storing bias settings for all the transmit subcircuits (also stored in Register 0x036 and Register 0x037) and the external PA bias on and off values for the PA_BIASx pins (also stored in Register 0x29 through Register 0x2C and Register 0x46 through Register 0x49). Similarly, seven memory locations are provided for storing bias settings for the receive chan- nel subcircuits (also stored in Register 0x34 and Register 0x35) and the external LNA bias on and off values for the LNA_BIAS pin (also stored in Register 0x2D and Register 0x4A) When the BIAS_RAM_BYPASS bit (Register 0x38, Bit 5) is at logic low, all subcircuit and external bias settings are sourced from memory (instead of the registers). After the bias setting is written to the RAM (see the ADAR1000 Memory Map), perform the following steps to fetch a bias setting from memory: 1. Set BIAS_RAM_BYPASS low in Register 0x038. 2. Write the desired 3-bit bias setting (Value 0 through Value 6 maps to bias Setting 1 through Setting 7) to Register 0x051 (for receive) or Register 0x052 (for transmit), and assert the fetch bit high (Bit 3) in each register. 3. Provide at least six additional clock cycles on SCLK to load the new data from the RAM. For data load, SCLK is independent of the CSB state: data is loaded when CSB is high and SCLK is applied or when CSB is low during a SPI write/read. Sequencing Through Memory Beam Positions The beam positions can be stepped sequentially through the posi- tions stored in memory. Sequencing through the beam positions eliminates the need for a SPI register write to load the next beam position, resulting in faster beam transitions. An example of this operation is shown in Figure 70. To use this function, perform the following steps: 1. Load Register 0x04D and Register 0x04E with the desired 7-bit transmit channel start and stop beam position indices of the sequence 2. Load Register 0x04F and Register 0x050 with the desired 7-bit receive channel start and stop beam position indices of the sequence. 3. If sequencing through transmit beam positions, assert only TX_BEAM_STEP_EN, and keep RX_BEAM_STEP_EN low in Register 0x038. If RX_BEAM_STEP_EN is also asserted high, the first transmit beam position of the first sequence does not fetch and load correctly. However, on subsequent times through the sequence, the first transmit beam position loads correctly when RX_BEAM_STEP_EN is asserted high. If sequencing through receiver beam positions, TX_BEAM_STEP_EN and RX_BEAM_STEP_EN bits can both be asserted high. The first receive beam position fetches and loads correctly when TX_BEAM_STEP_EN is asserted high. 4. Provide at least six additional clock cycles on SCLK to load the starting beam position from the RAM. For data load, SCLK is independent of the CSB state. Data is loaded when CSB is high and SCLK is applied or when CSB is low during a SPI write/read. 5. Pulse the TX_LOAD/RX_LOAD pin or the LDTX_OVER- RIDE/LDRX_OVERRIDE bit for the starting beam position to take effect. Keep the transmit and receive load commands separate be- cause loading problems can occur when the TX_LOAD and RX_LOAD pins are pulsed high together or the LDTX_OVER- RIDE/LDRX_OVERRIDE bits are asserted high in the same SPI Write. Keep the pin pulsing separated by at least 8 SCLK cycles for the former, and asserting the bits in separate SPI writes for the latter. 6. Repeat the last two steps for the next sequential beam position to take effect. After the stop beam position is loaded, the sequence returns to the start beam position and repeats. Toggling Between RAM and Registers While stepping through the beam positions in the RAM, data can be sourced from the SPI registers, and then sourced from RAM again with the following procedure:

1. Assert the BEAM_RAM_BYPASS bit high to source the data
2. Perform a transmit or receive load command over the SPI or

the pins to load the gain and phase data from the registers.

1. To source the data from the RAM again, deassert the

cycles, and perform another transmit or receive load command. high through the process. The memory sequencer stays enabled. issued to load the register gain and phase data. issued to load the next memory position. this RAM to Register to RAM sequence is completed. again at its programmed start beam position index. and need to be controlled separately for proper operation. because doing so causes the beam positions to load improperly. SCLK cycles for proper beam position loading from memory. in receive mode, and vice versa. mit while the device is in receive mode, and vice versa. of each channel at the desired frequency operation. Table 8. Address Decoding Structure vector data of receive Channel 2 for Beam Position 65.

state of the switched attenuator. ter control the VGA gain approximately as shown in Figure 95. high means that attenuator is bypassed). phase setting while loading the next setting in the background.

1. Assert the BEAM_RAM_BYPASS bit (Bit 6 of Register 0x038)

high to source the gain and phase data from the registers.

1. Write data to Register 0x010 through Register 0x01B to set the

receive channel gains and phases.

1. Write data to Register 0x01C through Register 0x027 to set the

transmit channel gains and phases.

1. Issue a transmit or receive load command.

causing the new settings to take effect in the RF subcircuits. There are two ways issue a transmit load command. There are two ways issue a receive load command. pins, pull these pins logic low. memory, see the Memory Access section. Figure 95. Normalized Gain vs. 7-Bit Gain Control Code to the receive or transmit working registers as shown in Table 9. Table 9. Step Attenuator Control

polarity Bit 5 and the VM Q Gain Bits[4:0]. Table 10. Quadrant 1 Phase Control—Mapping of I and Q VM VGA Register Table 11. Quadrant 2 Phase Control—Mapping of I and Q VM VGA Register Table 12. Quadrant 3 Phase Control—Mapping of I and Q VM VGA Register

Table 13. Quadrant 4 Phase Control—Mapping of I and Q VM VGA Register appropriately with the TX_EN and RX_EN bits.

is deasserted, both pins are floating. Register 0x031) to logic high. Table 14. Controlling TR_SW_POS and TR_SW_NEG Output

0 X X X X X X Floating Floating

some inputs are don't care depending on the settings). See Table 16 for all control combinations. Table 15. PA Bias Output Control by Inputs or if the bias DACs can be controlled with the other inputs (BIAS_CTRL = 1). EXT_PAx_BIAS_ONExternal PA Bias on data that can be sourced from multiple locations. EXT_PAx_BIAS_OFFExternal PA Bias off data that can be sourced from multiple locations. Input Pins TR Determines transmit or receive mode of chip when TR_SOURCE = 1. in transmit mode, BIAS_CTRL is set to 1, and in TR pin control. Table 16. Control of PA Bias Outputs

0 X1 X1 X1 X1 EXT_PAx_BIAS_ON

is controlled by a combination of inputs (see Table 17). by LNA_BIAS_ON data. See Table 18 for all control combinations. Table 17. LNA Bias Output Control by Inputs can be controlled with the other inputs (BIAS_CTRL = 1). on the ADAR1000 product page. EXT_LNA_BIAS_ONExternal LNA Bias on data that can be sourced from multiple locations. on the ADAR1000 product page. EXT_LNA_BIAS_OFFExternal LNA Bias off data that can be sourced from multiple locations. Table 18. Control of LNA_BIAS Output

0 X1 X1 X1 X1 Open circuit (floating)

upon power-up. That is, all PA_BIASx pins are driven to 0 V. ►The LNA_BIAS pin is floating upon power-up. ►TR_SW_POS and TR_SW_NEG are floating upon power-up. pin control is established. See Table 19 for the bit settings. Table 19. Bias Bit Settings for TR Pin Control Set the bits as shown in Table 20. Table 20. Bias Bit Settings for SPI Control Bit 5 RX_EN = 1 Enable receive paths. Bit 6 TX_EN = 0 Disables transmit paths. the TR_SPI bit, while in SPI control. PA_BIASx pins while in SPI control mode. pin control is established. Set the bits as shown in Table 21. Table 21. LNA Bias Bit Settings for TR Pin Control Bit 4 LNA_BIAS_OUT_EN = 1Enables LNA bias driver.

Set the bits as shown in Table 22. Table 22. LNA Bias Bit Settings for SPI Control Bit 4 LNA_BIAS_OUT_EN = 1Enables LNA bias driver. Bit 6 BIAS_CTRL = 1 Enables control of bias pins. Bit 5 RX_EN = 1 Enable receive paths. Bit 6 TX_EN = 0 Disables transmit paths. the TR_SPI bit, while in SPI control. and LNA_BIAS pins assume the values in their bias on registers. Table 23 outlines the four possible bias cases. Table 23. Possible External Bias States While in SPI Control subcircuits when both TX_EN and RX_EN are high. TR pin control is established. SW_DRV_TR_MODE_SEL (Bit 7 in Register 0x30). Set the following bits in Register 0x31, as shown in Table 24. Table 24. Register 0x31 Bit Settings for Switch Bias Setup Set the following bits in Register 0x31, as shown in Table 24. Table 25. Register 0x31 Bit Settings for Switch Bias Setup, SPI Control Bit 1 TR_SPI = 0 Puts ADAR1000 in receive mode.

pin drives four ADTR1107 devices. for its four supply voltages, two gate biases, and switch control.

1. Connect a 3.3 V supply to the ADTR1107 via VDD_SW and

VDD_LNA and to the ADAR1000 main supply.

1. Connect a −3.3 V supply to the ADTR1107 via VSS_SW.
2. Set the ADAR1000 TR_SW_POS pin to drive the ADTR1107
3. Connect a −5 V supply to ADAR1000 as the secondary supply.
4. Set the ADAR1000 PA_BIASx pins to −2.5 V to drive the
5. Connect a 5 V supply to the ADTR1107 VDD_PA pin.

pins during the power-up procedure. Figure 97. Interfacing the ADAR1000 to the ADTR1107; One Channel Shown

analog.com Rev. B | 45 of 79 Setting the ADAR1000 TR_SW_POS When powering up the ADAR1000 and ADTR1107 together, the TR_SW_POS pin is the first bias pin that must be set in the sequence. To set this pin after bringing up the +3.3 V and −3.3 V supply voltages while in TR control, follow these steps: 1. Pull the TR pin low. 2. In Register 0x31, set TR_SOURCE = 1 (Bit 2), SW_DRV_EN_TR = 1 (Bit 4), and SW_DRV_TR_STATE = 1 (Bit 7). Pulling the TR pin low and setting the Register 0x31 bits puts the ADAR1000 in receive mode and sets the TR_SW_POS pin to 3.3 V, which, when driving the ADTR1107 CTRL_SW pin, also puts the ADTR1107 in receive mode. If in SPI control, set the following bits in Register 0x31 to set TR_SW_POS: ►Bit 1: TR_SPI = 0 ►Bit 2: TR_SOURCE = 0 ►Bit 4: SW_DRV_EN_TR = 1 ►Bit 7: SW_DRV_TR_STATE = 1 Setting the Register 0x31 bits puts the ADAR1000 in receive mode and sets the TR_SW_POS pin to 3.3 V, which, when driving the ADTR1107 CTRL_SW pin, also puts the ADTR1107 in receive mode. All other bits not mentioned are assumed to be default values. Setting the ADAR1000 PA_BIASx Pins For safe power up of the ADTR1107 PA, the PA_BIASx bias pins must be set to −2.5 V before the +5 V supply is powered up. Once the −5 V supply for the ADAR1000 is powered up, the user can make the following SPI writes if in TR control: 1. Set Bit 6 in Register 0x30, BIAS_CTRL = 1. 2. Set Bit 5 in Register 0x38, BIAS_RAM_BYPASS = 1 3. Set the data in Register 0x29, Register 0x2A, Register 0x2B, and Register 0x2C for approximately −1.1 V, with EXT_PAx_BIAS_ON = 0x39 (where x = 1, 2, 3, or 4). 4. Set the data in Register 0x46, Register 0x47, Register 0x48, and Register 0x49 for approximately −2.5 V, with EXT_PAx_BIAS_OFF = 0x85 (where x = 1, 2, 3, or 4). With TR low, all PA_BIASx pins are set to approximately −2.5 V, which is a safe voltage for the VGG_PA pins when the +5 V supply is powered up. After the +5 V supply is powered up, TR can be pulled high, which sets all the PA_BIASx pins to approximately −1.1 V, which in turn sets the ADTR1107 PA bias current to 220 mA. If in SPI control, to set the PA_BIASx pins, follow these steps: 1. Set Bit 6 in Register 0x30, BIAS_CTRL = 1. 2. Set Bit 6 in Register 0x31, TX_EN = 0. 3. Set Bit 5 in Register 0x38, BIAS_RAM_BYPASS = 1. 4. Set the data in Register 0x29, Register 0x2A, Register 0x2B, and Register 0x2C for approximately −1.1 V, with EXT_PAx_BIAS_ON = 0x39 (where x = 1, 2, 3, or 4). 5. Set the data in Register 0x46, Register 0x47, Register 0x48, and Register 0x49 for approximately −2.5 V, with EXT_PAx_BIAS_OFF = 0x85 (where x = 1, 2, 3, or 4). With TX_EN = 0, all PA_BIASx pins are set to approximately −2.5 V, which is a safe voltage for the VGG_PA pins when the +5 V supply is powered up. After the +5 V supply is powered up, setting TX_EN = 1 sets all the PA_BIASx pins to approximately −1.1 V, which in turn sets the ADTR1107 PA bias current to 220 mA. All other bits not mentioned maintain their values from the Setting the ADAR1000 TR_SW_POS section. Setting the ADAR1000 LNA_BIAS Pin Connecting the ADAR1000 LNA_BIAS pin to the ADTR1107 VGG_LNA is optional because the ADTR1107 LNA is self biased. However, if a different LNA bias setting is desired or if the LNA must be debiased while in transmit mode, perform the following writes to drive the VGG_LNA if in TR control: 1. Set Bit 4 in Register 0x30, LNA_BIAS_OUT_EN = 1. 2. Set the data in Register 0x2D for 0 V, with EXT_LNA_BIAS_ON = 0x00. 3. Set the data in Register 0x4A for approximately −2 V, with EXT_LNA_BIAS_OFF = 0x68. With TR low and after making these SPI writes, the LNA_BIAS pin is at 0 V. Taking TR high causes the LNA_BIAS pin to be at approximately −2 V. If in SPI control, to set the LNA_BIAS pin, follow these steps: 1. Set Bit 4 in Register 0x30, LNA_BIAS_OUT_EN = 1. 2. Set Bit 5 in Register 0x31, RX_EN = 1. 3. Set the data in Register 0x2D for 0 V, with EXT_LNA_BIAS_ON = 0x00. 4. Set the data in Register 0x4A for approximately −2 V, with EXT_LNA_BIAS_OFF = 0x68. After making these SPI writes, the LNA_BIAS pin is at 0 V. Taking RX_EN = 0 causes the LNA_BIAS pin to be at approximately −2 V. All other bits not mentioned maintain their values from the Setting the ADAR1000 PA_BIASx Pins section. POWERING THE ADAR1000 The ADAR1000 has two power supply domains, +3.3V and −5 V. These power supplies can be driven with the synchronous step down regulator LT8609S and the inverting dc-to-dc converter LT3462, respectively. With a single 5.5 V supply driving both the LT8609S and LT3462, the LT8609S generates the +3.3 V supply, while the LT3462 generates the −5 V supply.

corresponding chips required to power multiple ADAR1000 devices. Figure 98. LNA_BIAS Rise Time; −10 mA Load, Measured on P9A of Figure 99. LNA_BIAS Fall Time; −10 mA Load, Measured on P9A of Figure 100. PA_BIAS1, PA_BIAS2, PA_BIAS3, or PA_BIAS 4 Rise Time; −10 Figure 101. PA_BIAS1, PA_BIAS2, PA_BIAS3, or PA_BIAS4 Fall Time; −10 mA Figure 102. Block Diagram of the LT8609S and the LT3462 Powering the Table 26. Power Solutions for Multiple ADAR1000 Devices

4 LT8609S LT1931

16 LT8642S LT3580

32 LTC7151S LT3957A

64 LTM4636 LT3757

address ascension mode, or SDO enabled, respectively. soft reset bits are self clearing. functions are not interrelated, and serve different purposes. bus, LSB_FIRST is low, and ADDR_ASCN is low. Table 28. 4-Wire SPI Mode—Chip 0, Chip 1, Chip 2, and Chip 3 Share SPI Bus Table 29. 3-Wire SPI Mode—Chip 0, Chip 1, Chip 2, and Chip 3 Share SPI Bus

external amplifier bias and switches also change state accordingly. Table 30. Register Programing to Set Up the ADAR1000 0x000 BD Reset whole chip, use SDO line for readback, address auto incrementing in block write mode. 0x401 02 Allow LDO adjustments from user settings. 0x400 55 Adjust LDO regulators. 0x046 85 Set PA_BIAS1 output to approximately −2.5 V in receive mode. 0x047 85 Set PA_BIAS2 output to approximately −2.5 V in receive mode. 0x048 85 Set PA_BIAS3 output to approximately −2.5 V in receive mode. 0x049 85 Set PA_BIAS4 output to approximately −2.5 V in receive mode. 0x029 39 Set PA_BIAS1 output to approximately −1.1 V in transmit mode. 0x02A 39 Set PA_BIAS2 output to approximately −1.1 V in transmit mode. 0x02B 39 Set PA_BIAS3 output to approximately −1.1 V in transmit mode. 0x02C 39 Set PA_BIAS4 output to approximately −1.1 V in transmit mode. 0x02D 00 Set LNA_BIAS to approximately 0 V, while in receive mode. 0x030 1F Enable LNA_BIAS, select fixed output. 0x038 60 Select SPI instead of internal RAM for channel settings. 0x031 1C Select TR input for transmit and receive switching control, enables switch outputs. 0x02F 7F Select all four transmit channel and enable transmit driver, vector modulator, and VGA. 0x036 16 Set transmit VGA bias to 2, vector modulator bias to 6. 0x037 06 Set transmit driver bias to 6. 0x01C FF Set Channel 1 attenuator to 0 dB, VGA gain to maximum. 0x020 36 Set Channel 1 vector modulator I input to positive, Magnitude 16. 0x021 35 Set Channel 1 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x01D FF Set Channel 2 attenuator to 0 dB, VGA gain to maximum. 0x022 36 Set Channel 2 vector modulator I input to positive, Magnitude 16. 0x023 35 Set Channel 2 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x01E FF Set Channel 3 attenuator to 0 dB, VGA gain to maximum. 0x024 36 Set Channel 3 vector modulator I input to positive, Magnitude 16. 0x025 35 Set Channel 3 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x01F FF Set Channel 4 attenuator to 0 dB, VGA gain to maximum. 0x026 36 Set Channel 4 vector modulator I input to positive, Magnitude 16. 0x027 35 Set Channel 4 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x02E 7F Select all four receive channel, enable receive LNA, vector modulator and VGA. 0x034 08 Set receive LNA bias to 8. 0x035 16 Set receive VGA bias to 2, vector modulator bias to 6. 0x010 FF Set Channel 1 attenuator to 0 dB, VGA gain to maximum. 0x014 36 Set Channel 1 vector modulator I input to positive, Magnitude 16. 0x015 35 Set Channel 1 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x011 FF Set Channel 2 attenuator to 0 dB, VGA gain to maximum. 0x016 36 Set Channel 2 vector modulator I input to positive, Magnitude 16. 0x017 35 Set Channel 2 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x012 FF Set Channel 3 attenuator to 0 dB; VGA gain to maximum. 0x018 36 Set Channel 3 vector modulator I input to positive, Magnitude 16. 0x019 35 Set Channel 3 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. 0x013 FF Set Channel 4 attenuator to 0 dB, VGA gain to maximum.

0x01A 36 Set Channel 4 vector modulator I input to positive, Magnitude 16. 0x01B 35 Set Channel 4 vector modulator Q input to positive, Magnitude 15. These two together set phase to 45°. Table 31. ADAR1000 Memory Register Programming Example for Beam Position 0 and Bias Setting 1

1 Transmitter and receiver gain are set to maximum and the phase value is 45° for all channels.

Table 32. Control Registers Summary

000 INTERFACE_

001 INTERFACE_

003 CHIP_TYPE [7:0] CHIP_TYPE 0x00 R

004 PRODUCT_ID_H[7:0] PRODUCT_ID[15:8] 0x00 R

005 PRODUCT_ID_L[7:0] PRODUCT_ID[7:0] 0x00 R

010 CH1_RX_GAIN [7:0] CH1_ATTN_RX RX_VGA_CH1 0x00 R/W

011 CH2_RX_GAIN [7:0] CH2_ATTN_RX RX_VGA_CH2 0x00 R/W

012 CH3_RX_GAIN [7:0] CH3_ATTN_RX RX_VGA_CH3 0x00 R/W

013 CH4_RX_GAIN [7:0] CH4_ATTN_RX RX_VGA_CH4 0x00 R/W

014 CH1_RX_PHASE_

015 CH1_RX_PHASE_

016 CH2_RX_PHASE_

017 CH2_RX_PHASE_

018 CH3_RX_PHASE_

019 CH3_RX_PHASE_

020 CH1_TX_PHASE_

021 CH1_TX_PHASE_

022 CH2_TX_PHASE_

023 CH2_TX_PHASE_

024 CH3_TX_PHASE_

025 CH3_TX_PHASE_

026 CH4_TX_PHASE_

027 CH4_TX_PHASE_

028 LD_WRK_REGS[7:0] RESERVED LDTX_ LDRX_ 0x00 W

029 CH1_PA_BIAS_O

030 MISC_ENABLES[7:0] SW_DRV_ BIAS_ BIAS_EN LNA_ CH1_ CH2_ CH3_ CH4_ 0x00 R/W

031 SW_CTRL [7:0] SW_DRV_ TX_EN RX_EN SW_DRV_ SW_DRV_ TR_ TR_SPI POL 0x00 R/W

032 ADC_CTRL [7:0] ADC_ ADC_ CLK_EN ST_CONV MUX_SEL ADC_EOC 0x00 R/W

033 ADC_OUTPUT [7:0] ADC 0x00 R

034 BIAS_CURRENT_[7:0] RESERVED LNA_BIAS 0x00 R/W

035 BIAS_CURRENT_[7:0] RESERVED RX_VGA_BIAS RX_VM_BIAS 0x00 R/W

036 BIAS_CURRENT_[7:0] RESERVED TX_VGA_BIAS TX_VM_BIAS 0x00 R/W

037 BIAS_CURRENT_[7:0] RESERVED TX_DRV_BIAS 0x00 R/W

038 MEM_CTRL [7:0] SCAN_ BEAM_ BIAS_ RESERVEDTX_BEAM_RX_ TX_CHX_ RX_CHX_ 0x00 R/W

039 RX_CHX_MEM [7:0] RX_CHX_ RX_CHX_RAM_INDEX 0x00 R/W

040 RX_CH4_MEM [7:0] RX_CH4_ RX_CH4_RAM_INDEX 0x00 R/W

041 TX_CH1_MEM [7:0] TX_CH1_ TX_CH1_RAM_INDEX 0x00 R/W

042 TX_CH2_MEM [7:0] TX_CH2_ TX_CH2_RAM_INDEX 0x00 R/W

043 TX_CH3_MEM [7:0] TX_CH3_ TX_CH3_RAM_INDEX 0x00 R/W

044 TX_CH4_MEM [7:0] TX_CH4_ TX_CH4_RAM_INDEX 0x00 R/W

045 REV_ID [7:0] REV_ID 0x00 R

046 CH1_PA_BIAS_

047 CH2_PA_BIAS_[7:0] EXT_PA2_BIAS_OFF 0x00 R/W

048 CH3_PA_BIAS_

049 CH4_PA_BIAS_

050 RX_BEAM_ [7:0] RX_BEAM_STEP_STOP 0x00 R/W

051 RX_BIAS_RAM_

052 TX_BIAS_RAM_

400 LDO_TRIM_CTL_

401 LDO_TRIM_CTL_

►When issuing a soft reset to Chip 0, all chips on the SPI bus perform a soft reset. ►When issuing a soft reset to any chip other than Chip 0, no chips on the SPI bus reset. ascension mode, or SDO enabled, respectively. ascension mode, or SDO enabled, respectively. reverse manner so that the bit pattern is the same, whether sent LSB first or MSB first. Table 33. Bit Descriptions for INTERFACE_CONFIG_A

7 SOFTRESET Soft Reset 0x0 R/W

6 LSB_FIRST LSB First 0x0 R/W

5 ADDR_ASCN Address Ascension 0x0 R/W

4 SDOACTIVE SDO Active 0x0 R/W

3 SDOACTIVE_ SDO Active (duplicate) 0x0 R/W

2 ADDR_ASCN_ Address Ascension (duplicate) 0x0 R/W

1 LSB_FIRST_ LSB First (duplicate) 0x0 R/W

0 SOFTRESET_ Soft Reset (duplicate) 0x0 R/W

Table 34. Bit Descriptions for INTERFACE_CONFIG_B

7 SINGLE_INSTRUCTION Single Instruction 0x0 R/W

6 CSB_STALL CSB Stall 0x0 R/W

5 MASTER_SLAVE_RB Master Slave Readback 0x0 R/W

4 SLOW_INTERFACE_CTRL Slow Interface Control 0x0 R/W

3 RESERVED Reserved 0x0 R

0 RESERVED Reserved 0x0 R

Table 35. Bit Descriptions for CHIP_TYPE Table 36. Bit Descriptions for PRODUCT_ID_H Table 37. Bit Descriptions for PRODUCT_ID_L

Table 38. Bit Descriptions for SCRATCH_PAD Table 39. Bit Descriptions for SPI_REV Table 40. Bit Descriptions for VENDOR_ID_H Table 41. Bit Descriptions for VENDOR_ID_L Table 42. Bit Descriptions for TRANSFER_REG

0 MASTER_SLAVE_XFER Master Slave Transfer 0x0 R/W

Table 43. Bit Descriptions for CH1_RX_GAIN Table 44. Bit Descriptions for CH2_RX_GAIN Table 45. Bit Descriptions for CH3_RX_GAIN Table 46. Bit Descriptions for CH4_RX_GAIN

Table 47. Bit Descriptions for CH1_RX_PHASE_I

5 RX_VM_CH1_POL_I Channel 1 Receive Vector Modulator I Polarity 0x0 R/W

Table 48. Bit Descriptions for CH1_RX_PHASE_Q

5 RX_VM_CH1_POL_Q Channel 1 Receive Vector Modulator Q Polarity 0x0 R/W

Table 49. Bit Descriptions for CH2_RX_PHASE_I

5 RX_VM_CH2_POL_I Channel 2 Receive Vector Modulator I Polarity 0x0 R/W

Table 50. Bit Descriptions for CH2_RX_PHASE_Q

5 RX_VM_CH2_POL_Q Channel 2 Receive Vector Modulator Q Polarity 0x0 R/W

Table 51. Bit Descriptions for CH3_RX_PHASE_I

5 RX_VM_CH3_POL_I Channel 3 Receive Vector Modulator I Polarity 0x0 R/W

Table 52. Bit Descriptions for CH3_RX_PHASE_Q

5 RX_VM_CH3_POL_Q Channel 3 Receive Vector Modulator Q Polarity 0x0 R/W

Table 53. Bit Descriptions for CH4_RX_PHASE_I

5 RX_VM_CH4_POL_I Channel 4 Receive Vector Modulator I Polarity 0x0 R/W

Table 54. Bit Descriptions for CH4_RX_PHASE_Q

5 RX_VM_CH4_POL_Q Channel 4 Receive Vector Modulator Q Polarity 0x0 R/W

Table 55. Bit Descriptions for CH1_TX_GAIN Table 56. Bit Descriptions for CH2_TX_GAIN Table 57. Bit Descriptions for CH3_TX_GAIN

Table 58. Bit Descriptions for CH4_TX_GAIN Table 59. Bit Descriptions for CH1_TX_PHASE_I

5 TX_VM_CH1_POL_I Channel 1 Transmit Vector Modulator I Polarity 0x0 R/W

Table 60. Bit Descriptions for CH1_TX_PHASE_Q

5 TX_VM_CH1_POL_Q Channel 1 Transmit Vector Modulator Q Polarity 0x0 R/W

Table 61. Bit Descriptions for CH2_TX_PHASE_I

5 TX_VM_CH2_POL_I Channel 2 Transmit Vector Modulator I Polarity 0x0 R/W

Table 62. Bit Descriptions for CH2_TX_PHASE_Q

5 TX_VM_CH2_POL_Q Channel 2 Transmit Vector Modulator Q Polarity 0x0 R/W

Table 63. Bit Descriptions for CH3_TX_PHASE_I

5 TX_VM_CH3_POL_I Channel 3 Transmit Vector Modulator I Polarity 0x0 R/W

Table 64. Bit Descriptions for CH3_TX_PHASE_Q

5 TX_VM_CH3_POL_Q Channel 3 Transmit Vector Modulator Q Polarity 0x0 R/W

Table 65. Bit Descriptions for CH4_TX_PHASE_I

5 TX_VM_CH4_POL_I Channel 4 Transmit Vector Modulator I Polarity 0x0 R/W

Table 66. Bit Descriptions for CH4_TX_PHASE_Q

5 TX_VM_CH4_POL_Q Channel 4 Transmit Vector Modulator Q Polarity 0x0 R/W

Table 67. Bit Descriptions for LD_WRK_REGS phase settings. Also can be used when advancing transmit beam position. phase settings. Also can be used when advancing receive beam position.

Table 68. Bit Descriptions for CH1_PA_BIAS_ON Table 69. Bit Descriptions for CH2_PA_BIAS_ON Table 70. Bit Descriptions for CH3_PA_BIAS_ON Table 71. Bit Descriptions for CH4_PA_BIAS_ON Table 72. Bit Descriptions for LNA_BIAS_ON

Table 73. Bit Descriptions for RX_ENABLES

7 RESERVED Reserved 0x0 R

6 CH1_RX_EN Enables Receive Channel 1 Subcircuits 0x0 R/W

5 CH2_RX_EN Enables Receive Channel 2 Subcircuits 0x0 R/W

4 CH3_RX_EN Enables Receive Channel 3 Subcircuits 0x0 R/W

3 CH4_RX_EN Enables Receive Channel 4 Subcircuits 0x0 R/W

2 RX_LNA_EN Enables the Receive Channel LNAs 0x0 R/W

1 RX_VM_EN Enables the Receive Channel Vector Modulators 0x0 R/W

0 RX_VGA_EN Enables the Receive Channel VGAs 0x0 R/W

Table 74. Bit Descriptions for TX_ENABLES

6 CH1_TX_EN Enables Transmit Channel 1 Subcircuits 0x0 R/W

5 CH2_TX_EN Enables Transmit Channel 2 Subcircuits 0x0 R/W

4 CH3_TX_EN Enables Transmit Channel 3 Subcircuits 0x0 R/W

3 CH4_TX_EN Enables Transmit Channel 4 Subcircuits 0x0 R/W

2 TX_DRV_EN Enables the Transmit Channel Drivers 0x0 R/W

1 TX_VM_EN Enables the Transmit Channel Vector Modulators 0x0 R/W

0 TX_VGA_EN Enables the Transmit Channel VGAs 0x0 R/W

Table 75. Bit Descriptions for MISC_ENABLES with device mode (transmit and receive). Table 76. Bit Descriptions for SW_CTRL

Table 77. Bit Descriptions for ADC_CTRL Table 78. Bit Descriptions for ADC_OUTPUT

Table 79. Bit Descriptions for BIAS_CURRENT_RX_LNA Table 80. Bit Descriptions for BIAS_CURRENT_RX Table 81. Bit Descriptions for BIAS_CURRENT_TX Table 82. Bit Descriptions for BIAS_CURRENT_TX_DRV

Table 83. Bit Descriptions for MEM_CTRL

1 TX_CHX_RAM_BYPASS Assert high to load different beam position indices for each transmit channel and

transmit channels and use Register 0x3A. .

0 RX_CHX_RAM_BYPASS Assert high to load different beam position indices for each receive channel and

receive channels and use Register 0x39. Table 84. Bit Descriptions for RX_CHX_MEM

7 RX_CHX_RAM_FETCH Get Receive Channel Beam Settings from RAM 0x0 R/W

Table 85. Bit Descriptions for TX_CHX_MEM

7 TX_CHX_RAM_FETCH Get Transmit Channel Beam Settings from RAM 0x0 R/W

Table 86. Bit Descriptions for RX_CH1_MEM

7 RX_CH1_RAM_FETCH Get Receive Channel 1 Beam Settings from RAM 0x0 R/W

Table 87. Bit Descriptions for RX_CH2_MEM

7 RX_CH2_RAM_FETCH Get Receive Channel 2 Beam Settings from RAM 0x0 R/W

Table 88. Bit Descriptions for RX_CH3_MEM

7 RX_CH3_RAM_FETCH Get Receive Channel 3 Beam Settings from RAM 0x0 R/W

Table 89. Bit Descriptions for RX_CH4_MEM

7 RX_CH4_RAM_FETCH Get Receive Channel 4 Beam Settings from RAM 0x0 R/W

Table 90. Bit Descriptions for TX_CH1_MEM

7 TX_CH1_RAM_FETCH Get Transmit Channel 1 Beam Settings from RAM 0x0 R/W

Table 91. Bit Descriptions for TX_CH2_MEM

7 TX_CH2_RAM_FETCH Get Transmit Channel 2 Beam Settings from RAM 0x0 R/W

Table 92. Bit Descriptions for TX_CH3_MEM

7 TX_CH3_RAM_FETCH Get Transmit Channel 3 Beam Settings from RAM 0x0 R/W

Table 93. Bit Descriptions for TX_CH4_MEM

7 TX_CH4_RAM_FETCH Get Transmit Channel 4 Beam Settings from RAM 0x0 R/W

Table 94. Bit Descriptions for REV_ID Table 95. Bit Descriptions for CH1_PA_BIAS_OFF Table 96. Bit Descriptions for CH2_PA_BIAS_OFF Table 97. Bit Descriptions for CH3_PA_BIAS_OFF

Table 98. Bit Descriptions for CH4_PA_BIAS_OFF Table 99. Bit Descriptions for LNA_BIAS_OFF Table 100. Bit Descriptions for TX_TO_RX_DELAY_CTRL Table 101. Bit Descriptions for RX_TO_TX_DELAY_CTRL

Table 102. Bit Descriptions for TX_BEAM_STEP_START Table 103. Bit Descriptions for TX_BEAM_STEP_STOP Table 104. Bit Descriptions for RX_BEAM_STEP_START Table 105. Bit Descriptions for RX_BEAM_STEP_STOP Table 106. Bit Descriptions for RX_BIAS_RAM_CTL

3 RX_BIAS_RAM_FETCH Get Receive Beam Settings from RAM 0x0 R/W

Table 107. Bit Descriptions for TX_BIAS_RAM_CTL

3 TX_BIAS_RAM_FETCH Get Transmit Channel Beam Settings from RAM 0x0 R/W

Table 108. Bit Descriptions for LDO_TRIM_CTL_0 Table 109. Bit Descriptions for LDO_TRIM_CTL_1

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 107. 88-Terminal Land Grid Array [LGA]