ADAQ7980/ADAQ7988 (Rev. B)

Document overview

  • Manufacturer or author: Analog Devices, Inc.
  • PDF pages: 50

Technical content

16-Bit, 1 MSPS, Integrated Data Acquisition Subsystem Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Easy to use ►μModule data acquisition system ►All active components designed by Analog Devices, Inc. ►50% PCB area savings ►Includes critical passive components ►SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface ►Daisy-chain multiple ADAQ7980/ADAQ7988 devices ►Versatile supply configuration with 1.8 V/2.5 V/3 V/5 V logic interface ►High performance ►16-bit resolution with no missing codes ►Throughput: 1 MSPS (ADAQ7980) and 500 kSPS (ADAQ7988) ►INL: ±8 ppm typical and 20 ppm maximum ►SNR: 91.5 dB typical at 10 kHz (unity gain) ►THD: −105 dB at 10 kHz ►Zero error: ±0.06 mV typical (unity gain) ►Zero error temperature drift: 1.3 µV/°C maximum ►Low power dissipation ►21 mW typical at 1 MSPS (ADAQ7980) ►16.5 mW typical at 500 kSPS (ADAQ7988) ►Flexible power-down modes ►Small, 24-lead, 5 mm × 4 mm LGA package ►Excellent ESD ratings ►3500 V human body model (HBM) ►1250 V field-induced charged device model (FICDM) ►Wide operating temperature range: −55°C to +125°C

APPLICATIONS

►Automated test equipment (ATE) ►Battery powered instrumentation ►Communications ►Data acquisition ►Process control ►Medical instruments GENERAL DESCRIPTION The ADAQ7980/ADAQ7988 are 16-bit analog-to-digital converter (ADC) μModule® data acquisition systems that integrate four com- mon signal processing and conditioning blocks into a system in package (SiP) design that supports a variety of applications. These devices contain the most critical passive components, eliminating many of the design challenges associated with traditional signal chains that use successive approximation register (SAR) ADCs. These passive components are crucial to achieving the specified device performance. The ADAQ7980/ADAQ7988 contain a high accuracy, low power, 16-bit SAR ADC, a low power, high bandwidth, high input impe- dance ADC driver, a low power, stable reference buffer, and an efficient power management block. Housed within a tiny, 5 mm × 4 mm LGA package, these products simplify the design process for data acquisition systems. The level of system integration of the ADAQ7980/ADAQ7988 solves many design challenges, while the devices still provide the flexibility of a configurable ADC driver feedback loop to allow gain and/or common-mode adjustments. A set of four device supplies provides optimal system performance; however, single-supply operation is possible with minimal impact on device operating specifications. The ADAQ7980/ADAQ7988 integrate within a compact, integrated circuit (IC)-like form factor key components commonly used in data acquisition signal chain designs. The µModule family transfers the design burden of component selection, optimization, and layout from designer to device, shortening overall design time, system troubleshooting, and ultimately improving time to market. The serial peripheral interface (SPI)-compatible serial interface fea- tures the ability to daisy-chain multiple devices on a single, 3-wire bus and provides an optional busy indicator. The user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic. Specified operation of these devices is from −55°C to +125°C. Table 1. Integrated SAR ADC μModules

Data Sheet ADAQ7980/ADAQ7988 TABLE OF CONTENTS analog.com Rev. B | 2 of 50 Effect of Feedback Resistor on Frequency LDO Regulator Current-Limit and Thermal 3-Wire CS Mode Without the Busy Indicator....39 4-Wire CS Mode Without the Busy Indicator....41 Using the ADAQ7980/ADAQ7988 With Evaluating the Performance of the

REVISION HISTORY

8/2022—Rev. A to Rev. B Changes to Signal-to-Noise Ratio (SNR) Parameter and Signal-to-Noise-and-Distortion Ratio Changes to Signal-to-Noise Ratio Parameter and Signal-to-Noise-and-Distortion Ratio Parameter, 8/2017—Rev. 0 to Rev. A Changed Integrated Data Acquisition System to μModule, Subsystem to μModule Data Acquisition System, Subsystems to μModule Data Acquisition Systems, and DAQ Subsystem to μModule Data

Data Sheet ADAQ7980/ADAQ7988 TABLE OF CONTENTS analog.com Rev. B | 3 of 50 3/2017—Revision 0: Initial Version

Data Sheet ADAQ7980/ADAQ7988 FUNCTIONAL BLOCK DIAGRAM analog.com Rev. B | 4 of 50 Figure 1.

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 5 of 50 DUAL-SUPPLY CONFIGURATION unity-gain buffer configuration, fSAMPLE = 1 MSPS (ADAQ7980), and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits SYSTEM ACCURACY No Missing Codes 16 Bits Differential Nonlinearity Error (DNL) −14 ±7 +14 ppm1 Integral Nonlinearity Error (INL) −20 ±8 +20 ppm1 Transition Noise 0.6 LSB1 rms Gain Error TA = 25°C −0.01 ±0.002 +0.01 %FS Gain Error Temperature Drift 0.1 0.4 ppm/°C Zero Error TA = 25°C −0.5 ±0.06 +0.5 mV Zero Error Temperature Drift 0.3 1.3 µV/°C Common-Mode Rejection Ratio ADC driver configured as difference amplifier 103 130 dB Power Supply Rejection Ratio Positive V+ = +6.3 V to +8 V, V− = −2 V 75 105 dB Negative V+ = +7 V, V− = −1.0 V to −2.5 V 80 110 dB SYSTEM AC PERFORMANCE Dynamic Range 92 dB2 VREF = 2.5 V 87 dB2 Total RMS Noise 44.4 µV rms Oversampled Dynamic Range Oversample dynamic range frequency (fODR) = 10 kSPS 111 dB2 Signal-to-Noise Ratio (SNR) Input frequency (fIN) = 10 kHz 89.5 91.5 dB2 fIN = 10 kHz, VREF = 2.5 V 84.5 86.5 dB2 Spurious-Free Dynamic Range fIN = 10 kHz 106 dB2 Total Harmonic Distortion (THD) fIN = 10 kHz −105 −100 dB2 Signal-to-Noise-and-Distortion Ratio fIN = 10 kHz 89.1 91 dB2 fIN = 10 kHz, VREF = 2.5 V 84 86 dB2 Effective Number of Bits fIN = 10 kHz 14.65 14.8 Bits Noise Free Code Resolution 14.1 Bits SYSTEM SAMPLING DYNAMICS Conversion Rate ADAQ7980 VIO ≥ 3.0 V 0 1 MSPS VIO ≥ 1.7 V 0 833 kSPS ADAQ7988 VIO ≥ 1.7 V 0 500 kSPS Transient Response Full-scale step 430 500 ns −3 dB Input Bandwidth ADC driver RC filter 4.42 MHz −1 dB Frequency ADC driver RC filter 2.2 MHz −0.1 dB Frequency ADC driver RC filter 0.67 MHz

0.1 Hz to 10 Hz Voltage Noise 17 µV p-p

Aperture Delay 2.0 ns Aperture Jitter 2.0 ns 1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV and 1 LSB = 15.26 ppm. 2 All specifications in dB are referred to a full-scale input, FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 6 of 50 unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE Input Voltage Range Voltage at REF pin 2.4 5.1 V Load Current REFOUT 330 µA Buffer Input Resistance REF 50 MΩ Capacitance REF 1 pF Bias Current 550 800 nA Offset Voltage TA = 25°C 13 125 µV Offset Voltage Drift 0.2 1.3 µV/°C Voltage Noise fIN = 100 kHz 5.2 nV/√Hz Voltage Noise 1/f Corner Frequency 8 Hz Current Noise fIN = 100 kHz 0.7 pA/√Hz

0.1 Hz to 10 Hz Voltage Noise 44 nV rms

Linear Output Current REFOUT ±40 mA Short-Circuit Current REFOUT sinking/sourcing 85/73 mA ADC DRIVER CHARACTERISTICS Voltage Range IN+, IN−, AMP_OUT 0 VREF V Absolute Input Voltage IN+, IN−, AMP_OUT −0.1 +5.1 V ADCN −0.1 +0.1 V −3 dB Bandwidth G = +1, VAMP_OUT = 0.02 V p-p 37 MHz G = +1, VAMP_OUT = 2 V p-p 35 MHz Bandwidth for 0.1 dB Flatness G = +1, VAMP_OUT = 0.1 V p-p 4 MHz Slew Rate G = +1, VAMP_OUT = 2 V step 110 V/µs G = +1, VAMP_OUT = 5 V step 40 V/µs Input Voltage Noise f = 100 kHz 5.2 nV/√Hz 1/f Corner Frequency 8 Hz Noise f = 100 kHz 0.7 pA/√Hz Bias IN+, IN− 550 800 nA Offset 2.1 nA Input Offset Voltage TA = 25°C 13 125 µV Drift 0.2 1.3 µV/°C Open-Loop Gain 111 dB Input Resistance IN+, IN− Common Mode 50 MΩ Differential Mode 260 kΩ Input Capacitance IN+, IN− 1 pF Input Common-Mode Voltage Range Specified performance −0.1 V+ − 1.3 V V Output Overdrive Recovery Time VIN+ = 10% overdrive, fIN = 10 kHz 500 ns Linear Output Current ±40 mA Short-Circuit Current Sinking/sourcing 85/73 mA DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) VIO > 3.0 V −0.3 +0.3 × VIO V

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 7 of 50 Table 3. Parameter Test Conditions/Comments Min Typ Max Unit VIO ≤ 3.0 V −0.3 +0.1 × VIO V High (VIH) VIO > 3.0 V 0.7 × VIO VIO + 0.3 V VIO ≤ 3.0 V 0.9 × VIO VIO + 0.3 V Input Current Low (IIL) −1 +1 µA High (IIH) −1 +1 µA DIGITAL OUTPUTS Data Format Serial 16 bits, straight binary Pipeline Delay Conversion results available immediately after completed conversion VOL ISINK = 500 µA 0.4 V VOH ISOURCE = −500 µA VIO − 0.3 V POWER-DOWN SIGNALING ADC Driver/REF Buffer PD_AMP, PD_REF Voltage Low Powered down <2.2 V High Enabled >2.6 V Turn-Off Time 50% of PD_AMP, PD_REF to <10% of enabled quiescent current 1.25 2.75 µs Turn-On Time Specified performance 2 7.25 µs Dynamic Power Scaling Period Specified performance 10 µs Low Dropout (LDO) Regulator PD_LDO Voltage Low Powered down 1.06 1.12 1.18 V High Enabled 1.15 1.22 1.30 V PD_LDO Logic Hysteresis 100 mV Turn-Off Time 2.2 µF capacitive load 460 650 µs Turn-On Time 370 425 µs POWER REQUIREMENTS VDD 3.5 5 10 V LDO Voltage Accuracy ILDO_OUT = 10 mA, TA = 25°C −0.8 +0.8 % 100 µA < ILDO_OUT < 100 mA, VDD = 3.5 V to 10 V−1.8 +1.8 % LDO Line Regulation VDD = 3.5 V to 10 V −0.015 +0.015 %/V LDO Load Regulation ILDO_OUT = 100 µA to 100 mA 0.002 0.004 %/mA LDO Start-Up Time VLDO_OUT = 2.5 V 380 µs LDO Current-Limit Threshold 250 360 460 mA LDO Thermal Shutdown Threshold TJ rising 150 °C Hysteresis 15 °C LDO Dropout Voltage ILDO_OUT = 10 mA 30 60 mV ILDO_OUT = 100 mA 200 420 mV V+ 3.7 7 V− + 10 V VIO 1.7 5.5 V Total Standby Current1, 2 Static, all devices enabled 1.2 1.7 mA ADC driver, REF buffer disable 56 103 µA ADC driver, REF buffer, LDO disable 14 23 µA ADAQ7980 Current Draw 1 MSPS

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 8 of 50 Table 3. Parameter Test Conditions/Comments Min Typ Max Unit VIO 0.3 0.34 mA V+/V− 1.5 2.0 mA VDD 1.45 1.6 mA ADAQ7980 Power Dissipation 1 MSPS V+/V−/VDD 20 36 mW 1 kSPS, dynamic power scaling enabled3 5.8 9 mW VIO 1.0 1.9 mW Total 21 37.94 mW ADAQ7988 Current Draw VIO 0.15 0.17 mA V+/V− 1.35 1.85 mA VDD 0.73 0.8 mA ADAQ7988 Power Dissipation 500 kSPS V+/V−/VDD 16 26.5 mW 1 kSPS, dynamic power scaling enabled3 5.8 9 mW VIO 0.5 0.95 mW Total 16.5 27.54 mW TEMPERATURE RANGE Specified Performance TMIN to TMAX −55 +125 °C 1 With all digital inputs forced to VIO or GND as required. 2 During the acquisition phase. 3 Dynamic power scaling duty cycle is 10%. 4 Calculated with the maximum supply differential and not the typical supply values.

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 9 of 50 SINGLE-SUPPLY CONFIGURATION VDD = V+ = 5.0 V, V− = 0 V, VIO = 1.7 V to 5.5 V, VREF = 3.3 V, TA = −55°C to +125°C, the ADC driver in a unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits SYSTEM ACCURACY Differential Nonlinearity Error1 −14 ±7 +14 ppm2 Integral Nonlinearity Error1 −20 ±8 +20 ppm2 Transition Noise 0.8 LSB2 rms Gain Error TA = 25°C −0.013 ±0.002 +0.013 %FS Gain Error Temperature Drift 0.1 0.4 ppm/°C Zero Error TA = 25°C −0.5 ±0.06 +0.5 mV Zero Error Temperature Drift 0.35 1.75 µV/°C Common-Mode Rejection Ratio 103 133 dB Power Supply Rejection Ratio Positive V+ = 4.5 V to 5.5 V, V− = 0 V 75 92 dB SYSTEM AC PERFORMANCE Dynamic Range 89 dB3 Total RMS Noise 41.4 µV rms Oversampled Dynamic Range fODR = 10 kSPS 109 dB3 Signal-to-Noise Ratio Input frequency (fIN) = 10 kHz 86.5 88.7 dB3 Spurious-Free Dynamic Range fIN = 10 kHz 103 dB3 Total Harmonic Distortion fIN = 10 kHz −113 −100 dB3 Signal-to-Noise-and-Distortion Ratio fIN = 10 kHz 86.3 88.4 dB3 Effective Number of Bits fIN = 10 kHz 14.1 14.4 Bits Noise Free Code Resolution 13.5 Bits SYSTEM SAMPLING DYNAMICS Conversion Rate ADAQ7980 VIO ≥ 3.0 V 0 1 MSPS VIO ≥ 1.7 V 0 833 kSPS ADAQ7988 VIO ≥ 1.7 V 0 500 kSPS Transient Response Full-scale step 430 500 ns −3 dB Input Bandwidth ADC driver RC filter 4.42 MHz −1 dB Frequency ADC driver RC filter 2.2 MHz −0.1 dB Frequency ADC driver RC filter 0.67 MHz Aperture Delay 2.0 ns Aperture Jitter 2.0 ns 1 Nonlinearity guaranteed over input voltage range. Codes below 150 mV are not represented with a unipolar supply configuration. 3 All specifications in dB are referred to a full-scale input, FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 10 of 50 VDD = V+ = 5.0 V, V− = 0 V, VIO = 1.7 V to 5.5 V, VREF = 3.3 V, TA = −55°C to +125°C, the ADC driver in a unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE Input Voltage Range Voltage at REF pin 2.4 V+ − 1.3 V Load Current REFOUT 330 µA Buffer Input Resistance REF 50 MΩ Capacitance REF 1 pF Bias Current 470 720 nA Offset Voltage TA = 25°C 9 125 µV Offset Voltage Drift 0.2 1.5 µV/°C Voltage Noise fIN = 100kHz 5.9 nV/√Hz Voltage Noise 1/f Corner Frequency 8 Hz Current Noise fIN = 100kHz 0.6 pA/√Hz

0.1 Hz to 10 Hz Voltage Noise 54 nV rms

Linear Output Current REFOUT ±40 mA Short-Circuit Current REFOUT sinking/sourcing 73/63 mA ADC DRIVER CHARACTERISTICS Specified Voltage Range IN+, IN−, AMP_OUT 0.15 VREF V Absolute Input Voltage IN+, IN−, AMP_OUT −0.1 V+ − 1.3 V ADCN −0.1 +0.1 V −3 dB Bandwidth G = +1, VAMP_OUT = 0.02 V p-p 31 MHz G = +1, VAMP_OUT = 2 V p-p 30 MHz Bandwidth for 0.1 dB Flatness G = +1, VAMP_OUT = 0.1 V p-p 4 MHz Slew Rate G = +1, VAMP_OUT = 2 V step 31 V/µs G = +1, VAMP_OUT = 3.15 V step 20 V/µs Input Voltage Noise f = 100 kHz 5.9 nV/√Hz 1/f Corner Frequency 8 Hz Noise f = 100 kHz 0.6 pA/√Hz Bias IN+, IN− 470 720 nA Offset 0.4 nA Input Offset Voltage TA = 25°C 9 125 µV Open-Loop Gain 109 dB Input Resistance IN+, IN− Common Mode 50 MΩ Differential Mode 260 kΩ Input Capacitance IN+, IN− 1 pF Input Common-Mode Voltage RangeSpecified performance −0.1 V+ − 1.3 V Output Overdrive Recovery Time VIN+ = 10% overdrive, fIN = 10 kHz 800 ns Linear Output Current ±40 mA Short-Circuit Current Sinking/sourcing 73/63 mA DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) VIO > 3.0 V −0.3 +0.3 × VIO V VIO ≤ 3.0 V −0.3 +0.1 × VIO V

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 11 of 50 Table 5. Parameter Test Conditions/Comments Min Typ Max Unit High (VIH) VIO > 3.0 V 0.7 × VIO VIO + 0.3 V VIO ≤ 3.0 V 0.9 × VIO VIO + 0.3 V Input Current Low (IIL) −1 +1 µA High (IIH) −1 +1 µA DIGITAL OUTPUTS Data Format Serial 16 bits straight binary Pipeline Delay Conversion results available immediately after completed conversion VOL ISINK = 500 µA 0.4 V VOH ISOURCE = −500 µA VIO − 0.3 V POWER-DOWN SIGNALING ADC Driver/Reference Buffer PD_AMP, PD_REF Voltage Low Powered down <1.5 V High Enabled >1.9 V Turn-Off Time 50% of PD_AMP, PD_REF to <10% of enabled quiescent current 0.9 1.25 µs Turn-On Time Specified performance 2 7.25 µs Dynamic Power Scaling Period Specified performance 10 µs LDO PD_LDO Voltage Low Powered down 1.06 1.12 1.18 V High Enabled 1.15 1.22 1.30 V PD_LDO Logic Hysteresis 100 mV Turn-Off Time 2.2 µF capacitive load 460 650 µs Turn-On Time 370 425 µs POWER REQUIREMENTS VDD 3.5 5 10 V LDO Voltage Accuracy ILDO_OUT = 10 mA, TA = 25°C −0.8 +0.8 % 100 µA < ILDO_OUT < 100 mA, VDD = 3.5 V to 10 V −1.8 +1.8 % LDO Line Regulation VDD = 3.5 V to 10 V −0.015 +0.015 %/V LDO Load Regulation ILDO_OUT = 100 µA to 100 mA 0.002 0.004 %/mA LDO Start-Up Time VLDO_OUT = 2.5 V 380 µs LDO Current-Limit Threshold 250 360 460 mA LDO Thermal Shutdown Threshold TJ rising 150 °C Hysteresis 15 °C LDO Dropout Voltage ILDO_OUT = 10 mA 30 60 mV ILDO_OUT = 100 mA 200 420 mV V+ 3.7 5 V− + 10 V VIO 1.7 5.5 V Total Standby Current1, 2 Static, all devices enabled 1.1 1.7 mA ADC driver, REF buffer disabled 50 103 µA ADC driver, REF buffer, LDO disabled 7 23 µA ADAQ7980 Current Draw 1 MSPS VIO 0.3 0.34 mA

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 12 of 50 Table 5. Parameter Test Conditions/Comments Min Typ Max Unit V+/V− 1.3 2.0 mA VDD 1.45 1.6 mA ADAQ7980 Power Dissipation 1MSPS V+/V−/VDD 13.75 36 mW 1 kSPS, ADC driver dynamic power scaling enabled3 2.9 9 mW VIO 1.0 1.9 mW Total 14.75 37.94 mW ADAQ7988 Current Draw VIO 0.15 0.17 mA V+/V− 1.15 1.85 mA VDD 0.73 0.8 mA ADAQ7988 Power Dissipation 500 kSPS V+/V−/VDD 9.4 26.5 mW 1 kSPS, ADC driver dynamic power scaling enabled3 2.9 9 mW VIO 0.5 0.95 mW Total 9.9 27.54 mW TEMPERATURE RANGE Specified Performance TMIN to TMAX −55 +125 °C 1 With all digital inputs forced to VIO or GND as required. 2 During the acquisition phase. 3 Dynamic power scaling duty cycle is 10%. 4 Calculated with the maximum supply differential and not the typical supply values.

Data Sheet ADAQ7980/ADAQ7988 SPECIFICATIONS analog.com Rev. B | 13 of 50 TIMING SPECIFICATIONS VDD = 3.5 V to 10 V, VIO = 1.7 V to 5.5 V, and TA = −55°C to +125°C, unless otherwise noted In addition to Figure 2 and Figure 3, see Figure 72, Figure 74, Figure 76, Figure 78, Figure 80, and Figure 82 for the additional timing diagrams detailed in Table 6. Table 6. Parameter Symbol Min Typ Max Unit CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE tCONV VIO Above 3.0 V (ADAQ7980) 500 710 ns VIO Above 1.7 V (ADAQ7980) 500 800 ns ADAQ7988 500 1200 ns ACQUISITION PHASE1 tACQ ns ADAQ7980 290 ns ADAQ7988 800 ns TIME BETWEEN CONVERSIONS tCYC VIO Above 3.0 V (ADAQ7980) 1000 ns VIO Above 1.7 V (ADAQ7980) 1200 ns VIO Above 1.7 V (ADAQ7988) 2000 ns CS MODE CNV Pulse Width tCNVH 10 ns SCK Period tSCK VIO Above 4.5 V 10.5 ns VIO Above 3.0 V 12 ns VIO Above 1.7 V 22 ns CNV or SDI Low to SDO D15 MSB Valid tEN VIO Above 3.0 V 10 ns VIO Above 1.7 V 40 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV VIO Above 3.0 V 2 ns VIO Above 1.7 V 10 ns CHAIN MODE SCK Period tSCK VIO Above 4.5 V 11.5 ns VIO Above 3.0 V 13 ns VIO Above 1.7 V 23 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns SDI High to SDO High (with Busy Indicator) tDSDOSDI VIO Above 3.0 V 15 ns VIO Above 1.7 V 22 ns SCK Low Time tSCKL VIO Above 3.0 V 4.5 ns VIO Above 1.7 V 6 ns High Time tSCKH VIO Above 3.0 V 4.5 ns VIO Above 1.7 V 6 ns

TA = 25°C, unless otherwise noted. 1 The digital input pins include the following: CNV, SDI, and SCK. 2 The digital output pin is SDO. 3 Transient currents of up to 100 mA do not cause SCR latch-up. 4 Condition applies when power is provided to the device. ing conditions for extended periods may affect product reliability. material, layout, and environmental conditions. silicon device, only the worst case junction temperature is reported. Table 8. Thermal Resistance 1 These values represent the worst case die junction in the package.

2 Table 8 values were calculated based on the standard JEDEC test conditions

defined in Table 9, unless otherwise specified. P refers to total power dissipation in the chip (W). the top center of the package in the environment of the user.

Table 9. Standard JEDEC Test Conditions damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 4. Pin Configuration Table 10. Pin Function Descriptions 1 IN+ AI ADC Driver Noninverting Input. 2 IN− AI ADC Driver Inverting Input. 3 AMP_OUT AI, AO ADC Driver Output and ADC Input Before Low-Pass Filter (LPF). 4 ADCN AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. to ground for single-supply operation. 11 PD_AMP DI Active Low Power-Down Signal for ADC Driver. When powered down, the reference buffer output enters a high-Z state. 12 LDO_OUT P Regulated 2.5 Output Voltage from On-Board LDO. An internal 2.2 μF bypass capacitor to GND is provided. the device, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, read the data when CNV is high. 14 SDO DO Serial Data Output. The conversion result is output on this pin. SDO synchronizes with SCK. 15 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out onto SDO by this clock. 16 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. signals when low; if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 17 VIO P Input/Output Interface Digital Power. VIO is nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). state or for automatic startup, tie PD_LDO to the VDD pin (Pin 20). 20 VDD P Regulator Input Supply. Bypass VDD to GND with a 2.2 μF capacitor. reference buffer is maintained. This pin requires a 100 nF capacitor to GND for best operation. 24 REF_OUT AO Reference Buffer Output. This pin provides access to the buffered reference signal presented to the ADC. 1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output.

Data Sheet ADAQ7980/ADAQ7988 TERMINOLOGY analog.com Rev. B | 26 of 50 Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error The first transition occurs at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 … 10 to 111 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB − 1.76)/6.02 ENOB is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. Calculate it as follows: Noise Free Code Resolution = log2(2N/Peak to Peak Noise) Noise free code resolution is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels (dB). Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels (dB). It is measured with a signal at −60 dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels (dB). Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

Figure 52. ADC Simplified Schematic are designed by Analog Devices, Inc. matches the desired analog input range. significant space savings and allows flexible configurations. (DAC). Figure 52 shows the simplified schematic of the ADC. disconnected from the ADC input and connected to the GND input. comparator inputs, causing the comparator to become unbalanced. that the conversion is complete.

Data Sheet ADAQ7980/ADAQ7988 THEORY OF OPERATION analog.com Rev. B | 28 of 50 Transfer Functions The ideal transfer characteristics for the ADAQ7980/ADAQ7988 are shown in Figure 53 and Table 11. Figure 53. ADC Ideal Transfer Function Table 11. Output Codes and Ideal Input Voltages

Description

VREF = 5 V Digital Output Code (Hex) FSR – 1 LSB 4.999924 V 0xFFFF2 Midscale + 1 LSB 2.500076 V 0x8001 Midscale 2.5 V 0x8000 Midscale – 1 LSB 2.499924 V 0x7FFF –FSR + 1 LSB 76.3 µV 0x0001 –FSR 0 V 0x00003 1 The ADAQ7980/ADAQ7988 ADC driver in the unity-gain buffer configuration.

2 This is also the code for an overranged analog input (IN+ − IN− above VREF −

VGND). 3 This is also the code for an underranged analog input (IN+ − IN− below VGND). TYPICAL CONNECTION DIAGRAM Figure 54 shows an example of the recommended connection diagram for the ADAQ7980/ADAQ7988 when multiple supplies are available. Figure 54. Typical Application Diagram with Multiple Supplies

3.8 V to 10 V and consumes only 500 µA of supply current at a

to the desired application or configuration. Figure 55. ADC Driver Slew Enhancement Circuit device pair, as shown in Figure 56. Figure 56. ADC Driver Input Stage and Protection Diodes expected, the input current must be limited to less than 10 mA. short circuit), use the current limitation to protect the devices.

2.49 MHz

when performing the previous calculations. Figure 60. Multiplexed Application Timing

amplifier power supply pin (V+ and V−) to ground works best. can help lessen the degradation in PSRR performance. directly to the ground plane. pins during the power-on sequence of the ADAQ7980/ADAQ7988. removing power to the μModule data acquisition systems.

  1. Apply a logic low to PD_AMP, PD_REF, and PD_LDO.
  2. Apply a logic high to PD_LDO.
  3. Apply a voltage to V+ and V−.
  4. Apply a logic high to PD_AMP and PD_REF.
  5. Apply a logic low to PD_AMP, PD_REF, and PD_LDO.
  6. Apply a voltage to VDD and V+.
  7. Apply a logic high to PD_LDO.
  8. Apply a logic high to PD_AMP and PD_REF.
  9. Apply a logic low to PD_AMP and PD_REF.
  10. Remove the voltage from V+ and V−.
  11. Apply a logic low to PD_LDO.
  12. Remove the voltage from VDD.
  13. Remove the voltage from VIO.
  14. Apply a logic low to PD_AMP and PD_REF.
  15. Apply a logic low to PD_LDO.
  16. Remove the voltage from V+ and VDD.
  17. Remove the voltage from VIO.

Figure 70. PSRR vs. Frequency ADAQ7980/ADAQ7988 provide a wide supply range to the user. the V+ and VDD pins together and connect the V− pin to ground. with a single-supply system. temperature. Typical start-up time for the LDO regulator is 380 µs.

Data Sheet ADAQ7980/ADAQ7988 THEORY OF OPERATION analog.com Rev. B | 38 of 50 Internally, the LDO regulator consists of a reference, an error amplifier, a feedback voltage divider, and a positive metal-oxide semiconductor (PMOS) pass transistor. The PMOS pass device, which is controlled by the error amplifier, delivers the output current. The error amplifier compares the reference voltage with the feed- back voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device pulls lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device pulls higher, allowing less current to pass and decreasing the output voltage. The LDO regulator uses the PD_LDO pin to enable and disa- ble the LDO_OUT pin under normal operating conditions. When PD_LDO is high, LDO_OUT turns on, and when PD_LDO is low, LDO_OUT turns off. For automatic startup, tie PD_LDO to VDD. Only apply a logic low to PD_LDO if a logic low is applied to PD_AMP and PD_REF as well. LDO REGULATOR CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The current and thermal overload protection circuits protect the LDO regulator of the ADAQ7980/ADAQ7988 against damage due to excessive power dissipation. The LDO regulator current limits when the output load reaches 360 mA (typical). When the output load exceeds the current limit threshold, the output voltage reduces to maintain a constant current limit. Thermal overload protection is included, which limits the LDO regulator junction temperature to a maximum of 150°C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation), when the junction temperature starts to rise above 150°C, the output turns off, reducing the output current to zero. When the junction temperature drops below 135°C, the output turns on again, and the output current restores to its operating value. Consider the case where a hard short circuit from LDO_OUT to ground occurs. At first, the LDO regulator limits the current thresh- old that can be conducted into the short circuit. If self heating of the junction is enough to cause its temperature to rise above 150°C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135°C, the output turns on and conducts the current limit into the short, again causing the junction temperature to rise above 150°C. This thermal oscillation between 135°C and 150°C causes a current oscillation between the maximum current and 0 mA that continues as long as the short circuit remains at the output. Current-limit and thermal limit protections protect the device against accidental overload conditions. For reliable operation, externally limit the power dissipation of the devices so that the junction temperature does not exceed 125°C. LDO REGULATOR THERMAL CONSIDERATIONS In applications with a low, input to output voltage differential, the LDO regulator does not dissipate much heat. However, in applica- tions with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough to cause the junction temperature of the die to exceed the specified junction temperature of 125°C. When the junction temperature exceeds 150°C, the LDO regula- tor enters thermal shutdown. It recovers only after the junction temperature decreases below 135°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. To guarantee specified operation, the junction temperature of the LDO regulator must not exceed 125°C. To ensure that the junction temperature stays below this value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θJA). The θJA number is dependent on the package assembly compounds used and the amount of material used to solder the package GND pins to the PCB. DIGITAL INTERFACE Though the ADAQ7980/ADAQ7988 have a reduced number of pins, they offer flexibility in their serial interface modes. The ADAQ7980/ADAQ7988, when in CS mode, are compatible with SPI, QSPI™, and digital hosts. This interface can use either a 3- wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This independence is useful in low jitter sampling or simultaneous sampling applications. The ADAQ7980/ADAQ7988, when in chain mode, provide a daisy- chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which these devices operate depends on the SDI level when the CNV rising edge occurs. To select CS mode, set SDI high, and to select chain mode, set SDI low. The SDI hold time is such that when SDI and CNV are connected together, chain mode is selected. In either mode, the ADAQ7980/ADAQ7988 offer the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator enables

Figure 83. Noise Gain of Both Equals 5 the op amp itself, as well as the PCB) has a significant effect. resistor can compensate for this phase loss. resonance due to package and board inductance and capacitance). input range from 100 mV below ground to 1.3 V below positive rail. rail-to-rail output amplifier. Table 14. Recommended Component Values Table 15. ADAQ7980/ADAQ7988 Performance at Selected Input Frequency with 5 V Reference Value

Table 16. Typical Ambient Temperature Performance for the ADAQ7980/ADAQ7988 for Various Gain Configurations (fIN = 10 kHz) The typical ambient temperature results are listed Table 16. performed to fit a bipolar signal into the unipolar input of the ADC. system that sets the full scale of the ADC conversion range. Figure 86. Difference Amplifier Configuration Used to Fit Bipolar Signals to peaking in the frequency response. CS is the input stray capacitance. RF is the feedback resistor. CF is the feedback capacitor. the amplifier is restored, as if there is no stray input capacitance. Table 14 for recommended values.

yield significant heat dissipation benefits. the right side eases this task. crossover of digital and analog signals. planes underneath the ADAQ7980/ADAQ7988 devices. reduce the effect of glitches on the power supply lines. directly to the ground plane. Figure 89. Example Layout for the ADAQ7980/ADAQ7988

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 90. 24-Terminal Land Grid Array [LGA]