ADAQ4381-4

ADAQ4381-4 (Rev.A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 45

Technical content

Quad, 14-Bit, 4 MSPS, Simultaneous Sampling, µModule Data Acquisition Solution Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Easy to use μModule® data acquisition system ►11× footprint reduction vs. discrete solution ►Integrated critical passive components ►5 V single-supply operation ►Guaranteed 14-bit no missing codes ►On-chip oversampling function ►2-bit resolution boost ►Out of range indicator (ALERT) ►INL: ±0.3 LSB typical, ±1 LSB maximum ►SNR (typical) ►85 dB at gain = 1.0, fIN = 1 kHz ►92.4 dB with OSR = ×8 at gain = 1.0, fIN = 1 kHz ►Channel-to-channel phase matching: 0.005° typical at fIN = 20 kHz ►Integrated high precision reference, 3 ppm/oC typical drift ►Gain error: 0.003% typical ►Gain drift: 0.8 ppm/°C typical ►Integrated internal buffer with VCM generation ►Integrated fully differential ADC driver with signal scaling ►Wide input common-mode voltage range ►High common-mode rejection ►Single-ended to differential conversion ►Pin selectable input range with overrange ►Input ranges: ±2 V, ±3.3 V, ±5.5 V, ±11 V ►Gain/attenuation: G = 0.3, 0.6, 1.0, and 1.6 ►High-speed serial interface ►8 mm x 8 mm, 0.8 mm pitch, 81-ball CSP_BGA package

APPLICATIONS

►Lab grade battery test system ►Motor control current sense ►Motor control position feedback ►Sonar ►Power quality monitoring ►Data acquisition system ►Erbium-doped fiber amplifier (EDFA) applications ►I and Q demodulation GENERAL DESCRIPTION The ADAQ4381-4 is a quad-channel precision data acquisition (DAQ) signal chain μModule solution that reduces the development cycle of a precision measurement system by transferring the signal chain design challenges of component selection, optimization, and layout from the designer to the device. Using system-in-package (SIP) technology, the ADAQ4381-4 reduces end system component count by combining multiple com- mon signal processing and conditioning blocks into a single device. These blocks include a quad-channel, high resolution 14-bit, 4 MSPS simultaneous sampling SAR ADC, low noise, fully differential ADC driver amplifier, a 3.3 V precision voltage reference, low noise buffer amplifiers, and low-dropout linear regulator. The ADAQ4381-4 has on-chip oversampling blocks to improve dy- namic range and reduce noise at lower bandwidths. The oversam- pling can boost up to two bits of added resolution. It provides the flexibility of a configurable ADC driver feedback loop to allow four gain and attenuation adjustments, and accept both fully differential or single-ended to differential input configuration. Using Analog Devices, Inc., iPassives® technology, the ADAQ4381-4 incorporates critical passive components with superior matching and drift characteristics to minimize temperature dependent error sources and to offer optimized signal chain performance. Housed in a small 8 mm × 8 mm × 0.8 mm pitch, 81- ball CSP_BGA package, the ADAQ4381-4 enables compact design without sacrificing performance and simplifies end system bill of materials management. The ADAQ4381-4's optimum performance is guaranteed with a single 5 V supply operation, all the required bypass and decoupling capacitors are included inside the package. The level of ADAQ4381-4 system integration solves many design challenges, which enables a compact and simple solution for a multichannel application. The conversion result can clock out simultaneously through 4-wire mode for faster throughput or through 1-wire serial mode when slower throughput is allowed. The ADAQ4381-4 is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces using the separate logic supply. The ADAQ4381-4 is specified to operate over a temperature range of −40°C to +105°C. Table 1. µModule Data Acquisition Solutions

analog.com Rev. A | 2 of 45

REVISION HISTORY

1/2025—Rev. 0 to Rev. A 10/2024—Revision 0: Initial Version

Figure 1. Precision Current and Voltage Sensing for Servo Motors Control Using ADAQ4381-4

fSAMPLE = 4 MSPS, fully differential input configuration, full power mode, TA = 25°C , no oversampling, unless otherwise noted. Table 2. Electrical Specifications

Table 2. Electrical Specifications (Continued)

2 Limit the absolute differential input range, VIN, to 95% of full scale to allow enough footroom for the ADC driver with VS = 0 V to achieve specified performance.

analog.com Rev. A | 7 of 45 3 All AC specifications expressed in decibels are referred to full-scale input range (FSR) and are tested with an input signal of 0.5 dB below full scale, unless otherwise specified. 4 Hysteresis in output voltage is created by package stress that differs depending on whether the IC is previously at a higher or lower temperature. Output voltage is always measured at 25°C, but the IC is cycled to the hot or cold temperature limit before successive measurements. Hysteresis measures the maximum output change for the averages of three hot or cold temperature cycles. For instruments that are stored at well controlled temperatures (within 20°C or 30°C degrees of operational temperature), it is usually not a dominant error source. Typical hysteresis is the worst-case of 25°C to cold to 25°C or 25°C to hot to 25°C, preconditioned by one thermal cycle. 5 Maximum operating supply voltage, VS (VS+ − VS−) should not exceed 10 V. 6 The ADAQ4381-4 is rated for performance over extended industrial temperature range, TCASE = −40°C to +105°C.

Table 3. Digital Interface Timing

Table 4. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. junction-to-case thermal resistance. Table 5. Thermal Resistance

1 Test Condition 1: Thermal impedance simulated values are based on use of a

ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 6. ADAQ4381-4, 81-Ball CSP_BGA damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 9. Pin Configuration Table 7. Pin Function Descriptions A2 INC1+ AI Channel C Positive Input to 1.62 kΩ Gain Resistor Network. A3 INC1− AI Channel C Negative Input to 1.62 kΩ Gain Resistor Network. A4 IND2+ AI Channel D Positive Input to 2.70 kΩ Gain Resistor Network. A5 IND2− AI Channel D Negative Input to 2.70 kΩ Gain Resistor Network. A6 IND1+ AI Channel D Positive Input to 1.62 kΩ Gain Resistor Network. A7 IND1− AI Channel D Negative Input to 1.62 kΩ Gain Resistor Network. B2 OUTC− AO2 ADC Driver Negative Output for Channel C. B3 OUTC+ AO2 ADC Driver Positive Output for Channel C. B4 SJD+ AI ADC Driver Positive Input Summing Node for Channel D. B5 SJD− AI ADC Driver Negative Input Summing Node for Channel D. B6 OUTD− AO2 ADC Driver Negative Output for Channel D. B7 OUTD+ AO2 ADC Driver Positive Output for Channel D. B9 SDOD/ALERT DO Serial Data Output D/ALERT. This pin functions as a serial data output to or alert indication output. SDOD. This pin functions as a serial data output pin to access the conversion results. C1 INC2− AI Channel C Negative Input to 2.70 kΩ Gain Resistor Network. C2 SJC− AI ADC Driver Negative Input Summing Node for Channel C. internally. Additional decoupling capacitors may not be necessary. C6 EN_LDO P LDO enable. Connect to IN_LDO or VS+ to enable the internal LDO. Connect to GND if otherwise.

Table 7. Pin Function Descriptions (Continued) D1 INC2+ AI Channel C Positive Input to 2.70 kΩ Gain Resistor Network. D2 SJC+ AI ADC Driver Positive Input Summing Node for Channel C. D6, D7 OUT_LDO P Integrated LDO Output Voltage. The voltage at this pin is 3.45 V typical. D9 SCLK DI Serial Clock Input. This serial clock input is for data transfers to and from the ADC. E2 PD_FDA P Active low. Connect this pin to GND to power down (disable) the ADC Drivers. Connect VS+ for normal operation. E3 MODE_FDA P Power Mode for ADC Drivers. Connect to VS+ for full power mode. Connect to GND to enter low power mode. E6, F5, F6, G7 DNC N/A3 Do Not Connect. Leave these pins floating/unconnected. E9 SDI DI Serial Data Input. This input provides the data written to the on-chip control registers. F1 INB2+ AI Channel B Positive Input to 2.70 kΩ Gain Resistor Network. F2 SJB+ AI ADC Driver Positive Input Summing Node for Channel B. F7 REFIN P Internal Reference Supply Voltage. Connect to VS+ for normal operation. This pin is decoupled to ground internally. Additional decoupling capacitors may not be necessary. G1 INB2− AI Channel B Negative Input to 2.70 kΩ Gain Resistor Network. G2 SJB− AI ADC Driver Negative Input Summing Node for Channel B. G6 REFSENSE AO2 Reference Output Sense pin. leave this pin floating and unconnected. Capacitive load connected to this pin must not exceed 1 μF to ensure system stability. H2 OUTB− AO2 ADC Driver Negative Output for Channel B. H3 OUTB+ AO2 ADC Driver Positive Output for Channel B. H4 SJA+ AI ADC Driver Positive Input Summing Node for Channel A. H5 SJA− AI ADC Driver Negative Input Summing Node for Channel A. H6 OUTA− AO2 ADC Driver Negative Output for Channel A. H7 OUTA+ AO2 ADC Driver Positive Output for Channel A. ADAQ4381-4 and framing the serial data transfer. J2 INB1+ AI Channel B Positive Input to 1.62 kΩ Gain Resistor Network. J3 INB1− AI Channel B Negative Input to 1.62 kΩ Gain Resistor Network. J4 INA2+ AI Channel A Positive Input to 2.70 kΩ Gain Resistor Network. J5 INA2− AI Channel A Negative Input to 2.70 kΩ Gain Resistor Network. J6 INA1+ AI Channel A Positive Input to 1.62 kΩ Gain Resistor Network. J7 INA1− AI Channel A Negative Input to 1.62 kΩ Gain Resistor Network. 1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output. 2 Analog output pins are for voltage monitoring/measurement, and setting the gain of ADAQ4381-4 only. These pins must not be driven externally.

analog.com Rev. A | 20 of 45 Differential Voltage Differential voltage is the difference between two node voltages. For example, the differential input voltage (or equivalently, input differential mode voltage) is defined as: V IN , dm = V AI N A + − V AI N A − (1) where VAINA+ and VAINA− refer to the voltages at the AINA+ and AINA− terminals with respect to a common reference. Common-Mode Voltage (CMV) Common-mode voltage is the average of two node voltages. The input common-mode voltage is defined as: V I N , c m = V AI N A + + V AI N A − / 2 (2) Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition occurs at a level ½ LSB above analog ground. Offset error is the difference between the ideal mid-scale input voltage (0 V), and the actual voltage producing the mid-scale output code. Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of 1°C and the full-scale code range. Offset error drift is expressed in parts per million per degree Celsius (ppm/°C) as follows: Offset Error Drift pp m / ° C = 10 6 × Offset Error _ T M A X − Offset Error _ T MI N / T M A X − T MI N (3) where: TMAX = 105°C. TMIN = −40°C. Gain Error The first transition (from 100…000 to 100…001) must occur at a level ½ LSB above nominal negative full scale. The last transition (from 011…110 to 011…111) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain error is expressed as a percentage as follows: Gain Error (%) = 100 × ( PF S − NF S ) AC TU A L _ C ODE − ( PFS −NFS ) IDEAL _ CODE ) / ( PF S − NF S I D E AL _ C OD E (4) where: PFS is positive full scale. NFS is negative full scale. Gain Error Drift The gain error drift is the ratio of the gain error change due to a temperature change of 1°C and the full-scale range. Gain error drift is expressed in parts per million per degree Celsius (ppm/°C) as follows: Gain Error Drift p pm / ° C = 10 6 × Gain Error _ T M A X − Gain Error _ T MI N / T M A X − T MI N (5) where: TMAX = 105°C. TMIN = −40°C. Temperature Coefficient (TCVOUT) The temperature coefficient relates the change in the output voltage to the change in the ambient temperature of the device, as normalized by the output voltage at 25°C. This parameter is speci- fied using box method. TC V O U T = max V OU T T 1 , T 2 , T 3 − mi n V O U T T 1 , T 2 , T 3 V OU T T 2 × T 3 − T 1 × 10 6 (6) where: TCVOUT is expressed in ppm/°C. VOUT(TX) is the output voltage at temperature TX. T1 = −40°C. T2 = +25°C. T3 = +105°C.

analog.com Rev. A | 21 of 45 Long-Term Drift (ΔVOUT_LTD) Long-term drift refers to the shift in the output voltage vs. time. This is expressed as a difference in ppm from the nominal output. ∆ V OU T _ L TD = V OU T t 1 − V OU T t 0 V O U T t 0 × 10 6 (7) where: ΔVOUT_LTD is expressed in ppm. VOUT(t0) is the output voltage at the starting time of the measurement. VOUT(t1) is the output voltage at the end time of the measurement. Thermal Hysteresis (ΔVOUT_HYS) Thermal hysteresis represents the change in the output voltage after the device is exposed to a specified temperature cycle. This is expressed as a difference in ppm from the nominal output. ∆ V OU T _ HYS = V O U T 1_ 25° C − V O U T 2 _25° C V OU T 1 _25 ° C × 10 6 (8) where: ΔVOUT_HYS is expressed in ppm. VOUT1_25°C is the output voltage at 25°C. VOUT2_25°C is the output voltage after temperature cycling. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and DC. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding DC. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. ENOB is related to SINAD as follows: E NO B = S IN AD d B − 1 . 76 6 . 02 (9) where ENOB is expressed in bits. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in μModule output at the frequency, f, to the power of a 100 mV p-p sine wave applied to the input common-mode voltage of frequency, f. CMRR dB = 10log P μMo du l e _ I N / P μMo du l e _ OU T (10) where: PμModule_IN is the common-mode power at the frequency, f, applied to the inputs. PμModule_OUT is the power at the frequency, f, in the μModule output. Power-Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the μModule output at the frequency, f, to the power of a 500 mV p-p sine wave applied to the VS+, REFIN, and IN_LDO supply voltage centered at 5 V of frequency, f. PSRR dB = 10 log P μ Mo du l e _ I N / P μM od u l e _ OU T (11) where: PμModule_IN is the power at the frequency, f, at the VS+, REFIN, and IN_LDO pins. PμModule_OUT is the power at the frequency, f, at the μModule output. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the falling edge of the input and when the input signal is held for a conversion. Aperture Jitter Aperture jitter is the variation in aperture delay.

Figure 46. ADAQ4381-4 μModule Simplified Block Diagram signal chain that uses a simultaneous sampling SAR architecture. and minimize temperature dependent error sources. package. Any external capacitors are not necessary.

is at optimum performance with slightly higher power consumption. In low power mode, the ADAQ4381-4 consumes 20% less power. ADAQ4381-4 is highly dependent on the gain of the ADC drivers. must consider input common-mode voltage for proper operation. G = 0.3 and G = 1, respectively. Figure 56. Input Common-Mode Voltage vs. ADC Driver Output, Gain = 0.3, Figure 57. Input Common-Mode Voltage vs. ADC Driver Output, Gain = 1.0, Figure 58. ADAQ4381-4 Configured at Fully Differential Inputs

2 R G + R F

Figure 59. ADAQ4381-4 Configured at Single-Ended Inputs voltage across the RG input resistor.

controlling the operational mode of the device. aging and rolling averaging. OS_MODE bit and OSR bits in the Configuration1 Register. device. The sample data is cleared after the process is completed. using the oversampling bits, OSR. Register. For more details, see the Resolution Boost section. Table 10. Normal Average Oversampling Overview, G = 1

110 Invalid N/A1 N/A1 N/A1

111 Invalid N/A1 N/A1 N/A1

Figure 66. Normal Average Oversampling Operation

using the oversampling bits, OSR (see Table 11). average oversampling ratios without waiting for the FIFO to fill. the FIFO, added together and the result is divided by n. Table 11. Rolling Average Oversampling Overview, G = 1 Figure 67. Rolling Average Oversampling Mode Operation

and resets the internal oscillator block, see Figure 70. Figure 70. Software Reset Operation hard reset to reset the ADAQ4381-4 registers to the default status.

analog.com Rev. A | 37 of 45 CRC The ADAQ4381-4 has CRC checksum modes that can be used to improve interface robustness by detecting errors in data trans- missions. The CRC feature is independently selectable for SPI interface reads and SPI interface writes. For example, enable the CRC function for SPI writes to prevent unexpected changes to the device configuration but not enable it on SPI reads to maintain a higher throughput rate. The CRC feature is controlled by program- ming the CRC_W bit and CRC_R bit in the Configuration1 Register. CRC Read If enabled, a CRC consisting of an 8-bit word is appended to the conversion result or register reads. The CRC is calculated on the conversion result for ADC A, ADC B, ADC C, and ADC D and output on SDOA. A CRC is also calculated and appended to register read outputs. The CRC read function can be used in 1-wire SPI mode, 2-wire SPI mode, 4-wire SPI mode, and resolution boost mode. CRC Write To enable the CRC write function, the CRC_W bit in the Configuration1 Register register must be set to 1. To set the CRC_W bit to 1 to enable the CRC feature, a valid CRC must be appended to the request frame. After the CRC feature is enabled, all register write requests are ignored unless they are accompanied by a valid CRC command. A valid CRC is required to both enable and disable the CRC write feature. CRC Polynomial For CRC checksum calculations, the polynomial x8 + x2 + x + 1 is always used. To generate the checksum, the 14-bit data conversion result of the 4-channels are combined to produce a 56-bit data stream. The eight MSBs of the 56-bit data are inverted and the data is appended by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned such that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned such that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial, which is the 8-bit checksum. For example, ADAQ4381-4 polynomial is 100000111. Let the origi- nal data of 4-channels be 0xAAAA, 0x5555, 0xAAAA, and 0x5555. The eight MSBs of the data are inverted. The data is then append- ed to include eight 0s on right. In the final XOR operation, the reduced data is less than the polynomial. Therefore, the remainder is the CRC for the assumed data. For more details on ADAQ4381-4 CRC operation, see Table 13 and Figure 78.

Table 13. Example CRC Calculation for 4-Channel, 16-Bit Data Figure 78. CRC Operation

available on the ADAQ4381-4. considered a no operation and the data transmitted in the next SPI frame are the conversion results. Table 14. Register Description Table 15. Addressing Register Format Table 16. Bit Descriptions for Addressing Registers D15 WR When a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR if it is a valid address. Alternatively, when a 0 is written, the next data sent out on the SDO pin is a read from the designated register if it is a valid address. D14 to D12 REGADDR When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 14. during the next interface access. in the conversion results being readback.

Table 17. Bit Descriptions for Configuration1 Register frame is ignored. If the bit is set to 1, it requires a CRC to clear it to 0.

Table 18. Bit Descriptions for Configuration2 Register 00: 2-wire. Conversion Data are output on both SDOA and SDOB. 01: 1-wire. Conversion Data are output on SDOA only. 10: 4-wire. Conversion data are output on SDOA, SDOB, SDOC, and SDOD/ALERT. 11: 1-wire. Conversion Data are output on SDOA only. indication register and flushes any oversampling stored variables or active state machine.

Table 19. Bit Descriptions for Alert Indication Register set until the register is read. clear this bit and restart the device setup. the value set in the alert high threshold register. This fault bit is sticky and remains set until the register is read. the value set in the alert low threshold register. This fault bit is sticky and remains set until the register is read. the value set in the alert high threshold register. This fault bit is sticky and remains set until the register is read. the value set in the alert low threshold register. This fault bit is sticky and remains set until the register is read. the value set in the alert high threshold register. This fault bit is sticky and remains set until the register is read. the value set in the alert low threshold register. This fault bit is sticky and remains set until the register is read.

Table 19. Bit Descriptions for Alert Indication Register (Continued) the value set in the alert high threshold register. This fault bit is sticky and remains set until the register is read. the value set in the alert low threshold register. This fault bit is sticky and remains set until the register is read. Table 20. Bit Descriptions for Alert Low Threshold Register Table 21. Bit Descriptions for Alert High Threshold Register

©2024-2025 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. A | 45 of 45 Package Drawing (Option)Package Type Package Description BC-81-7 CSP_BGA 81-Ball Chip-Scale Package Ball Grid Array For the latest package outline information and land patterns (footprints), go to Package Index. Updated: October 28, 2024 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADAQ4381-4BBCZ −40°C to +105°C CHIP SCALE BGA TRAY, 348 BC-81-7 1 Z = RoHS-Compliant Part. EVALUATION BOARDS Model1 Description EV-ADAQ4381-4FMCZ Evaluation Board 1 Z = RoHS-Compliant Part.