ADAQ4216 (Rev.C)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 65
Technical content
16-Bit, 2MSPS, μModule Data-Acquisition Solution Rev. C DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
►Highly performance ►Throughput: 2MSPS, no latency ►INL: ±3ppm maximum from −40°C to 105°C ►Total system dynamic range: 123dB typical ►SNR: 97.5dBFS typical, THD: −122dBc typical ►Offset error drift: +5.05μV/°C maximum ►Gain error drift: +1.17ppm/°C maximum ►Ease of use features reduce system complexity ►Second-order, 270kHz anti-aliasing filter ►High-Z PGIA gain options: 1/3, 5/9, 20/9, 20/3 ►Flexible external reference voltage: 4.096V or 5V ►Differential input voltage ranges, ±REFIN/Gain: ±15V, ±9V, ±2.25V, ±0.75V ►Wide input common-mode voltage range: −8V to +10V ►Low input bias current: ±20pA typical ►High density solution reduces system footprint ►14mm x 9mm, 0.8mm pitch, 178-ball CSP BGA ►4× footprint reduction vs. equivalent discrete solution ►On-board reference buffer with an internal VCM generation ►Total power dissipation: 445mW typical at 2MSPS ►Flexi-SPI digital interface ►1, 2, or 4 SDO lanes allows slower SCK ►Echo clock mode simplifies use of digital isolator ►Compatible with 1.2V to 1.8V logic ►PGIA gain control (A0, A1) interface ►Extended sample resolution to 30-bits ►Overrange and synchronization bits
APPLICATIONS
►Automatic test equipment ►Machine automation ►Process controls ►Medical and industrial instrumentation ►Digital control loops FUNCTIONAL BLOCK DIAGRAM Figure 1. ADAQ4216 Functional Block Diagram
analog.com Rev. C | 2 of 65 Sample Conversion Timing and Data
REVISION HISTORY
2/2026—Rev. B to Rev. C 7/2025—Rev. A to Rev. B
analog.com Rev. C | 3 of 65 5/2025—Rev. 0 to Rev. A 1/2025—Revision 0: Initial Version
analog.com Rev. C | 4 of 65 The ADAQ4216 is a µModule® precision data-acquisition (DAQ) signal chain solution that reduces the development cycle of a preci- sion measurement system by transferring the signal-chain design challenge of component selection, optimization, and layout from the designer to the device. With a guaranteed maximum ±3ppm INL and no missing codes at 16 bits, the ADAQ4216 achieves unparalleled precision from −40°C to +105°C. Using system-in-package (SIP) technology, the ADAQ4216 com- bines the common signal processing blocks required in a data-ac- quisition solution in a small footprint, 14mm × 9mm, 0.8mm pitch, 178-ball CSP_BGA package. The ADAQ4216 integrates the following: ►A low-noise, high-bandwidth programmable gain instrumentation amplifier (PGIA). ►A second-order anti-aliasing filter. ►A low-noise, low-distortion, high-bandwidth analog‐ to‐ digital con- verter (ADC) driver. ►A high precision 16-bit, 2MSPS successive approximation regis- ter (SAR) ADC. ►A 1.8V low dropout (LDO) regulator. ►Performance critical passives. The ADAQ4216 incorporates the critical passive components with superior matching and drift characteristics using Analog Devices, Inc., iPassives® technology to minimize temperature-dependent error sources and to offer optimized performance. Integrating the critical power supply and reference bypass capacitors reduce sen- sitivity to the system level board layout. Reducing the solution footprint enables addition of more functions within the system and hence the smaller form factor instruments without sacrificing performance. The system integration solves many design challenges while the µModule still provides the flexibility of a configurable PGIA, which allows gain or attenuation and supporting the acquisition of differ- ential or single-ended input signal. The fast settling of the PGIA and ADC driver stage and no latency of the SAR ADC provide a unique solution for high channel count, multiplexed signal chain architectures, and control loop applications. The digital features include Flexi-SPI serial-peripheral interface (SPI), which allow data access by multiple SPI modes as well as offset correction, gain adjustment, and averaging. The digital features reduces the burden on the host processor. A wide-data clocking window, multiple SDO lanes, and optional DDR data clock- ing reduce the serial clock frequency while operating at full speed of 2MSPS and make it easier to isolate the DAQ solution, which reduces power dissipation and EMI. The echo clock mode and host clock mode of the ADAQ4216 relax the timing requirements and simplify the use of digital isolators. The Flexi-SPI serial-user interface is compatible with 1.2V to 1.8V using a separate VIO supply. The ADAQ4216 operation is specified from −40°C to +105°C.
specifications TMIN to TMAX, unless otherwise noted. Table 1. Specifications
Table 1. Specifications (Continued)
2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2MSPS. 3 These specification are not production tested but are supported by characterization data during initial product release. 4 Tested at 95% of full scale input. 5 See the low frequency noise plot in Figure 63. 1/f noise is canceled internally by auto-zeroing. Noise spectral density is substantially uniform from DC to fS/2. 6 Drop-out voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. 7 Start-up time is defined as the time between the rising edge of EN_LDO to VDD_1.8V being at 90% of its nominal value. 8 When VIO < 1.4 V, Bit IO2X must be set to 1. For more details, see the Output Driver Register section.
specifications are TMIN to TMAX, unless otherwise noted. For the timing voltage levels, see Figure 2. For VIO < 1.4V, Bit IO2X must be set to 1. Table 2. Digital Timing Interface guaranteed by characterization and design. 2 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2MSPS. Figure 2. Voltage Levels for Timing Table 3. Register Read/Write Timing
Figure 10. Host-Clock Mode Timing, DDR, 1-Lane
Table 8. Absolute Maximum Ratings 1 The input pins have clamp diodes connected to the power supply pins. ing conditions for extended periods may affect product reliability. enclosure. θJC is the junction-to-case thermal resistance. Table 9. Thermal Resistance sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 10. ADAQ4216, 178-Ball CSP_BGA devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.
Figure 11. Pin Configuration (Top View) Table 11. Pin Function Descriptions A5 to A6, J3 to J4 VDDH P PGIA Positive Power Supply. This pin has a 0.1μF bypass capacitor inside the package. to draw a larger current from the VDDH and VSSH supply. C3 to C4, G3 to G4 VSSH P PGIA Negative Power Supply. This pin has a 0.1μF bypass capacitor inside the package. PGIA to draw a larger current from the VDDH and VSSH supply. reference buffer and has a 2μF bypass capacitor at the output of the buffer.
Table 11. Pin Function Descriptions (Continued) D16 RSTB DI Reset Input (Active Low). Asynchronous ADC reset. output driver register must be set to 1. E3 A1 DI PGIA Gain-Control Logic Input 1. E4 A0 DI PGIA Gain-Control Logic Input 0. to GND with at least 2.2μF (0402, X5R) ceramic capacitor. E9 OUTP AO Positive FDA Output. Connect to ADCP pin. E10 ADCP AI Positive ADC Input. Connect to OUTP pin. IOGND P VIO Ground. Connect to the same ground plane as all GND pins. F9 OUTN AO Negative FDA Output. Connect to ADCN pin. F10 ADCN AI Negative ADC Input. Connect to OUTN pin. F16 SDO3 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. F17 SDO1 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. G7, G11 to G12, H11 to H12DNC Do Not Connect. G16 SDO2 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. G17 SDO0 DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. connect the PDB_FDA pin to VDD_FDA logic high supply. sourced by the internal oscillator. GND with at least 2.2μF (0402, X5R) ceramic capacitor. Connect to GND for fewer power supply rails. NIC Not Internally Connected. These pins are not connected internally. J16 to J17, K16 to K17 DNC Do Not Connect. These pins are internally connected to digital output drivers in high-Z mode. L7 EN_LDO DI Enable LDO pin. For automatic start-up, connect EN_LDO to VLDO. L14 CSB DI Chip Select Input (Active Low). L15 SDI DI Serial Data Input. 1 AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output.
analog.com Rev. C | 30 of 65 INTEGRAL NONLINEARITY ERROR (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½LSB before the first code transition. Positive full scale is defined as a level 1½LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 91). DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. OFFSET ERROR Offset error is the difference between the ideal midscale voltage, 0V, and the actual voltage producing the midscale output code, 0LSB. GAIN ERROR ½LSB above nominal negative full scale. The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. LEAST SIGNIFICANT BIT (LSB) The smallest increment that can be represented by a converter. For a fully differential input μModule with N bits of resolution, the LSB expressed in volts is: LSB (V) = (VREF × 2) / 2N × AFE Gain (1) SPURIOUS-FREE DYNAMIC RANGE (SFDR) SFDR is the difference, in decibel relative to the carrier (dBc), be- tween the rms amplitude of the input signal and the peak spurious signal. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB − 1.76)/6.02. ENOB is expressed in bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of the input signal and is expressed in decibel relative to the carrier (dBc). DYNAMIC RANGE Dynamic range is the rms voltage of a full-scale sine wave to the total rms voltage of the noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60dBFS so that it includes all noise sources and DNL artifacts. TOTAL SYSTEM DYNAMIC RANGE The ratio of the root-mean-square (RMS) value of the full scale input at Gain = 1/3V/V to the input referred RMS noise measured when input pins are shorted together at Gain = 20/3V/V. The value is expressed in decibels. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and DC. The value for SNR is expressed in decibel relative to full scale (dBFS). SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) RATIO SINAD is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding DC. The value of SINAD is expressed in decibel relative to full scale (dBFS). TRANSITION NOISE Transition noise is the noise generated when the μModule inputs are grounded or are connected to precise voltage source. Transition noise is calculated as: Transition Noise (LSB) = RTI RMS Noise / LSB (V)(2) APERTURE DELAY Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. TRANSIENT RESPONSE Transient response is the time required for the μModule to acquire a full-scale input step to ±1LSB accuracy. COMMON-MODE REJECTION RATIO (CMRR) CMRR is the ratio of the power in the μModule output at the frequency, f, to the power of a 4.5Vp-p sine wave applied to the input common-mode voltage of frequency, f. CMRR (dB) = 10× log(PμModule_IN/PμModule_OUT) (3) where: PμModule_IN is the common-mode power at the frequency, f, applied to the inputs. PμModule_OUT is the power at the frequency, f, in the μModule output. POWER-SUPPLY REJECTION RATIO (PSRR) PSRR is the ratio of the power in the μModule output at the frequency, f, to the power of a 200mVp-p sine wave applied to the
analog.com Rev. C | 31 of 65 μModule supply (VDD_5V, VDD_FDA, VSS_FDA, VDDH, VSSH) of frequency, f. PSRR (dB) = 10 × log(PSUPPLY_IN/PμModule_OUT) (4) where: PSUPPLY_IN is the power at the frequency, f, at the supply pin. PμModule_OUT is the power at the frequency, f, in the μModule output.
Figure 90. ADAQ4216 Functional Block Diagram eases level shifting requirements as well. ADAQ4216 dissipates only 445mW at 2MSPS.
- The differential output data is in twos complement format. Table
analog.com Rev. C | 33 of 65 Figure 91. ADC Ideal Transfer Function for the Differential Output Codes Table 12. Input Voltage to Output Code Mapping
Description
Digital Output Code (Twos Complement, Hex) FSR − 1LSB (32767 × VREF)/(G × 32768) 0x7FFF Midscale + 1LSBVREF/(G × 32768) 0x0001 Midscale 0V 0x0000 Midscale − 1LSB −VREF/(G × 32768) 0xFFFF −FSR + 1LSB −(32767 × VREF)/(G × 32768) 0x8001 −FSR − VREF/G 0x8000 SIGNAL CHAIN OPERATION The ADAQ4216 operates in two phases, the acquisition and the conversion phase. In the acquisition phase, the voltage present on each input pin (INP and INN) of PGIA is sampled independently. Issuing a rising edge pulse on the CNV pin initiates a conversion. The rising edge pulse on the CNV pin also asserts the BUSY signal to indicate a conversion in progress. At the end of the conversion, the BUSY signal is deasserted. The conversion result is a 16-bit code representing the input voltage difference and an 8-bit code representing the input common-mode voltage. Depending on the device configuration, this conversion result can be processed digitally and latched into the internal output register. The internal ADC acquisition circuit on each input pin is also precharged to the previous sample voltage, which minimizes the kick-back charge to the input driver stage (PGIA). The host processor retrieves the output code by the SDO pins that are internally connected to the internal output register. DIGITAL SAMPLE PROCESSING FEATURES The ADAQ4216 supports several digital and data processing fea- tures that can be applied to the signal samples. These features are enabled and disabled by the control registers of the ADAQ4216. Full-Scale Saturation The conversion results saturate digitally (before any post-process- ing) when either or both inputs exceed the analog limits specified herein. After applying offset and gain scaling, the results are re- duced to 16-bit representation (saturating at maximum 0x7FFF and minimum 0x8000). A user must be avoid unintentional saturation, especially when applying digital offset and/or gain scaling. For more details on the use of these features, see the Digital Offset Adjust and Digital Gain sections. Common-Mode Output When the host controller writes 0x1 to the OUT_DATA_MD bit field of the modes register (for more details, see the Modes Register section), an 8-bit code representing the input common-mode volt- age is appended to the 16-bit code representing the input voltage difference. The LSB size of the 8-bit code is VREF/256. The 8-bit code saturates at 0 and 255 when the common mode input voltage is 0V and VREF, respectively. The 8-bit code is not affected by digital offset and gain scaling, which is applied only to the code representing the input voltage difference. Block Averaging The ADAQ4216 provides a block averaging filter (SINC1) with programmable block length 2N, N = 1, 2, 3, …, 16. The filter is reset after processing each block of 2N samples. The filter is enabled by writing 0x3 to the OUT_DATA_MD bit field of the modes register (for more details, see the Modes Register section) as well as a value (1 ≤ N ≤ 16) to the AVG_VAL bit field in the averaging mode register (for more details, see the Averaging Mode Register section). In this configuration, the output sample word is 32 bits. The 30 most significant bits (MSBs) represent the numerical value of the 16-bit codes averaged in blocks of 2N samples. The automatic scaling allows the 16MSBs of the 30-bit code to be equal to the 16-bit codes when averaging blocks of constant values. The 31st bit (OR) is an overrange warning bit that is high when one or more samples in the block are subject to saturation. The 32nd bit (SYNC) is high once every 2N conversion cycles to indicate when the average values are updated at the end of each block of samples. For more details, see the Digital Sample Processing Features section. The effective data rate in averaging mode is fCNV/2N. The reset value of N in the AVG_VAL bit field is 0x00 (no averaging). Figure 115 shows an example timing diagram in averaging mode. Figure 92 shows the frequency response of the filter for an N = 1, 2, 3, 4,
analog.com Rev. C | 42 of 65 capacitors are not close to the ADC, add an external capacitors next to the ADC. The minimum rise time for all supplies is 100µs. Power Consumption States During a conversion, the power consumption of the ADAQ4216 is at its highest. When the conversion is complete, it enters a standby state and much of the internal circuitry is powered down, and current consumption drops to less than 20% relative to the conversion state. To ensure full accuracy, some circuitry, including the reference buffer, remains powered on during the standby state. The device can be placed into a lower power shutdown state during periods when the convert clock is idle by writing 0x3 to the OPERATING_MODES bit field of the device configuration register (for more details, see the Device Configuration Register section). The default value of this bit field is [00] for normal operating mode. In the shutdown state, the current consumption typically drops to less than 10µA. Shutdown Mode When the ADC enters shutdown mode, the internal reference buffer is disabled and a 500Ω switch connects REFIN to the output of the internal reference buffer, which keeps the 2µF capacitor on the output of the internal buffer charged up to allow fast recovery when the ADC exits shutdown mode. Because of this keep-alive switch, there is some charge injected to the REFIN pin when the ADC enters shutdown mode (400pC) and exits shutdown mode (5pC). When leaving shutdown mode, the output of the internal buffer is accurate after 30μs.
output data is clocked out on up to 4 SDO lanes (see Figure 108). Figure 108. ADAQ4216 Multilane SPI clock output for these clocking modes. of the user registers of the ADAQ4216. maximum frequency of the CNV clock is 2MSPS. ►SCK (input). Serial data clock sourced by the host controller. ►SDO0 through SDO3 (outputs). Data lanes to the host controller. Table 13. BUSY_SCKOUT Pin Behavior vs. Clocking Mode signal from the internal oscillator. sent by the host controller over the SPI, as shown in Figure 5. CS low for the entire transaction.
- Perform a readback from a dummy register address 0x3FFF, to
enter the register configuration mode.
- Readback from or write to the required user register addresses.
- Exit the register configuration mode by writing 0x01 to register
register updates to take effect.
transactions while the ADAQ4216 is in register configuration mode. starting at a given address. Figure 109. Stream Mode Bulk Register Readback Operation
into the output shift register.
- The quiet zone immediately before the rising edge of CNV is
then sample N is overwritten with sample N+1. Figure 110. Example Timing for Data Transfer Zones
1-lane mode. Table 14 lists the active SDO lanes for 2-lane mode. Clocking Requirements and Timing section. shown in the Data Clocking Requirements and Timing section. Table 14. ADAQ4216 Supported Data Output Modes
1 SDO0 SPI SDR only 16, 24 or 32
2 SDO0, SDO1 SPI SDR only 16, 24 or 32
4 SDO0, SDO1, SDO2, SDO3SPI SDR only 16, 24 or 32
analog.com Rev. C | 54 of 65 The following layout guidelines are recommended to achieve maxi- mum performance of the ADAQ4216: ►The ADAQ4216 contains internal 1μF bypass capacitors for VDD_5V and VDD_1.8V, and VIO contains an internal 0.2μF capacitor, so no external bypass capacitors are required. This saves board space, bill of materials count, and reduces layout sensitivity. ►It is recommended to have all the analog signals flow in from the left side of the ADAQ4216 and all the digital signals to flow in and out from the right side of the ADAQ4216 because this helps isolate analog signals from digital signals. ►Use a solid ground plane under the ADAQ4216 and connect all the analog ground (GND) pins and digital ground (IOGND) pins to the shared ground plane to avoid formation of ground loops. ►Traces routed to the REFIN pin must be isolated and shielded from other signals. Avoid routing signals beneath the reference trace (REFIN). If a noise reduction filter is placed between the output of the reference (or buffer) and the chosen reference input, it must be placed as close as possible to the ADAQ4216.
Table 16. ADAQ4216 Register Summary
Interface configuration settings. Table 17. Bit Descriptions for INTERFACE_CONFIG_A 0: Address accessed is decremented by one for each data byte when streaming. Additional interface configuration settings. Table 18. Bit Descriptions for INTERFACE_CONFIG_B 0: Streaming mode is enabled. The address decrements as successive data bytes are received. 1: Single instruction mode is enabled.
Table 19. Bit Descriptions for DEVICE_CONFIG uniquely identify a given product. Table 20. Bit Descriptions for CHIP_TYPE Table 21. Bit Descriptions for PRODUCT_ID_L High byte of the product ID.
Table 22. Bit Descriptions for PRODUCT_ID_H Identifies product variations and device revisions. Table 23. Bit Descriptions for CHIP_GRADE [7:3] GRADE This is the device performance grade. This register can be used to test writes and reads. Table 24. Bit Descriptions for SCRATCH_PAD Table 25. Bit Descriptions for SPI_REVISION
Table 26. Bit Descriptions for VENDOR_L Table 27. Bit Descriptions for VENDOR_H Defines the length of the loop when streaming data. Table 28. Bit Descriptions for STREAM_MODE Status bits are set to 1 to indicate an active condition. The status bits can be cleared by writing a 1 to the corresponding bit location.
Table 29. Bit Descriptions for INTERFACE_STATUS_A 4 CLOCK_COUNT_ERR 0 = No error. 1 = Incorrect Number of Clocks Detected in a Transaction. Write 1 to clear. Table 30. Bit Descriptions for EXIT_CFG_MD Table 31. Bit Descriptions for AVG 0x00 = No averaging. Use only 0x01 through 0x10 for averaging mode. 0x11 through 0x1F = invalid.
Table 32. Bit Descriptions for OFFSET_LB [7:0] USER_OFFSET[7:0] 16-Bit Offset. Twos complement (signed).
1 LS B =
Table 33. Bit Descriptions for OFFSET_HB [7:0] USER_OFFSET[15:8] 16-Bit Offset. Twos complement (signed).
1 L SB =
Table 34. Bit Descriptions for GAIN_LB Table 35. Bit Descriptions for GAIN_HB
Table 36. Bit Descriptions for MODES 1 = DDR (only valid for echo clock mode and host clock mode). 000 = 16-bit differential data. 001 = 16-bit differential data + 8-bit common-mode data. 011 = 30-bit averaged differential data + OR bit + SYNC bit. 100 = 32-bit test data pattern (TEST_DATA_PAT). Table 37. Bit Descriptions for OSCILLATOR ADAQ4216 based on the data word size, number of active SDO lanes, and data rate mode (SDR or DDR). 00 = No divide (divide by 1). Table 38. Bit Descriptions for IO
Table 38. Bit Descriptions for IO (Continued) 1 = Double output driver strength. 0 = Normal output driver strength. Table 39. Bit Descriptions for TEST_PAT_BYTE0 Table 40. Bit Descriptions for TEST_PAT_BYTE1 Table 41. Bit Descriptions for TEST_PAT_BYTE2 Table 42. Bit Descriptions for TEST_PAT_BYTE3
Table 43. Bit Descriptions for DIG_DIAG Table 44. Bit Descriptions for DIG_ERR
12.80 REF
Figure 121. 178-Ball Chip-Scale Package, Ball Grid Array