ADAQ23875

ADAQ23875 (Rev.A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

analog.com Rev. A | 2 of 24

REVISION HISTORY

2/2026—Rev. 0 to Rev. A 11/2020—Revision 0: Initial Version

analog.com Rev. A | 3 of 24 VDD = 5 V ± 5%, VS+ = 5 V ± 5%, VS− = −1 V± 5%, VS− = 0 V(95% of VIN), VIO = 2.375 V to 2.625 V, REFBUF = 4.096 V, sampling frequency (fS) = 15 MSPS, gain = 2, and all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT IMPEDANCE, ZIN VIN = 4.096 V p-p Single-ended to differential configuration 825 Ω Differential configuration 1100 Ω Input Capacitance IN1+, IN1− 3.3 pF Differential Input Voltage Range, VIN1, 2 Gain = 2, VIN = 4.096 V p-p −2.048 +2.048 V THROUGHPUT Complete Cycle 66.6 ns Conversion Time 54 58 63 ns Acquisition Phase3 tCYC − 39 ns Throughput Rate4 0.02 15 MSPS Transient Response5 Full-scale step 52 ns DC ACCURACY Single-ended and differential configuration No Missing Codes 16 Bits Integral Linearity Error −1 ±0.6 +1 LSB6 Differential Linearity Error −1 ±0.25 +1 LSB Transition Noise 0.73 LSBRMS Gain Error −0.045 ±0.005 +0.045 %FS Gain Error Drift −1 ±0.05 +1 ppm/°C Offset Error −1.5 +1.5 mV Offset Error Drift −1.8 ±0.25 +1.8 ppm/°C Common Mode Rejection Ratio (CMRR), Input Referred ∆VICM/∆VOSDIFF 96 dB Power Supply Rejection Ratio (PSRR) Positive VDD = 4.75 V to 5.25 V 105 dB VS+ = 4.75 V to 5.25 V, VS− = −1 V 115 dB Negative VS+ = +5 V, VS− = −0.75 V to −1.25 V 103 dB 1/f Noise7 Bandwidth = 0.1 Hz to 10 Hz 9 µV p-p Input Current Noise f = 100 kHz 1 pA/√Hz AC ACCURACY8 Single-ended and differential configuration Dynamic Range Input frequency (fIN) = 1 kHz, −60 dB input 88 90 dB Total RMS Noise 91.6 µVRMS Input Voltage Noise Density 16.7 nV/√Hz Signal-to-Noise Ratio fIN = 1 kHz 87.5 89.5 dB fIN = 100 kHz 88.5 dB fIN = 400 kHz 88 dB fIN = 1 MHz 87.5 dB Signal-to-Noise + Distortion (SINAD)fIN = 1 kHz 87.3 89 dB fIN = 100 kHz 88 dB fIN = 400 kHz 87.5 dB fIN = 1 MHz 87 dB Total Harmonic Distortion (THD) fIN = 1 kHz −115 dB fIN = 100 kHz −111 dB fIN = 400 kHz −106 dB

Table 1. (Continued)

1 For gain = 2, limit the differential input range, VIN, to 95% to allow enough footroom for the ADC driver with VS− = 0 V to achieve the specified performance. 2 The differential input ranges, VIN, must be within the allowed input common-mode range as per Figure 31. VIN is dependent on the VS+ and VS− supply rails used. 3 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADAQ23875 running at a throughput rate of 15 MSPS. 4 fS = 15 MHz, and the REFBUF current (IREFBUF) varies linearly with throughput rate. 5 The transient response is the time required for the ADAQ23875 to acquire a full-scale input step to within ±1 LSB accuracy. Guaranteed by design, not subject to test. 6 The LSB unit means least significant bit. The weight of the LSB, referred to input, changes depending on the input voltage range. 7 See the 1/f noise plot in Figure 35. 9 Guaranteed by design, not subject to test. 10 When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN = 0 V. Refer to the Voltage Reference Input section for more information. 11 The VCMO voltage can be used for other circuitry. However, drive the voltage with a buffer to ensure the VCMO voltage remains stable as per the specified range. 12 With all digital inputs forced to VIO or GND, as required. 13 During the acquisition phase. 14 In two-lane mode, the VIO power dissipation is about 10 mW higher than one-lane mode. gain = 2, and all specifications TMIN to TMAX, unless otherwise noted. Table 2. Digital Interface Timing

ing conditions for extended periods may affect product reliability. Table 4. Thermal Resistance

1 Test Condition 1: thermal impedance simulated values are based on use of a

sensitive devices in an ESD protected area only. The human body model (HBM) is per ANSI/ESDA/JEDDEC JS-001. Table 5. ADAQ23875, 100-Ball CSP_BGA devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.

Figure 5. 100-Ball CSP_BGA Pin Configuration, Top View Table 6. Pin Function Descriptions A2, B2 IN1− AI Negative Input of the FDA Connected to a 550 Ω Resistor. A3, B3 IN1+ AI Positive Input of the FDA Connected to a 550 Ω Resistor. 2.2 μF (0402, X5R) ceramic capacitor to GND. disabled. Logic levels are determined by VIO. must be bypassed with an at least 2.2 μF (0402, X5R) ceramic capacitor to GND. an at least 2.2 μF (0402, X5R) ceramic capacitor to GND.

Table 6. Pin Function Descriptions (Continued) D6 VCMO AO FDA Output Common-Mode Voltage. The VCMO pin is nominally REFBUF/2. E10 CLK− DI LVDS Clock Input. The CLK− is an externally applied clock that serially shifts out the conversion result. capacitance. See the PCB Layout section. disabled to reduce power consumption. to power down the buffer and connect an external buffered reference to REFBUF. high, the device operates normally. Logic levels are determined by VIO. supply of μModule must be bypassed with an at least 2.2 μF (0402, X5R) ceramic capacitor to GND. conversion result. Logic levels are determined by VIO. disabled to reduce power consumption. disabled to reduce power consumption. disabled to reduce power consumption. DI, and DO pins to avoid undesired parasitic capacitance and impact on performance. See the Board Layout section.

analog.com Rev. A | 15 of 24 Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity (DNL) In an ideal µModule, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition occurs at a level ½ LSB above analog ground (62.5 µV for the gain = 2, ±2.048 V range). Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of 1°C and the full-scale code range (gain = 2, ±2.048 V range). This drift is expressed in parts per million per degree Celsius as follows: Offset Error Drift (ppm/°C) = 106 × (Offset Error_TMAX − Offset Error_TMIN)/(TMAX − TMIN) (1) where: TMAX = 85°C and TMIN = −40°C. Gain Error The first transition (from 100 … 000 to 100 …001) occurs at a level ½ LSB above nominal negative full scale (−4.0959375 V for gain = 2, ±2.048 V range) and the last transition (from 011 … 110 to 011 … 111) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.0958125 V for the gain = 2, ±2.048 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the ideal levels after the offset error is removed. This error is expressed in percentage as follow: G ai n _ E rr o r % = 100 × P FS − N FS AC TU AL _ C OD E − P FS − N FS I DE AL _ COD E / PF S − NF S I D E A L _ C ODE (2) where: PFS is positive full scale. NFS is negative full scale. GAIN ERROR DRIFT Gain error drift is the ratio of the gain error change due to a temperature change of 1°C and the full-scale range (gain = 2, ±2.048 V range). This drift is expressed in parts per million per degree Celsius as follows: Gain Error Drift (ppm/°C) = 106 × (Gain Error_TMAX – Gain Error_TMIN)/(TMAX − TMIN) (3) where: TMAX = 85°C and TMIN = −40°C. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. ENOB is related to SINAD and expressed in bits as follows: ENOB = (SINADdB − 1.76)/6.02 (4) Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. This range is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the µModule to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the µModule output at the frequency, f, to the power of a 1.3 V p-p sine wave applied to the input common-mode voltage of frequency, f. CMRR (dB) = 10log(PµModule_IN/PµModule_OUT) (5)

analog.com Rev. A | 16 of 24 where: PµModule_IN is the common-mode power at the frequency, f, applied to the inputs. PµModule_OUT is the power at the frequency, f, in the µModule output. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the µModule output at the frequency, f, to the power of a 500 mV p-p sine wave applied to the VDD and VS+ supply voltage centered at 5 V and 100 mV p-p for a VS− supply voltage centered at – 1 V of frequency, f. PSRR (dB) = 10 log(PµModule_IN/PµModule_OUT) (6) where: PµModule_IN is the power at the frequency, f, at each of the VDD, VS+ and VS− supply pins. PµModule_OUT is the power at the frequency, f, in the µModule output.

analog.com Rev. A | 20 of 24 The logic levels for both the PDB_AMP and PDB_ADC pins are determined by VS+ and VIO, respectively.

Figure 48. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]