ADADC84 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
ANALOG Fast, Complete DEVICES 12-Bit A/D Converters FEATURES FUNCTIONAL BLOCK DIAGRAM Performance are "AD ADCSA/AD ADGBS/ADSINO Complete 12-Bit A/D Converter with Reference and Clock ae ron abe 1 Ss —— senacour Fast Successive Approximation Conversion: 10us or 5ys ae en ne + 4] ie Buried Zener Reference for Long Term Stability and Low aseron wore (2) | | a <—peen i eka CSS Fa purren our Gain T.C.: 10ppm/°C er ro] 2 Max Nonlinearity: <+0.012% w—— gb [2] vv sueny Low Power: 880mW Typical wr eee FO [2] oan sonar Low Chip Count — High Reliability sre EF V Fae cord Industry Standard Pin Out os oe Pal ce ci me Sea “Z" Models for #12V Operation Available one US io ee Sere MIL-STD-883B Processing Available ons et Ee [ates Fy f=) re? Venti tweed ch oa ee Se Mersey ons Ca] Pen] fan evs, Negative-True Parallel or Serial Logic Outputs mul SoH = eee Short Cycle Capability i a excenour Precision +6.3V Reference for External Applications biota] Lt | W VW = ner oureav et led ES PRODUCT DESCRIPTION The AD ADC84/AD ADC85/AD5240 series devices are high- 12-bit accuracy (+0.012% FSR max) with 8.4ys, 10s speed, low-cost 10- and 12-bit successive approximation (AD ADC84/AD ADC85) and 41s, Sus (AD$240) max analog-to-digital converters that include internal clock, refer- conversion times respectively. ence and comparator. Its hybrid IC design utilizes MSI digital and linear monolithic chips in conjunction with a 12-bit The AD ADC84 and AD ADC85C specified for operation over monolithic DAC to provide modular performance and versa~ the 0 to +70°C temperature range. The AD ADC85 and tility with IC size, price and reliability. AD ADC85S are specified for the -25°C to +85°C, -55°C to Important performance characteristics of the AD ADC84/ +125°C ranges respectively. AD ADC85/AD5240 series include a maximum linearity error PRODUCT HIGHLIGHTS at +25 C of 20.012%, gain T.C. below 15ppm/"C, typical 1. The AD ADC84/AD ADC85/AD5240 series devices are power dissipation of 880mW, and conversion time of less than complete 12-bit A/D converters. No external components 10ys for the 12-bit versions. Of considerable significance in are required to perform a conversion. severe and acrospace applications is the guaranteed perfor- a - mance from -55°C to +125°C of the AD ADC85S which is 2. The AD ADC84/AD ADC85/AD5240 directly replaces also available with environmental screening. Monotonic other devices of this type with significant increases in operation of the feedback D/A converter guarantees no performance. missing codes over temperature ranges of 0 to +70°C, -25°C 3. The fast conversion rates of the AD ADC84/AD ADC85 to +85 C, and -55 C to +125 C. (10ps) and AD5240 (5s) make them an excellent choice The design of the AD ADC84/AD ADC85/AD5240 includes for applications requiring high system throughput rates. scaling resistors that provide analog input signal ranges of 4. The internal buried zener reference is laser trimmed to and value are the +6.3V precision reference, which also can is available externally and can provide up to ImA. be used for external applications, and the input buffer ampli- 74. ineegrated package construction provides high qual fier. All digital signals are fully DTL and TTL compatible, am relisbility ae weigh igh quality and the data output is negative-true and available in cither . serial or parallel form. 6. The monolithic 12-bit feedback DAC is used for reduced The AD ADC84/AD ADC8S/AD5240 series devices are avail- chip count and higher reliability. able in two different performance grades. The devices are 7. The AD ADC85S/883B and AD5240SD/883B come specified for either 10-bit accuracy (0.048% FSR max) or processed to MIL-STD-883, Class B requirements (see ADI Military Products Databook). REV. A Information furnished by Analog Devices is believed to be accurate and which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS:
AD ADC 84/AD ADC85/AD5240 —SPECIFICATIONS * 5s: chervse roa — +5V unless otherwise noted) ‘AD5240KD/ MODEL AD ADC84 AD ADC8SC_ADADC85_AD ADC85S_AD5240SD UNITS RESOLUTION 10/2 10/12 10/12 10/12 12 Bits ‘ANALOG INPUTS Voltage Ranges Unipolar 0 t0 +5, 0 t0 +10 : . . . Volts Impedance (Direct Input) Buffer Amplifier! Impedance (min) 100 . . . . Mo Bias Current 50 . . . . nA Settling Time To 0.01% for 20V Step 2 . ‘ . ‘ ws DIGITAL INPUTS? Convert Command Positive Pulse 100ns min Trailing Edge Initiates Conversion . . . . ‘Logic Loading 1 bd . * . TTL Load ‘TRANSFER CHARACTERISTICS ERROR Offset Error® Adjustable to Zero . . . ° Inherent Quantization Error 20.5 . : . . LsB Differential Linearity Error 20.5 . ‘ . ; LSB No Missing Codes Temperature Range 0 to +70 0t0 +70 -25t0 +85 -S5to+125 Oto +70/-SS to +125 °C Power Supply Sensitivity DRIFT Specification Temperature Range Oto +70 . 2510485 © -$Sto +125 Oto +70/-S5 to +125 °C Gain (max) £30 240/425 420/215 425 #30/225 ppm/c Offset Unipolar 43 bd . +5 max . ppm/c Bipolar (max)* +15 220/412 t10/27 #10 #15/47 ppm/?C Linearity (max) 33 . 23/82 . 2 ppm/°C Monotonicity GUARANTEED : : . GUARANTEED QONVERSION SPEED(MAX) gang DIGITAL OUTPUT (all codes complementary) Parallel ‘Ourput Codes” Unipolar csB . . . . Bipolar cos, crc . . . . Output Drive 2 : . . : TTL Loads Serial Data Codes (NRZ) CSB, COB . . . . Output Drive 2 : . . . ‘TTL Loads Status Logic “1” during Conversion * . . ‘ ‘Status Output Drive 2 . . . . TTL Loads Internal Clock ‘Glock Output Drive 2 7 . . . TTL Loads Frequency 1.9/1.22 : : ‘ 26 MHz INTERNAL REFERENCE VOLTAGE 6.3/15mV max . . . - Volts Max. External Current (with no degradation of specifications) 10 . : . . mA ‘Tempco of Drift, (max) ++20/max £10 typ +5 yp £5 yp +10 ppm/c POWER REQUIREMENTS Rated Voltages +5, 415 : : : . Volts Supply Drain +15V 25 max * . . 15 max mA -135V 35 max . . . 35 max mA +5V 140 max * : ‘ 100 max mA Total Power Dissipation 1500 max . ‘ ‘ 1100 max mW TEMPERATURE RANGE Specification 010 +70 . 12510485 -$5t0 4125 010 #70/-55 10 +125 °G Operating (Derated Specs) =25 to +85 . -55t0 +125 -55t0 4125 -$5 t0 +125 °C ‘Storage $5 to +125 * . . ~65 to +150 °C PACKAGE OPTION? SX DI-32F Ceramic Ceramic Ceramic Ceramic Ceramic NOTES ‘ Buffer Sevding time adds to conversion speed when buffer is connected to input. "See Table I *DTL/TTL compatible Logic “0” = 0.8V max, Logic “1"” = 2.0V min for *For £12V operation add “2” to model aumber. Input range limited to & digital output, Logic “0” = OAV max, Logic “1” = 2.4V min, maximum of =5V. «Adjustable to sero. Range. For package outline information see Package Information section, "Guaranteed at Viy = 0 volts. * Specifications same as AD ADC84. “Error shown isthe same as +1/21SB max error in % of FSR. Specifications subject to change without notice. -2- REV. A
to Comparator Input pin 22 for all ranges. As shown in Figure sensitive to external noise pick-up). 2.3ppm/°C of FSR, if the OFFSET ADJ potentiometer is set to the gain adjust pin 27 as shown in Figure 7. Figure 5. Offset Adjustment Circuit are used is shown in Figure 8.
1002 AD5240 " 4 “, y
Figure 6. Low Tempco Zero Adjustment Circuit
into an equivalent 12-bit binary number. This conversion is decision is made (keep) and Bit 3 is reset unconditionally. LSB last). The decision to keep or reject each bit is then to the Logic ‘‘0” state. VERT START signal sets the STATUS flag, indicating conver- _receiving shift register on these edges (see Figure 9). CONVERT START signal. At time to, By is reset and Bz - initiated by the trailing edge of the STATUS signal.
- THE CONVERT START PULSE WIDTH IS 100ns MIN AND MUST REMAIN LOW DURING
- 10us FOR 12BITS AND 8.4 FOR 10 BITS (AD ADC84/AD ADC85) OR Sys FOR 12 BITS
AND 4.1ys FOR 10 BITS (AD5240). 4, LSB DECISION 20ns PRIOR TO THE STATUS GOING LOW. Figure 9. Timing Diagram (Binary Code 011001110110)
DIGITAL OUTPUT DATA. AD ADC84/ Both parallel and serial data from TTL storage registers arc in. eee Short Connect Clock Gbps negative true form. Parallel data output coding is complemen- cycle Pin 14 To Rate Control Resolution Conversion Status Flag tary binary for unipolar ranges and either complementary off- Pin: Pin17To Bits (% FSR) Time (us) Reset set binary or complementary two’s complement binary, de- pending on whether BIT 1 (pin 12) or its logical inverse BIT 1 * 18 12 0.024105) tg + 40ns 4 - - 16 10 0.100 8.5 (4.1) typ * 40ns (pin 13) is used as the MSB, Parallel data becomes valid approx- ‘ 2 8 039068033) te + 4Ons imately 4Ons before the STATUS flag returns to Logic “0”, : a permitting parallel data transfer to be clocked on the “1” to Table |. Short Cycle Connections “0” transition of the STATUS flag. Serial data coding is complementary binary for unipolar input © INPUT SCALING ranges and complementary offset binary for bipolar input The AD ADC84/AD ADC85/AD5240 inputs should be scaled ranges, Serial output is by bit (MSB first, LSB last) in NRZ as close to the maximum input signal range as possible in (non-return-to-zero) format. Serial and parallel data outputs order to utilize the maximum signal resolution of the A/D change state on positive-going clock edges. Serial data is guaran- converter. Connect the input signal as shown in Table II. See teed valid 200ns after the rising clock edges, permitting serial Figure 10 for circuit detail. data to be clocked directly into a receiving register on the negative-going clock edges as shown in Figure 9. There are 13 TN | 10V SPAN negative-going clock edges in the complete 12-bit conversion @--1 @) cycle, as shown in Figure 9. The first edge shifts an invalid bit @) L-@)— ane into the register, which is shifted out on the 13th negative- 20V SPAN Re going clock edge. All serial data bits will have been correctly comin @2) transferred and be in the receiving shift register locations FROM O/A TOSAR shown at the completion of the conversion period. converten E . . Pan COMPARATOR Short Cycle Input: A Short Cycle Input, pin 14, permits the BIPOLAR (3) Viner timing cycle shown in Figure 9 to be terminated after any ANALOG number of desired bits has been converted, permitting some- ann O—. whatshorter conversion times in applications not requiring full . - a 12-bit resolution, When 12-bit resolution is required, pin 14 is Figure 10, input Scaling Circuit connected to +5V (pin 16). When 10-bit resolution is desired, For Direct For Buffered pin 14 is connected to Bit 11 output pin 2. The conversion Input Input Pin 30 cycle then terminates, and the STATUS flag resets after the Input Connect Connect Connect Connect Bit 10 decision (to +40ns in timing diagram of Figure 9). Rowe up Fin? Pin 25 sietto Top Short Cycle pin connections and associated maximum 12-, 10- and 8-bit conversion times are summarized in Table I. s10v COBorCTC — 22 Input Signal 25 2s +5V COBorCTC 22 Open 24 24 22.5V COB or CTC 22 Pin 22 24 4 OVto+SV CSB 26 Pin 22 24 24 OVt0+10V CSB 26 Open 24 24 Table II. Input Scaling Connections INPUT VOLTAGE RANGE AND LSB VALUES Analog Input Voltage Range +10V 5V #2.5V OV to +10V OV to +5V Code COB* ‘COB* coB* ‘One Least FSR 20V 10V_ 5v 10V Sv Significant 2m 2n 2" 2n 2A 2A n=12 4.88mV_ 2.44mV 1.22mV 2.44mV 1,22mv Transition Values MSB LSB 000...000**** +Full Scale +10V-3/2LSB 0 +5V -3/2LSB +2.5V-3/2LSB -+10V--3/2LSB_— +5 -3/2LSB O11...111 Mid Scale C) 0 0 +5V +2.5V 11...110 -Full Scale -10V +1/2LSB 0 -SV +1/2LSB -2.5V +1/2LSB 0+ 1/2LSB 0 +1/2LSB NOTES: *COB = Complementary Offset Binary CTC = Complementary Two's complement—obtained by using the complement of the most significant bit (HSB), HSB is available to pia 13- *CSB = Complementary Straight Binary. ****Voltages given are the nominal value for transition to the code specified. Table Ill. Input Voltages and Code Definition -6- REV. A
MICROPROCESSOR INTERFACING ane ia The fast conversion times of the AD ADC84/AD ADC85 and of] al ol : Ps | AD5240 suggest several different methods of interface to 2 wo? —_f at] de 107 microprocessors. In systems where the ADC is used for high Lal ne 2 8 sampling rates on a single signal which is to be digitally pro- a a a 2 cessed, CPU-controlled conversion may be inefficient due to anual? a = the slow cycle times of most microprocessors. It is generally oi, A a ee preferable to perform conversions independently, inserting [| yor fp | of PITT the resultant digital data directly into memory. This can be rome fy Td SET done using direct memory access (DMA) which is totally ib | of +h] ; D> n00 transparent to the CPU. Interface to user-designed DMA hard- v pe ' ware is facilitated by the guaranteed data validity on the fall- ” eT | ' ing edge of the EOC signal. ie I l I | Clearly, 12 bits of data must be broken up for interface to an a rs er ! 8-bit wide data bus. There are two possible formats: right- ut BEE oe eh ' justified and left-justified. In a right-justified system, the Fete i | 4 I i least-significant 8 bits occupy one byte and the four MSB’s wy > i st { reside in the low nybble of another byte. This format is use- seats an | > ~-Pansnal ful when the data from the ADC is being treated as a binary (behets Tyo Ks number between 0 and 4095. The left-justified format sup- i plies the eight most-significant bits in one byte and the tom evre > 4LSBs in the high nybble of another byte. The data now re- (Bees presents the fractional binary number relating the analog . signal to the full-scale voltage. An advantage to this organiza. Figure 15. AD ADC84/AD ADC85/AD5240 - 8085A Interface tion is that the most-significant eight bits can be read by the Connections Processor as a coarse indication of the true signal value. The full 12-bit word can then be read only when all 12 bits are as well as the connections to the data bus high and low byte needed. This allows faster and more efficient control of a address signals. Process: When dealing with bipolar inputs (£5V, 10V ranges), using Figure 15 shows a typical connection of an 8085-type bus, the MSB directly yields a complementary offset binary-coded using a left-justified data format for unipolar inputs, Status output. If complementary two's complement coding is desired, polling is optional, and can be read simultaneously with the it can be produced by substituting MSB (pin 13) for the MSB. 4LSBs. If it is desired to right-justify the data, pins 1 through This facilitates arithmetic operations which are subsequently 12 of the AD ADC84/AD ADC85/AD5240 should be reversed, _ performed on the ADC output data. OUTLINE DIMENSIONS Dimensions shown in inches (mm) 0.015 (0.38) ae =| F 0.120 (3.05) MAX 1,105 (28.07) fo trsersn —| 0.015 (0.38) 0.008 (0.20) — Seon zea - REV. A