ADADC71 Complete, High Resolution 16-Bit A/D Converter Data Sheet (Rev. C)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 12
Technical content
Complete, High Resolution 16-Bit A/D Converter ADADC71 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
16-bit converter with reference and clock ±0.003% maximum nonlinearity No missing codes to 14 bits Fast conversion: 35 μs (14 bit) Short cycle capability Parallel logic outputs Low power: 645 mW typical Industry standard pinout
APPLICATIONS
Medical and analytic instrumentation Precision measurement for industrial robots Automatic test equipment Multi-channel data acquisition systems Servo-control systems FUNCTIONAL BLOCK DIAGRAM 03537-001 (MSB) BIT 1 1 BIT 2 2 BIT 3 3 BIT 4 4 BIT 5 5 BIT 6 6 BIT 7 7 BIT 8 8 BIT 9 9 BIT 10 10 BIT 11 11 BIT 12 12 (LSB FOR 13 BITS) BIT 13 13 (LSB FOR 14 BITS) BIT 14 14 BIT 15 15 BIT 16 16 SHORT CYCLE32 CONVERT COMMAND31 +5V DC SUPPLY VL30 GAIN ADJUST29 +15V DC SUPPLY VCC28 COMPARATOR IN27 BIPOLAR OFFSET26 +10V25 +20V24 REF OUT (4.3V)23 ANALOG COMMON22 –15V DC SUPPLY VEE21 CLOCK OUT20 DIGITAL COMMON19 STATUS18 NC NC = NO CONNECT 16-BIT DAC 16-BIT SAR CLOCK REFERENCE COMPARATOR 7.5kΩ 3.75kΩ 3.75kΩ ADADC71 Figure 1. GENERAL DESCRIPTION The ADADC71 is a high resolution 16-bit hybrid IC analog-to- digital converter including reference, clock, and laser-trimmed thin-film components. The package is a compact 32-pin hermetic ceramic DIP . The thin-film scaling resistors allow analog input ranges of ±2.5 V , ±5 V , ±10 V , 0 to +5 V , 0 to +10 V , and 0 to +20 V . Important performance characteristics of the device are maximum linearity error of ±0.003% of FSR, and maximum conversion time of 50 μs. This performance is due to innovative design and the use of proprietary monolithic DAC chips. Laser- trimmed thin-film resistors provide the linearity and wide temperature range for no missing codes. The ADADC71 provides data in parallel format with corresponding clock and status outputs. All digital inputs and outputs are TTL-compatible. The ADADC71 used to provide data in a serial format. The serial output function is no longer available after date code 0120. PRODUCT HIGHLIGHTS 1. The ADADC71 provides 16-bit resolution with a maximum linearity error less than ±0.003% (±0.006% for J grades) at 25oC. 2. Conversion time is 35 μs typical (50 μs max) to 14 bits with short cycle capability. 3. Two binary codes are available on the ADADC71 output: complementary straight binary (CSB) for unipolar input voltage ranges, and complementary offset binary (COB) for bipolar input ranges. Complementary two’s complement (CTC) coding may be obtained by inverting Pin 1 (MSB). 4. The proprietary chips used in this hybrid design provide excellent stability over temperature, and lower chip count for improved reliability.
Rev. C | Page 2 of 12 TABLE OF CONTENTS
REVISION HISTORY
6/05—Rev. B to Rev. C
Rev. C | Page 3 of 12 SPECIFICATIONS Typical at TA =+25oC, VS = ±15 V , +5 V unless otherwise noted. Table 1. Parameter Min Typ Max Units Comment RESOLUTION 16 Bits ANALOG INPUTS Voltage Ranges Bipolar ±2.5 V ±5 V ±10 V Unipolar 0 to +5 V 0 to +10 V 0 to +20 V Impedance (Direct Input) 0 to ±5 V, ±2.5 V 1.88 KΩ 0 to ±10 V, ±5.0 V 3.75 KΩ 0 to ±20 V, ±10 V 7.50 KΩ DIGITAL INPUTS1 Convert command Trailing edge of positive 50 ns (min) pulse initiates conversion Logic Loading 1 LSTTL Load TRANSFER CHARACTERISTICS ACCURACY Gain Error ±0.12 ±0.2 % Offset Error Unipolar ±0.052 ±0.1 % of FSR3 Bipolar ±0.12 ±0.2 % of FSR Linearity Error ±0.006 % of FSR J Grade ±0.003 % of FSR K Grade Inherent Quantization Error ±1/2 LSB Differential Linearity Error ±0.003 % of FSR No Missing Codes @ 25oC4 to 14 bits Guaranteed K Grade POWER SUPPLY SENSITIVITY ±15 V dc 0.003 % of FSR/%ΔVs +5 V dc 0.001 % of FSR/%ΔVs CONVERSION TIME5 (14 BITS) 35 50 μs WARM-UP TIME 5 Minutes DRIFT Gain ±15 ppm/oC Offset Unipolar ±2 ±4 ppm of FSR/oC Bipolar ±10 ppm of FSR/oC Linearity ±2 ±3 ppm of FSR/oC Guaranteed No Missing Code Temperature Range 4 0 to 70 oC JD (13 bits), KD (14 bits)
Rev. C | Page 4 of 12 Parameter Min Typ Max Units Comment DIGITAL OUTPUT1 All codes complementary Parallel Output Codes6 Unipolar CSB Bipolar COB, CTC7 Output Drive 5 LSTTL Loads Status Logic 1 during conversion Status Output Drive 5 LSTTL Loads Internal Clock Clock Output Drive 5 LSTTL Loads Frequency 400 kHz INTERNAL REFERENCE VOLTAGE 6.3 V dc Error ±5 % Max External Current Drain with No Degradation of Specifications ±200 μA Temperature Coefficient ±10 ppm/oC POWER SUPPLY REQUIREMENTS Power Consumption 645 850 mW Rated Voltage, Analog ±15 ±0.5 V dc Rated Voltage, Digital ±5 ±0.25 V dc Supply Drain +15 V dc +16 mA Supply Drain −15 V dc −21 mA Supply Drain +5 V dc +18 mA TEMPERATURE RANGE Specification 0 to +70 °C Operating (Derated Specs) −25 to +85 °C Storage −55 to +125 °C 2 Adjustable to 0. 3 Full scale range. 4 For definition of “No Missing Codes,” refer to the Th eory of Operation section. 5 Conversion time may be shortened with short cycle set for lower resolution. 6 CSB—Complementary straight binary. COB— Complementary offset binary, CTC—Complementary twos complement. 7 CTC coding obtained by inverting MSB (Pin 1).
Rev. C | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage ±18 V Logic Supply Voltage 7 V Analog Ground to Digital Ground ±0.3 V Analog Inputs (Pin 25, Pin 24) ±VS Digital Input −0.3 V to VDD + 0.3 V Junction Temperature 175°C Storage Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensit ive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
outputs change state on positive-going clock edges. Figure 9. LSB Valid to Status Low 15-bit conversion times are summarized in Table 3. Table 3. Short Cycle Connections Table 4. See Figure 10 for circuit details. Figure 10. ADADC71 Input Scaling Circuit Table 4. Input Scaling Connections
0 V to +5 V CSB Pin 22 Pin 271 Pin 25
0 V to +10 V CSB Pin 22 Open Pin 25
0 V to +20 V CSB Pin 22 Input Signal Pin 24
1 Pin 27 is extremely sensitive to noise and should be guarded by analog common
Table 5. Transition Values vs. Calibration Codes 1 For LSB value for range and resolution used, see Ta ble 6. 2 Voltages given are the nominal value for transition to the code specified.
Table 6. Input Voltage Range and LSB Values 1 COB = complementary offset binary. 2 CTC = complementary twos complement—achieved by using an inverter to complement the most significant bit to produce (MSB). 3 CSB = complementary straight binary. ANALOG ( ) AND DIGITAL ( ) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY. Figure 11. Analog and Power Connections ANALOG ( ) AND DIGITAL ( ) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY. Figure 12. Analog and Power Connections analog range (0 for unipolar and −FS for bipolar input ranges).
0 V to +10 V Range
+5.00000 V; digital output code should be 01111111111111. Inc., 1986 Part II, Chapter 4.
Rev. C | Page 10 of 12 GROUNDING, DECOUPLING, AND LAYOUT CONSIDERATIONS Many data-acquisition components have two or more ground pins, which are not connected together within the device. These grounds are usually referred to as the DIGITAL COMMON (logic power return), ANALOG COMMON (analog power return), or analog signal ground. These grounds (Pin 19 and Pin 22) must be tied together at one point as close as possible to the converter. Ideally, a single solid analog ground plane under the converter would be desirable. Current flows through the wires and etch stripes of the circuit card, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system analog ground point and the ground pins of the ADADC71. Separate wide conductor stripe ground returns should be provided for high resolution converters to minimize noise and IR losses from the current flow in the path from the converter to the system ground point. In this way the ADADC71 supply currents and other digital logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Each of the ADADC71’s supply terminals should be capacitively decoupled as close to the ADADC71 as possible. A large value, such as 1 μF, capacitor in parallel with a 0.1 μF capacitor is usually sufficient. Analog supplies are to be bypassed to the ANALOG COMMON (analog power return) Pin 22 and the logic supply is bypassed to DIGITAL COMMON (logic power return) Pin 19. The metal cover is internally grounded with respect to the power supplies, grounds and electrical signals. Do not externally ground the cover. T/H REQUIREMENTS FOR HIGH RESOLUTION The characteristics required for high resolution track-and-hold amplifiers are low feedthrough, low pedestal shifts with changes of input signal or temperature, high linearity, low temperature coefficients, and minimal droop rate. The aperture jitter is a result of noise within the switching network that modulates the phase of the hold command, and is manifested in the variations in the value of the analog input that has been held. The aperture error which results from this jitter is directly related to the dV/dt of the analog input. The T/H amplifier slew rate determines the maximum frequency tracking rate and part of the settling time when sampling pulses and square waves. The feedthrough from input to output while in the hold mode should be less than 1 LSB. The amplitude of 1 LSB of the companion ADC for a given input range will vary from 610 μV for a 14-bit ADC using a 0 V to +10 V input range to 4.88 mV for a 12-bit ADC using a ±10 V input range. The hold mode droop rate should produce less than 1 LSB of droop in the output during the conversion time of the ADC. For 610 μV/LSB, as noted in the example above, for a 50 μs 14-bit ADC, the maximum droop rate is 610 μV/50 μs or 12 μV/μs during the 50 μs conversion period. Minimal thermal tail effects are another requirement of high resolution applications. The self-heating errors induced by the changing current levels in the output stages of T/H amps may cause more than 1 LSB of error due to thermal tail effects. The linearity error should be less than 1 LSB over the transfer function, as set by the resolution of the ADC. The T/H acquisition time and T/H settling time along with the conversion time of the ADC determines the highest sampling rate. This in turn determines the highest input signal frequency that can be sampled at twice a cycle. The maximum input frequency is constrained by the Nyquist sampling theorem to be half of the maximum throughput rate. Input frequencies higher than half the maximum throughput rate result in under sampling or aliasing errors of the input signal. The pedestal shift due to input signal changes should either be linear, to be seen as a gain error, or negligible, as with the feedthrough specification. The temperature coefficients for drift would be low enough such that full accuracy is maintained over some minimum temperature range. The droop rate and pedestal shift increases above +70 oC (+158oF). For commercial and industrial users, these shifts only appear above the highest temperatures their equipment might expect to experience. Most precision instrumentation is installed only in human inhabitable work spaces or in controlled enclosures if the area has a hostile environment. Thus, the ADADC71 used with a sample-and-hold amplifier offers high accuracy sampling in high precision applications.
times in order to synchronize the ADC with an external clock. control the ADADC71 at slower conversion times. 1EXTENAL CLK RATE CTRL (PIN 23) GROUNDED. Figure 13. Timing Diagram for Use with an External Clock
- INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE
IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE.
- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 14. 32-Lead Bottom-Brazed Ceramic Dip for Hybrid [BBDIP_H] registered trademarks are the prop erty of their respective owners.