ADA8282 (Rev. 0)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 21
Technical content
Radar Receive Path AFE: 4-Channel LNA and PGA Data Sheet ADA8282 Rev. 0 Document Feedback Information furnishe d by Ana log Dev ices is be lieved to be accurate a nd re liable. Howeve r, no respons ibility is as sumed by Ana lo g Device s f or its use , n o r f or any in fr ingemen ts of pa ten ts or o the r righ ts of th ird pa rt ies t hat may resu lt f rom its use. S pec if icat io ns s ubje ct to cha nge w ith ou t n ot ice . N o license is granted by im plica tion or otherw ise under any patent or pa tent r ig ht s of Ana lo g Dev ices . Trademarks and registered trademarks are the property of their respective owners. Tel: 781 .32 9. 47 00 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
4 channels of low noise amplifiers (LNAs) followed by programmable gain amplifiers (PGAs) Minimum −3 dB bandwidth of 5 MHz Typical –3 dB bandwidth of 42.3 MHz Typical slew rate of 28 V/µs Differential input and output Gain of 18 dB to 36 dB in 6 dB steps Selectable low noise and low power modes Input referred noise of 4.5 nV/√Hz at 18.3 mW per channel Input referred noise of 3.8 nV/√Hz at 26.5 mW per channel Input referred noise of 3.6 nV/√Hz at 34.8 mW per channel Input referred noise of 3.4 nV/√Hz at 54.8 mW per channel Channel to channel gain matching of ±0.25 dB Absolute gain error of ±0.5 dB SPI programmable Power-down mode (SPI selectable) 3.1 V p-p differential output swing when using a 3.3 V supply 32-lead, 5 mm × 5 mm LFCSP package Specified from −40°C to +125°C Qualified for automotive applications
APPLICATIONS
+OUTA –OUTA +INA –INA LNA PGA3nV√Hz +24dB –6dB TO +12dB +OUTB –OUTB +INB –INB LNA PGA3nV√Hz +24dB –6dB TO +12dB +OUTC –OUTC +INC –INC LNA PGA3nV√Hz +24dB –6dB TO +12dB +OUTD –OUTD +IND –IND LNA PGA3nV√Hz +24dB –6dB TO +12dB ADA8282 POWER MODE SPI GAIN SELECT VIO AVDD RESETSCLK SDI SDOCS 13132-001 Fi gure 1. GENERAL DESCRIPTION The ADA8282 is designed for applications that require low cost, low power, compact size, and flexibility. The ADA8282 has four parallel channels, each including an LNA and a PGA. The LNA and PGA combine to form a signal chain that features a gain range of 18 dB to 36 dB in 6 dB increments with a guaranteed minimum bandwidth of 5 MHz. Using the highest power settings, the combined input referred voltage noise of the combined LNA and PGA channel is 3.4 nV/√Hz at maximum gain. The ADA8282 can be configured in four power modes that trade off power and noise performance to optimize the overall performance according to the end application. Fabricated in an advanced complementary metal-oxide semiconductor (CMOS) process, the ADA8282 is available in a 5 mm × 5 mm, RoHS-compliant, 32-lead LFCSP . It is specified over the automotive temperature range of −40°C to +125°C.
Rev. 0 | Page 2 of 21 TABLE OF CONTENTS
REVISION HISTORY
7/15—Revision 0: Initial V ersion
Rev. 0 | Page 3 of 21 SPECIFICATIONS AVDD = 3.3 V , LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = −40°C to +125°C, PGA_BIAS_SEL = b’10, LNA_BIAS_SEL= b’10, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG CHANNEL CHARACTERISTICS Gain 18/24/30/36 dB Gain Range 18 dB Gain Error ±0.5 dB −3 dB Bandwidth VOUT = 100 mV p-p, gain = 36 dB PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 5 20.5 MHz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 5 34.2 MHz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 5 42.3 MHz PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 5 52.3 MHz Channel to Channel Gain Matching Frequencies up to 5 MHz 0.1 ±0.25 dB Channel to Channel Phase Matching1 Frequencies up to 5 MHz 0.1 ±1 Degrees Slew Rate 28 V/μs Input Referred Noise Gain = 36 dB at 2 MHz PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 4.5 nV/√Hz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 3.8 nV/√Hz PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 3.6 nV/√Hz PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 3.4 nV/√Hz 50 Ω impedance used for voltage to power conversion −156 dBm/Hz Output Referred Noise Gain = 18 dB 36 nV/√Hz Gain = 24 dB 61 nV/√Hz Gain = 30 dB 115 nV/√Hz Gain = 36 dB 218 nV/√Hz Offset Voltage Referred to Input Gain = 36 dB ±0.8 ±3 mV Referred to Output Gain = 36 dB ±50 ±200 mV SPI Offset Adjustment Resolution (Relative to Input) LNA_BIAS_SEL = b’00 113 μV LNA_BIAS_SEL = b’01 186 μV LNA_BIAS_SEL = b’10 250 μV LNA_BIAS_SEL = b’11 440 μV SPI Offset Adjustment Range (Relative to Input) LNA_BIAS_SEL = b’00 ±4 mV LNA_BIAS_SEL = b’01 ±6 mV LNA_BIAS_SEL = b’10 ±8 mV LNA_BIAS_SEL = b’11 ±14 mV Harmonic Distortion Second Harmonic (HD2) VOUT = 2 V p-p, fIN = 100 kHz −70 dBc V OUT = 100 mV p-p, fIN = 2 MHz −85 dBc Third Harmonic (HD3) VOUT = 2 V p-p, fIN = 100 kHz −85 dBc V OUT = 100 mV p-p, fIN = 2 MHz −95 dBc Intermodulation Distortion VOUT = 2 V p-p, fIN1 = 100 kHz, fIN2 = 150 kHz −72 dBc V OUT = 100 mV p-p, fIN1 = 2 MHz, fIN2 = 2.1 MHz −83 dBc Common-Mode Rejection Ratio (CMRR) −80 dB Crosstalk −105 dBc
Rev. 0 | Page 4 of 21 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Total Power Dissipation PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 73 mW PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 106 mW PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 139 mW PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 219 mW Power Dissipation per Channel 31 mW AVDD 3.0 3.6 V VIO 1.8 3.6 V IAVDD Four channels active PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 19.6 22 mA PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 29 32 mA PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 37.7 42 mA PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 60 66.3 mA One channel active 9.8 11 mA IVIO 10 12 μA Power-Down Current IAVDD and IVIO 20 100 μA Power-Down Dissipation 0.07 0.33 mW Power-Up Time Time to operational after chip is enabled 5 μs Power Supply Rejection Ratio (PSRR) At dc −80 dB At 1 MHz −80 dB INPUT Input Resistance Differential Input Resistance 1.45 1.57 1.7 kΩ Common-Mode Input Resistance 0.37 0.39 0.42 kΩ Differential Input Capacitance 10.8 12 13.2 pF OUTPUT Output Voltage Swing +OUTx (−OUTx), gain = 18 dB 3.1 V p-p +OUTx (−OUTx), gain = 24 dB, 30 dB, or 36 dB 6.3 V p-p Output Balance fIN = 100 kHz −70 dB Short-Circuit Current Per output at 25°C 205 mA Capacitive Load 20% overshoot 30 pF 1 Normalized to 0° phase matching at 25°C; see the Theory of Operation section for details. DIGITAL SPECIFICATIONS AVDD = 3.3 V , TA = −40°C to +125°C, unless otherwise noted. Table 2. Parameter Temperature Min Typ Max Unit LOGIC INPUT (CS) Logic 1 Voltage Full 1.2 VIO + 0.3 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 15 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUTS (SDI, SCLK, RESET) Logic 1 Voltage Full 1.2 VIO + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 2.5 kΩ Input Capacitance 25°C 2 pF Maximum SCLK Frequency 10 MHz LOGIC OUTPUT (SDO) Logic 1 Voltage (IOH = 800 μA) Full VIO − 0.3 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V
soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
- NIC = NO INTERNAL CONNECTION.
- TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE
PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE. Figure 2. Pin Configuration Table 5. Pin Function Descriptions 0 EPAD Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane. 1 +INA Positive LNA Analog Input for Channel A. 2 −INA Negative LNA Analog Input for Channel A. 3 +INB Positive LNA Analog Input for Channel B. 4 −INB Negative LNA Analog Input for Channel B. 5 +INC Positive LNA Analog Input for Channel C. 6 −INC Negative LNA Analog Input for Channel C. 7 +IND Positive LNA Analog Input for Channel D. 8 −IND Negative LNA Analog Input for Channel D. 10 NIC No Internal Connection. Leave this pin floating. 11 NIC No Internal Connection. Leave this pin floating. 12 NIC No Internal Connection. Leave this pin floating. 13 NIC No Internal Connection. Leave this pin floating. 14 NIC No Internal Connection. Leave this pin floating. 15 NIC No Internal Connection. Leave this pin floating. 16 AVDD 3.3 V Analog Supply. 17 −OUTD Negative Analog Output for Channel D. 18 +OUTD Positive Analog Output for Channel D. 19 −OUTC Negative Analog Output for Channel C. 20 +OUTC Positive Analog Output for Channel C. 21 −OUTB Negative Analog Output for Channel B. 22 +OUTB Positive Analog Output for Channel B. 23 −OUTA Negative Analog Output for Channel A. 24 +OUTA Positive Analog Output for Channel A. 25 AVDD 3.3 V Analog Supply. 26 VIO Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V. pulled to ground by default. A logic high triggers the reset. 32 AVDD 3.3 V Analog Supply.
b’10, unless otherwise noted. Figure 8. Input Impedance vs. Frequency
Figure 10. Input Referred Noise vs. Frequency
Rev. 0 | Page 9 of 21 200 –50 100 150 0 1000800600400200 VOUT (mV) TIME (ns) NO LOAD 5pF 33pF 66pF 100pF 13132-116 Fi gure 15. Pulse Response at V arious Output Capacitive Load s 0 100 200 300 400 500 600 700 800 900 1000 VOUT (V) TIME (ns) –1.5 –1.0 –0.5 0.5 1.0 1.5 MODE 0 MODE 1 MODE 2 MODE 3 13132-121 Fi gure 16. Larg e Signal Pu lse Re sp on se fo r V ario us L NA an d PGA Bias Modes 500 300 320 340 360 380 400 420 440 460 480 –40 –25 10 5 20 35 50 65 80 95 110 125 SHORT-CIRCUIT CURRENT (mA) TEMPERATURE (°C) 13132-118 Fi gure 17. Short-Ci rcui t Current vs. Temperature Per Channel –40 –25 10 5 20 35 50 65 80 95 110 125 SLEW RATE (V/µs) TEMPERATURE (°C) GAIN = 18dB GAIN = 24dB GAIN = 30dB GAIN = 36dB 13132-119 Fi gure 18. Output Slew Rate vs. Temperature 18 24 30 36 VOUT (V) GAIN (dB) –3.4 –3.0 –2.6 –2.2 –1.8 –1.4 –1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 13132-125 Fi gure 19. Maximum and Minimum Differ ential V O UT vs. Gain 10 100 1k 10k 100k OUTPUT VOLTAGE SWING (V) OUTPUT LOAD RESISTANCE (Ω) TA = –40°C TA = +25°C TA = +85°C 13132-117 Fi gure 20. Differ ential Output Voltage Swing vs. Output Load Resistance
Rev. 0 | Page 10 of 21 120 100 10k 100k 1M 10M 100M PSRR (dB) FREQUENCY (Hz) GAIN = 18dB GAIN = 24dB GAIN = 30dB GAIN = 36dB 13132-122 Fi gure 21. PSRR vs. Frequency at Various Gains 100 100k 1M 10M 100M CMRR (dB) FREQUENCY (Hz) GAIN = 18dB GAIN = 24dB GAIN = 30dB GAIN = 36dB 13132-123 Fi gure 22. CMRR vs. Frequency at Various Gains –140 –120 –100 –80 –60 –40 –20 10k 100k 1M 10M 100M CROSSTALK (dB) FREQUENCY (Hz) 13132-124 Fi gure 23. Crosstalk vs. Frequency –40 –25 10 5 20 35 50 65 80 95 110 125 SUPPLY CURRENT (mA) TEMPERATURE (°C) 37.55 37.60 37.65 37.70 37.75 37.80 37.85 13132-120 Fi gure 24. Quiescent Supply Current vs. Temperature
The gain setting and gains are listed in Table 7. Table 7. Gain Settings The ADA8282 gain is implemented using two internal gain stages. swing that is dependent on gain, as shown in Table 8. Table 8. Output Swing at Various Gains as required by the application. are dependent on the LNA bias mode as described in Table 9. Table 9. Offset Voltage Adjustments when designing boards with this device. single register. Then, a 13-bit address and an 8-bit data byte follow. The SPI port operates at SCLK frequencies of up to 10 MHz. Figure 26. Serial Instruction Details
variation for up to 5 MHz input signals. calibration temperature of 25°C. Figure 27. Channel to Channel Phase Mismatch, Normalized to 0° at 25°C,
5 MHz over the full temperature range for all gain settings in
Table 10. Maximum Channel to Channel Phase Mismatch over Temperature After 25°C Calibration
Table 11. Gain Settings for Two Devices in Series Figure 28. Using Two ADA8282 Devices in Series to Increase Gain
3.3 V power supply, using the EPAD as the analog ground
low with a 10 kΩ resistor and drive it with 3.3 V GPIO logic. The SPI pins can be directly connected to the SPI bus. Figure 30. Typical Component Connections
Table 12. Register Summary The INTF_CONFA configuration register is symmetric, as it is the first register written and sets the data direction (LSB first or MSB first). Table 13. INTF_CONFA Configuration Register Bit Descriptions Table 14. SOFT_RESET Configuration Register Bit Descriptions Table 15. CHIP_IDLOW Configuration Register Bit Descriptions
Table 16. CHIP_IDHI Configuration Register Bit Descriptions Table 17. Revision Configuration Register Bit Descriptions Table 18. LNA_OFFSET0 Configuration Register Bit Descriptions offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset. LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range. LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range. LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range. LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range. Table 19. LNA_OFFSET1 Configuration Register Bit Descriptions offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset. LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range. LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range. LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range. LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.
Table 20. LNA_OFFSET2 Configuration Register Bit Descriptions offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset. LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range. LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range. LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range. LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range. Table 21. LNA_OFFSET3 Configuration Register Bit Descriptions offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset. LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range. LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range. LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range. LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range. The PGA bias select register allows the user to trade off power and performance (for example, bandwidth and noise). Table 22. BIAS_SEL Configuration Register Bit Descriptions The PGA gain register allows independent gain settings for each channel. Table 23. PGA_GAIN Configuration Register Bit Descriptions
to the EN_CHAN register to enable all channels. Table 24. EN_CHAN Register Bit Descriptions
3 EN_CHANNEL3 Set to b’1 to enable Channel D, and set to b’0 to disable Channel D 0x00 RW
2 EN_CHANNEL2 Set to b’1 to enable Channel C, and set to b’0 to disable Channel C 0x00 RW
1 EN_CHANNEL1 Set to b’1 to enable Channel B, and set to b’0 to disable Channel B 0x00 RW
0 EN_CHANNEL0 Set to b’1 to enable Channel A, and set to b’0 to disable Channel A 0x00 RW
generator stays active, even when all channels are disabled. Leaving the bias generator active decreases the enable time of the device. Table 25. EN_BIAS_GEN Register Bit Descriptions GPIO_WRITE register or read by the GPIO_READ register. Table 26. SPAREWR0 Configuration Register Bit Descriptions Table 27. SPARERD0 Configuration Register Bit Descriptions
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
3.50 REF
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
Figure 31. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 2 W = Qualified for Automotive Applications. obtain the specific Automotive Reliability reports for these models. registered trademarks are the prop erty of their respective owners.